1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
13
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
16
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
19
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23
24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
26 #define NVME_NSID_ALL 0xffffffff
27
28 /* Special NSSR value, 'NVMe' */
29 #define NVME_SUBSYS_RESET 0x4E564D65
30
31 enum nvme_subsys_type {
32 /* Referral to another discovery type target subsystem */
33 NVME_NQN_DISC = 1,
34
35 /* NVME type target subsystem */
36 NVME_NQN_NVME = 2,
37
38 /* Current discovery type target subsystem */
39 NVME_NQN_CURR = 3,
40 };
41
42 enum nvme_ctrl_type {
43 NVME_CTRL_IO = 1, /* I/O controller */
44 NVME_CTRL_DISC = 2, /* Discovery controller */
45 NVME_CTRL_ADMIN = 3, /* Administrative controller */
46 };
47
48 enum nvme_dctype {
49 NVME_DCTYPE_NOT_REPORTED = 0,
50 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
51 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
52 };
53
54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
55 enum {
56 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
57 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
58 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
59 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
60 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
61 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
62 NVMF_ADDR_FAMILY_MAX,
63 };
64
65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
66 enum {
67 NVMF_TRTYPE_RDMA = 1, /* RDMA */
68 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
69 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
70 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
71 NVMF_TRTYPE_MAX,
72 };
73
74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
75 enum {
76 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
77 NVMF_TREQ_REQUIRED = 1, /* Required */
78 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
79 #define NVME_TREQ_SECURE_CHANNEL_MASK \
80 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
81
82 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
83 };
84
85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
86 * RDMA_QPTYPE field
87 */
88 enum {
89 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
90 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
91 NVMF_RDMA_QPTYPE_INVALID = 0xff,
92 };
93
94 /* RDMA Provider Type codes for Discovery Log Page entry TSAS
95 * RDMA_PRTYPE field
96 */
97 enum {
98 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
99 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
100 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
101 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
102 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
103 };
104
105 /* RDMA Connection Management Service Type codes for Discovery Log Page
106 * entry TSAS RDMA_CMS field
107 */
108 enum {
109 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
110 };
111
112 /* TSAS SECTYPE for TCP transport */
113 enum {
114 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
115 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
116 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
117 NVMF_TCP_SECTYPE_INVALID = 0xff,
118 };
119
120 #define NVME_AQ_DEPTH 32
121 #define NVME_NR_AEN_COMMANDS 1
122 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
123
124 /*
125 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
126 * NVM-Express 1.2 specification, section 4.1.2.
127 */
128 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
129
130 enum {
131 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
132 NVME_REG_VS = 0x0008, /* Version */
133 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
134 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
135 NVME_REG_CC = 0x0014, /* Controller Configuration */
136 NVME_REG_CSTS = 0x001c, /* Controller Status */
137 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
138 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
139 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
140 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
141 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
142 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
143 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
144 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
145 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
146 * Location
147 */
148 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
149 * Space Control
150 */
151 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
152 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
153 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
154 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
155 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
156 * Buffer Size
157 */
158 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
159 * Write Throughput
160 */
161 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
162 };
163
164 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
165 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
166 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
167 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
168 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
169 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
170 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
171 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
172
173 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
174 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
175
176 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
177 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
178
179 enum {
180 NVME_CMBSZ_SQS = 1 << 0,
181 NVME_CMBSZ_CQS = 1 << 1,
182 NVME_CMBSZ_LISTS = 1 << 2,
183 NVME_CMBSZ_RDS = 1 << 3,
184 NVME_CMBSZ_WDS = 1 << 4,
185
186 NVME_CMBSZ_SZ_SHIFT = 12,
187 NVME_CMBSZ_SZ_MASK = 0xfffff,
188
189 NVME_CMBSZ_SZU_SHIFT = 8,
190 NVME_CMBSZ_SZU_MASK = 0xf,
191 };
192
193 /*
194 * Submission and Completion Queue Entry Sizes for the NVM command set.
195 * (In bytes and specified as a power of two (2^n)).
196 */
197 #define NVME_ADM_SQES 6
198 #define NVME_NVM_IOSQES 6
199 #define NVME_NVM_IOCQES 4
200
201 enum {
202 NVME_CC_ENABLE = 1 << 0,
203 NVME_CC_EN_SHIFT = 0,
204 NVME_CC_CSS_SHIFT = 4,
205 NVME_CC_MPS_SHIFT = 7,
206 NVME_CC_AMS_SHIFT = 11,
207 NVME_CC_SHN_SHIFT = 14,
208 NVME_CC_IOSQES_SHIFT = 16,
209 NVME_CC_IOCQES_SHIFT = 20,
210 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
211 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
212 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
213 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
214 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
215 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
216 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
217 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
218 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
219 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
220 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
221 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
222 NVME_CC_CRIME = 1 << 24,
223 };
224
225 enum {
226 NVME_CSTS_RDY = 1 << 0,
227 NVME_CSTS_CFS = 1 << 1,
228 NVME_CSTS_NSSRO = 1 << 4,
229 NVME_CSTS_PP = 1 << 5,
230 NVME_CSTS_SHST_NORMAL = 0 << 2,
231 NVME_CSTS_SHST_OCCUR = 1 << 2,
232 NVME_CSTS_SHST_CMPLT = 2 << 2,
233 NVME_CSTS_SHST_MASK = 3 << 2,
234 };
235
236 enum {
237 NVME_CMBMSC_CRE = 1 << 0,
238 NVME_CMBMSC_CMSE = 1 << 1,
239 };
240
241 enum {
242 NVME_CAP_CSS_NVM = 1 << 0,
243 NVME_CAP_CSS_CSI = 1 << 6,
244 };
245
246 enum {
247 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
248 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
249 };
250
251 struct nvme_id_power_state {
252 __le16 max_power; /* centiwatts */
253 __u8 rsvd2;
254 __u8 flags;
255 __le32 entry_lat; /* microseconds */
256 __le32 exit_lat; /* microseconds */
257 __u8 read_tput;
258 __u8 read_lat;
259 __u8 write_tput;
260 __u8 write_lat;
261 __le16 idle_power;
262 __u8 idle_scale;
263 __u8 rsvd19;
264 __le16 active_power;
265 __u8 active_work_scale;
266 __u8 rsvd23[9];
267 };
268
269 enum {
270 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
271 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
272 };
273
274 enum nvme_ctrl_attr {
275 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
276 NVME_CTRL_ATTR_TBKAS = (1 << 6),
277 NVME_CTRL_ATTR_ELBAS = (1 << 15),
278 };
279
280 struct nvme_id_ctrl {
281 __le16 vid;
282 __le16 ssvid;
283 char sn[20];
284 char mn[40];
285 char fr[8];
286 __u8 rab;
287 __u8 ieee[3];
288 __u8 cmic;
289 __u8 mdts;
290 __le16 cntlid;
291 __le32 ver;
292 __le32 rtd3r;
293 __le32 rtd3e;
294 __le32 oaes;
295 __le32 ctratt;
296 __u8 rsvd100[11];
297 __u8 cntrltype;
298 __u8 fguid[16];
299 __le16 crdt1;
300 __le16 crdt2;
301 __le16 crdt3;
302 __u8 rsvd134[122];
303 __le16 oacs;
304 __u8 acl;
305 __u8 aerl;
306 __u8 frmw;
307 __u8 lpa;
308 __u8 elpe;
309 __u8 npss;
310 __u8 avscc;
311 __u8 apsta;
312 __le16 wctemp;
313 __le16 cctemp;
314 __le16 mtfa;
315 __le32 hmpre;
316 __le32 hmmin;
317 __u8 tnvmcap[16];
318 __u8 unvmcap[16];
319 __le32 rpmbs;
320 __le16 edstt;
321 __u8 dsto;
322 __u8 fwug;
323 __le16 kas;
324 __le16 hctma;
325 __le16 mntmt;
326 __le16 mxtmt;
327 __le32 sanicap;
328 __le32 hmminds;
329 __le16 hmmaxd;
330 __u8 rsvd338[4];
331 __u8 anatt;
332 __u8 anacap;
333 __le32 anagrpmax;
334 __le32 nanagrpid;
335 __u8 rsvd352[160];
336 __u8 sqes;
337 __u8 cqes;
338 __le16 maxcmd;
339 __le32 nn;
340 __le16 oncs;
341 __le16 fuses;
342 __u8 fna;
343 __u8 vwc;
344 __le16 awun;
345 __le16 awupf;
346 __u8 nvscc;
347 __u8 nwpc;
348 __le16 acwu;
349 __u8 rsvd534[2];
350 __le32 sgls;
351 __le32 mnan;
352 __u8 rsvd544[224];
353 char subnqn[256];
354 __u8 rsvd1024[768];
355 __le32 ioccsz;
356 __le32 iorcsz;
357 __le16 icdoff;
358 __u8 ctrattr;
359 __u8 msdbd;
360 __u8 rsvd1804[2];
361 __u8 dctype;
362 __u8 rsvd1807[241];
363 struct nvme_id_power_state psd[32];
364 __u8 vs[1024];
365 };
366
367 enum {
368 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
369 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
370 NVME_CTRL_CMIC_ANA = 1 << 3,
371 NVME_CTRL_ONCS_COMPARE = 1 << 0,
372 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
373 NVME_CTRL_ONCS_DSM = 1 << 2,
374 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
375 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
376 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
377 NVME_CTRL_VWC_PRESENT = 1 << 0,
378 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
379 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
380 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
381 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
382 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
383 NVME_CTRL_CTRATT_128_ID = 1 << 0,
384 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
385 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
386 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
387 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
388 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
389 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
390 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
391 };
392
393 struct nvme_lbaf {
394 __le16 ms;
395 __u8 ds;
396 __u8 rp;
397 };
398
399 struct nvme_id_ns {
400 __le64 nsze;
401 __le64 ncap;
402 __le64 nuse;
403 __u8 nsfeat;
404 __u8 nlbaf;
405 __u8 flbas;
406 __u8 mc;
407 __u8 dpc;
408 __u8 dps;
409 __u8 nmic;
410 __u8 rescap;
411 __u8 fpi;
412 __u8 dlfeat;
413 __le16 nawun;
414 __le16 nawupf;
415 __le16 nacwu;
416 __le16 nabsn;
417 __le16 nabo;
418 __le16 nabspf;
419 __le16 noiob;
420 __u8 nvmcap[16];
421 __le16 npwg;
422 __le16 npwa;
423 __le16 npdg;
424 __le16 npda;
425 __le16 nows;
426 __u8 rsvd74[18];
427 __le32 anagrpid;
428 __u8 rsvd96[3];
429 __u8 nsattr;
430 __le16 nvmsetid;
431 __le16 endgid;
432 __u8 nguid[16];
433 __u8 eui64[8];
434 struct nvme_lbaf lbaf[64];
435 __u8 vs[3712];
436 };
437
438 /* I/O Command Set Independent Identify Namespace Data Structure */
439 struct nvme_id_ns_cs_indep {
440 __u8 nsfeat;
441 __u8 nmic;
442 __u8 rescap;
443 __u8 fpi;
444 __le32 anagrpid;
445 __u8 nsattr;
446 __u8 rsvd9;
447 __le16 nvmsetid;
448 __le16 endgid;
449 __u8 nstat;
450 __u8 rsvd15[4081];
451 };
452
453 struct nvme_zns_lbafe {
454 __le64 zsze;
455 __u8 zdes;
456 __u8 rsvd9[7];
457 };
458
459 struct nvme_id_ns_zns {
460 __le16 zoc;
461 __le16 ozcs;
462 __le32 mar;
463 __le32 mor;
464 __le32 rrl;
465 __le32 frl;
466 __u8 rsvd20[2796];
467 struct nvme_zns_lbafe lbafe[64];
468 __u8 vs[256];
469 };
470
471 struct nvme_id_ctrl_zns {
472 __u8 zasl;
473 __u8 rsvd1[4095];
474 };
475
476 struct nvme_id_ns_nvm {
477 __le64 lbstm;
478 __u8 pic;
479 __u8 rsvd9[3];
480 __le32 elbaf[64];
481 __u8 rsvd268[3828];
482 };
483
484 enum {
485 NVME_ID_NS_NVM_STS_MASK = 0x7f,
486 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
487 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
488 NVME_ID_NS_NVM_QPIF_SHIFT = 9,
489 NVME_ID_NS_NVM_QPIF_MASK = 0xf,
490 NVME_ID_NS_NVM_QPIFS = 1 << 3,
491 };
492
493 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
494 {
495 return elbaf & NVME_ID_NS_NVM_STS_MASK;
496 }
497
498 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
499 {
500 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
501 }
502
503 static inline __u8 nvme_elbaf_qualified_guard_type(__u32 elbaf)
504 {
505 return (elbaf >> NVME_ID_NS_NVM_QPIF_SHIFT) & NVME_ID_NS_NVM_QPIF_MASK;
506 }
507
508 struct nvme_id_ctrl_nvm {
509 __u8 vsl;
510 __u8 wzsl;
511 __u8 wusl;
512 __u8 dmrl;
513 __le32 dmrsl;
514 __le64 dmsl;
515 __u8 rsvd16[4080];
516 };
517
518 enum {
519 NVME_ID_CNS_NS = 0x00,
520 NVME_ID_CNS_CTRL = 0x01,
521 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
522 NVME_ID_CNS_NS_DESC_LIST = 0x03,
523 NVME_ID_CNS_CS_NS = 0x05,
524 NVME_ID_CNS_CS_CTRL = 0x06,
525 NVME_ID_CNS_NS_CS_INDEP = 0x08,
526 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
527 NVME_ID_CNS_NS_PRESENT = 0x11,
528 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
529 NVME_ID_CNS_CTRL_LIST = 0x13,
530 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
531 NVME_ID_CNS_NS_GRANULARITY = 0x16,
532 NVME_ID_CNS_UUID_LIST = 0x17,
533 };
534
535 enum {
536 NVME_CSI_NVM = 0,
537 NVME_CSI_ZNS = 2,
538 };
539
540 enum {
541 NVME_DIR_IDENTIFY = 0x00,
542 NVME_DIR_STREAMS = 0x01,
543 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
544 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
545 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
546 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
547 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
548 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
549 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
550 NVME_DIR_ENDIR = 0x01,
551 };
552
553 enum {
554 NVME_NS_FEAT_THIN = 1 << 0,
555 NVME_NS_FEAT_ATOMICS = 1 << 1,
556 NVME_NS_FEAT_IO_OPT = 1 << 4,
557 NVME_NS_ATTR_RO = 1 << 0,
558 NVME_NS_FLBAS_LBA_MASK = 0xf,
559 NVME_NS_FLBAS_LBA_UMASK = 0x60,
560 NVME_NS_FLBAS_LBA_SHIFT = 1,
561 NVME_NS_FLBAS_META_EXT = 0x10,
562 NVME_NS_NMIC_SHARED = 1 << 0,
563 NVME_LBAF_RP_BEST = 0,
564 NVME_LBAF_RP_BETTER = 1,
565 NVME_LBAF_RP_GOOD = 2,
566 NVME_LBAF_RP_DEGRADED = 3,
567 NVME_NS_DPC_PI_LAST = 1 << 4,
568 NVME_NS_DPC_PI_FIRST = 1 << 3,
569 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
570 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
571 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
572 NVME_NS_DPS_PI_FIRST = 1 << 3,
573 NVME_NS_DPS_PI_MASK = 0x7,
574 NVME_NS_DPS_PI_TYPE1 = 1,
575 NVME_NS_DPS_PI_TYPE2 = 2,
576 NVME_NS_DPS_PI_TYPE3 = 3,
577 };
578
579 enum {
580 NVME_NSTAT_NRDY = 1 << 0,
581 };
582
583 enum {
584 NVME_NVM_NS_16B_GUARD = 0,
585 NVME_NVM_NS_32B_GUARD = 1,
586 NVME_NVM_NS_64B_GUARD = 2,
587 NVME_NVM_NS_QTYPE_GUARD = 3,
588 };
589
590 static inline __u8 nvme_lbaf_index(__u8 flbas)
591 {
592 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
593 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
594 }
595
596 /* Identify Namespace Metadata Capabilities (MC): */
597 enum {
598 NVME_MC_EXTENDED_LBA = (1 << 0),
599 NVME_MC_METADATA_PTR = (1 << 1),
600 };
601
602 struct nvme_ns_id_desc {
603 __u8 nidt;
604 __u8 nidl;
605 __le16 reserved;
606 };
607
608 #define NVME_NIDT_EUI64_LEN 8
609 #define NVME_NIDT_NGUID_LEN 16
610 #define NVME_NIDT_UUID_LEN 16
611 #define NVME_NIDT_CSI_LEN 1
612
613 enum {
614 NVME_NIDT_EUI64 = 0x01,
615 NVME_NIDT_NGUID = 0x02,
616 NVME_NIDT_UUID = 0x03,
617 NVME_NIDT_CSI = 0x04,
618 };
619
620 struct nvme_smart_log {
621 __u8 critical_warning;
622 __u8 temperature[2];
623 __u8 avail_spare;
624 __u8 spare_thresh;
625 __u8 percent_used;
626 __u8 endu_grp_crit_warn_sumry;
627 __u8 rsvd7[25];
628 __u8 data_units_read[16];
629 __u8 data_units_written[16];
630 __u8 host_reads[16];
631 __u8 host_writes[16];
632 __u8 ctrl_busy_time[16];
633 __u8 power_cycles[16];
634 __u8 power_on_hours[16];
635 __u8 unsafe_shutdowns[16];
636 __u8 media_errors[16];
637 __u8 num_err_log_entries[16];
638 __le32 warning_temp_time;
639 __le32 critical_comp_time;
640 __le16 temp_sensor[8];
641 __le32 thm_temp1_trans_count;
642 __le32 thm_temp2_trans_count;
643 __le32 thm_temp1_total_time;
644 __le32 thm_temp2_total_time;
645 __u8 rsvd232[280];
646 };
647
648 struct nvme_fw_slot_info_log {
649 __u8 afi;
650 __u8 rsvd1[7];
651 __le64 frs[7];
652 __u8 rsvd64[448];
653 };
654
655 enum {
656 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
657 NVME_CMD_EFFECTS_LBCC = 1 << 1,
658 NVME_CMD_EFFECTS_NCC = 1 << 2,
659 NVME_CMD_EFFECTS_NIC = 1 << 3,
660 NVME_CMD_EFFECTS_CCC = 1 << 4,
661 NVME_CMD_EFFECTS_CSER_MASK = GENMASK(15, 14),
662 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
663 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
664 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),
665 };
666
667 struct nvme_effects_log {
668 __le32 acs[256];
669 __le32 iocs[256];
670 __u8 resv[2048];
671 };
672
673 enum nvme_ana_state {
674 NVME_ANA_OPTIMIZED = 0x01,
675 NVME_ANA_NONOPTIMIZED = 0x02,
676 NVME_ANA_INACCESSIBLE = 0x03,
677 NVME_ANA_PERSISTENT_LOSS = 0x04,
678 NVME_ANA_CHANGE = 0x0f,
679 };
680
681 struct nvme_ana_group_desc {
682 __le32 grpid;
683 __le32 nnsids;
684 __le64 chgcnt;
685 __u8 state;
686 __u8 rsvd17[15];
687 __le32 nsids[];
688 };
689
690 /* flag for the log specific field of the ANA log */
691 #define NVME_ANA_LOG_RGO (1 << 0)
692
693 struct nvme_ana_rsp_hdr {
694 __le64 chgcnt;
695 __le16 ngrps;
696 __le16 rsvd10[3];
697 };
698
699 struct nvme_zone_descriptor {
700 __u8 zt;
701 __u8 zs;
702 __u8 za;
703 __u8 rsvd3[5];
704 __le64 zcap;
705 __le64 zslba;
706 __le64 wp;
707 __u8 rsvd32[32];
708 };
709
710 enum {
711 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
712 };
713
714 struct nvme_zone_report {
715 __le64 nr_zones;
716 __u8 resv8[56];
717 struct nvme_zone_descriptor entries[];
718 };
719
720 enum {
721 NVME_SMART_CRIT_SPARE = 1 << 0,
722 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
723 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
724 NVME_SMART_CRIT_MEDIA = 1 << 3,
725 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
726 };
727
728 enum {
729 NVME_AER_ERROR = 0,
730 NVME_AER_SMART = 1,
731 NVME_AER_NOTICE = 2,
732 NVME_AER_CSS = 6,
733 NVME_AER_VS = 7,
734 };
735
736 enum {
737 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
738 };
739
740 enum {
741 NVME_AER_NOTICE_NS_CHANGED = 0x00,
742 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
743 NVME_AER_NOTICE_ANA = 0x03,
744 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
745 };
746
747 enum {
748 NVME_AEN_BIT_NS_ATTR = 8,
749 NVME_AEN_BIT_FW_ACT = 9,
750 NVME_AEN_BIT_ANA_CHANGE = 11,
751 NVME_AEN_BIT_DISC_CHANGE = 31,
752 };
753
754 enum {
755 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
756 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
757 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
758 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
759 };
760
761 struct nvme_lba_range_type {
762 __u8 type;
763 __u8 attributes;
764 __u8 rsvd2[14];
765 __le64 slba;
766 __le64 nlb;
767 __u8 guid[16];
768 __u8 rsvd48[16];
769 };
770
771 enum {
772 NVME_LBART_TYPE_FS = 0x01,
773 NVME_LBART_TYPE_RAID = 0x02,
774 NVME_LBART_TYPE_CACHE = 0x03,
775 NVME_LBART_TYPE_SWAP = 0x04,
776
777 NVME_LBART_ATTRIB_TEMP = 1 << 0,
778 NVME_LBART_ATTRIB_HIDE = 1 << 1,
779 };
780
781 enum nvme_pr_type {
782 NVME_PR_WRITE_EXCLUSIVE = 1,
783 NVME_PR_EXCLUSIVE_ACCESS = 2,
784 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3,
785 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4,
786 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5,
787 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6,
788 };
789
790 enum nvme_eds {
791 NVME_EXTENDED_DATA_STRUCT = 0x1,
792 };
793
794 struct nvme_registered_ctrl {
795 __le16 cntlid;
796 __u8 rcsts;
797 __u8 rsvd3[5];
798 __le64 hostid;
799 __le64 rkey;
800 };
801
802 struct nvme_reservation_status {
803 __le32 gen;
804 __u8 rtype;
805 __u8 regctl[2];
806 __u8 resv5[2];
807 __u8 ptpls;
808 __u8 resv10[14];
809 struct nvme_registered_ctrl regctl_ds[];
810 };
811
812 struct nvme_registered_ctrl_ext {
813 __le16 cntlid;
814 __u8 rcsts;
815 __u8 rsvd3[5];
816 __le64 rkey;
817 __u8 hostid[16];
818 __u8 rsvd32[32];
819 };
820
821 struct nvme_reservation_status_ext {
822 __le32 gen;
823 __u8 rtype;
824 __u8 regctl[2];
825 __u8 resv5[2];
826 __u8 ptpls;
827 __u8 resv10[14];
828 __u8 rsvd24[40];
829 struct nvme_registered_ctrl_ext regctl_eds[];
830 };
831
832 /* I/O commands */
833
834 enum nvme_opcode {
835 nvme_cmd_flush = 0x00,
836 nvme_cmd_write = 0x01,
837 nvme_cmd_read = 0x02,
838 nvme_cmd_write_uncor = 0x04,
839 nvme_cmd_compare = 0x05,
840 nvme_cmd_write_zeroes = 0x08,
841 nvme_cmd_dsm = 0x09,
842 nvme_cmd_verify = 0x0c,
843 nvme_cmd_resv_register = 0x0d,
844 nvme_cmd_resv_report = 0x0e,
845 nvme_cmd_resv_acquire = 0x11,
846 nvme_cmd_resv_release = 0x15,
847 nvme_cmd_zone_mgmt_send = 0x79,
848 nvme_cmd_zone_mgmt_recv = 0x7a,
849 nvme_cmd_zone_append = 0x7d,
850 nvme_cmd_vendor_start = 0x80,
851 };
852
853 #define nvme_opcode_name(opcode) { opcode, #opcode }
854 #define show_nvm_opcode_name(val) \
855 __print_symbolic(val, \
856 nvme_opcode_name(nvme_cmd_flush), \
857 nvme_opcode_name(nvme_cmd_write), \
858 nvme_opcode_name(nvme_cmd_read), \
859 nvme_opcode_name(nvme_cmd_write_uncor), \
860 nvme_opcode_name(nvme_cmd_compare), \
861 nvme_opcode_name(nvme_cmd_write_zeroes), \
862 nvme_opcode_name(nvme_cmd_dsm), \
863 nvme_opcode_name(nvme_cmd_verify), \
864 nvme_opcode_name(nvme_cmd_resv_register), \
865 nvme_opcode_name(nvme_cmd_resv_report), \
866 nvme_opcode_name(nvme_cmd_resv_acquire), \
867 nvme_opcode_name(nvme_cmd_resv_release), \
868 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
869 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
870 nvme_opcode_name(nvme_cmd_zone_append))
871
872
873
874 /*
875 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
876 *
877 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
878 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
879 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
880 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
881 * request subtype
882 */
883 enum {
884 NVME_SGL_FMT_ADDRESS = 0x00,
885 NVME_SGL_FMT_OFFSET = 0x01,
886 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
887 NVME_SGL_FMT_INVALIDATE = 0x0f,
888 };
889
890 /*
891 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
892 *
893 * For struct nvme_sgl_desc:
894 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
895 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
896 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
897 *
898 * For struct nvme_keyed_sgl_desc:
899 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
900 *
901 * Transport-specific SGL types:
902 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
903 */
904 enum {
905 NVME_SGL_FMT_DATA_DESC = 0x00,
906 NVME_SGL_FMT_SEG_DESC = 0x02,
907 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
908 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
909 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
910 };
911
912 struct nvme_sgl_desc {
913 __le64 addr;
914 __le32 length;
915 __u8 rsvd[3];
916 __u8 type;
917 };
918
919 struct nvme_keyed_sgl_desc {
920 __le64 addr;
921 __u8 length[3];
922 __u8 key[4];
923 __u8 type;
924 };
925
926 union nvme_data_ptr {
927 struct {
928 __le64 prp1;
929 __le64 prp2;
930 };
931 struct nvme_sgl_desc sgl;
932 struct nvme_keyed_sgl_desc ksgl;
933 };
934
935 /*
936 * Lowest two bits of our flags field (FUSE field in the spec):
937 *
938 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
939 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
940 *
941 * Highest two bits in our flags field (PSDT field in the spec):
942 *
943 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
944 * If used, MPTR contains addr of single physical buffer (byte aligned).
945 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
946 * If used, MPTR contains an address of an SGL segment containing
947 * exactly 1 SGL descriptor (qword aligned).
948 */
949 enum {
950 NVME_CMD_FUSE_FIRST = (1 << 0),
951 NVME_CMD_FUSE_SECOND = (1 << 1),
952
953 NVME_CMD_SGL_METABUF = (1 << 6),
954 NVME_CMD_SGL_METASEG = (1 << 7),
955 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
956 };
957
958 struct nvme_common_command {
959 __u8 opcode;
960 __u8 flags;
961 __u16 command_id;
962 __le32 nsid;
963 __le32 cdw2[2];
964 __le64 metadata;
965 union nvme_data_ptr dptr;
966 struct_group(cdws,
967 __le32 cdw10;
968 __le32 cdw11;
969 __le32 cdw12;
970 __le32 cdw13;
971 __le32 cdw14;
972 __le32 cdw15;
973 );
974 };
975
976 struct nvme_rw_command {
977 __u8 opcode;
978 __u8 flags;
979 __u16 command_id;
980 __le32 nsid;
981 __le32 cdw2;
982 __le32 cdw3;
983 __le64 metadata;
984 union nvme_data_ptr dptr;
985 __le64 slba;
986 __le16 length;
987 __le16 control;
988 __le32 dsmgmt;
989 __le32 reftag;
990 __le16 apptag;
991 __le16 appmask;
992 };
993
994 enum {
995 NVME_RW_LR = 1 << 15,
996 NVME_RW_FUA = 1 << 14,
997 NVME_RW_APPEND_PIREMAP = 1 << 9,
998 NVME_RW_DSM_FREQ_UNSPEC = 0,
999 NVME_RW_DSM_FREQ_TYPICAL = 1,
1000 NVME_RW_DSM_FREQ_RARE = 2,
1001 NVME_RW_DSM_FREQ_READS = 3,
1002 NVME_RW_DSM_FREQ_WRITES = 4,
1003 NVME_RW_DSM_FREQ_RW = 5,
1004 NVME_RW_DSM_FREQ_ONCE = 6,
1005 NVME_RW_DSM_FREQ_PREFETCH = 7,
1006 NVME_RW_DSM_FREQ_TEMP = 8,
1007 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
1008 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
1009 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
1010 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
1011 NVME_RW_DSM_SEQ_REQ = 1 << 6,
1012 NVME_RW_DSM_COMPRESSED = 1 << 7,
1013 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
1014 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
1015 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
1016 NVME_RW_PRINFO_PRACT = 1 << 13,
1017 NVME_RW_DTYPE_STREAMS = 1 << 4,
1018 NVME_WZ_DEAC = 1 << 9,
1019 };
1020
1021 struct nvme_dsm_cmd {
1022 __u8 opcode;
1023 __u8 flags;
1024 __u16 command_id;
1025 __le32 nsid;
1026 __u64 rsvd2[2];
1027 union nvme_data_ptr dptr;
1028 __le32 nr;
1029 __le32 attributes;
1030 __u32 rsvd12[4];
1031 };
1032
1033 enum {
1034 NVME_DSMGMT_IDR = 1 << 0,
1035 NVME_DSMGMT_IDW = 1 << 1,
1036 NVME_DSMGMT_AD = 1 << 2,
1037 };
1038
1039 #define NVME_DSM_MAX_RANGES 256
1040
1041 struct nvme_dsm_range {
1042 __le32 cattr;
1043 __le32 nlb;
1044 __le64 slba;
1045 };
1046
1047 struct nvme_write_zeroes_cmd {
1048 __u8 opcode;
1049 __u8 flags;
1050 __u16 command_id;
1051 __le32 nsid;
1052 __u64 rsvd2;
1053 __le64 metadata;
1054 union nvme_data_ptr dptr;
1055 __le64 slba;
1056 __le16 length;
1057 __le16 control;
1058 __le32 dsmgmt;
1059 __le32 reftag;
1060 __le16 apptag;
1061 __le16 appmask;
1062 };
1063
1064 enum nvme_zone_mgmt_action {
1065 NVME_ZONE_CLOSE = 0x1,
1066 NVME_ZONE_FINISH = 0x2,
1067 NVME_ZONE_OPEN = 0x3,
1068 NVME_ZONE_RESET = 0x4,
1069 NVME_ZONE_OFFLINE = 0x5,
1070 NVME_ZONE_SET_DESC_EXT = 0x10,
1071 };
1072
1073 struct nvme_zone_mgmt_send_cmd {
1074 __u8 opcode;
1075 __u8 flags;
1076 __u16 command_id;
1077 __le32 nsid;
1078 __le32 cdw2[2];
1079 __le64 metadata;
1080 union nvme_data_ptr dptr;
1081 __le64 slba;
1082 __le32 cdw12;
1083 __u8 zsa;
1084 __u8 select_all;
1085 __u8 rsvd13[2];
1086 __le32 cdw14[2];
1087 };
1088
1089 struct nvme_zone_mgmt_recv_cmd {
1090 __u8 opcode;
1091 __u8 flags;
1092 __u16 command_id;
1093 __le32 nsid;
1094 __le64 rsvd2[2];
1095 union nvme_data_ptr dptr;
1096 __le64 slba;
1097 __le32 numd;
1098 __u8 zra;
1099 __u8 zrasf;
1100 __u8 pr;
1101 __u8 rsvd13;
1102 __le32 cdw14[2];
1103 };
1104
1105 enum {
1106 NVME_ZRA_ZONE_REPORT = 0,
1107 NVME_ZRASF_ZONE_REPORT_ALL = 0,
1108 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1109 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1110 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1111 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1112 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1113 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1114 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
1115 NVME_REPORT_ZONE_PARTIAL = 1,
1116 };
1117
1118 /* Features */
1119
1120 enum {
1121 NVME_TEMP_THRESH_MASK = 0xffff,
1122 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1123 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1124 };
1125
1126 struct nvme_feat_auto_pst {
1127 __le64 entries[32];
1128 };
1129
1130 enum {
1131 NVME_HOST_MEM_ENABLE = (1 << 0),
1132 NVME_HOST_MEM_RETURN = (1 << 1),
1133 };
1134
1135 struct nvme_feat_host_behavior {
1136 __u8 acre;
1137 __u8 etdas;
1138 __u8 lbafee;
1139 __u8 resv1[509];
1140 };
1141
1142 enum {
1143 NVME_ENABLE_ACRE = 1,
1144 NVME_ENABLE_LBAFEE = 1,
1145 };
1146
1147 /* Admin commands */
1148
1149 enum nvme_admin_opcode {
1150 nvme_admin_delete_sq = 0x00,
1151 nvme_admin_create_sq = 0x01,
1152 nvme_admin_get_log_page = 0x02,
1153 nvme_admin_delete_cq = 0x04,
1154 nvme_admin_create_cq = 0x05,
1155 nvme_admin_identify = 0x06,
1156 nvme_admin_abort_cmd = 0x08,
1157 nvme_admin_set_features = 0x09,
1158 nvme_admin_get_features = 0x0a,
1159 nvme_admin_async_event = 0x0c,
1160 nvme_admin_ns_mgmt = 0x0d,
1161 nvme_admin_activate_fw = 0x10,
1162 nvme_admin_download_fw = 0x11,
1163 nvme_admin_dev_self_test = 0x14,
1164 nvme_admin_ns_attach = 0x15,
1165 nvme_admin_keep_alive = 0x18,
1166 nvme_admin_directive_send = 0x19,
1167 nvme_admin_directive_recv = 0x1a,
1168 nvme_admin_virtual_mgmt = 0x1c,
1169 nvme_admin_nvme_mi_send = 0x1d,
1170 nvme_admin_nvme_mi_recv = 0x1e,
1171 nvme_admin_dbbuf = 0x7C,
1172 nvme_admin_format_nvm = 0x80,
1173 nvme_admin_security_send = 0x81,
1174 nvme_admin_security_recv = 0x82,
1175 nvme_admin_sanitize_nvm = 0x84,
1176 nvme_admin_get_lba_status = 0x86,
1177 nvme_admin_vendor_start = 0xC0,
1178 };
1179
1180 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1181 #define show_admin_opcode_name(val) \
1182 __print_symbolic(val, \
1183 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1184 nvme_admin_opcode_name(nvme_admin_create_sq), \
1185 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1186 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1187 nvme_admin_opcode_name(nvme_admin_create_cq), \
1188 nvme_admin_opcode_name(nvme_admin_identify), \
1189 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1190 nvme_admin_opcode_name(nvme_admin_set_features), \
1191 nvme_admin_opcode_name(nvme_admin_get_features), \
1192 nvme_admin_opcode_name(nvme_admin_async_event), \
1193 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1194 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1195 nvme_admin_opcode_name(nvme_admin_download_fw), \
1196 nvme_admin_opcode_name(nvme_admin_dev_self_test), \
1197 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1198 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1199 nvme_admin_opcode_name(nvme_admin_directive_send), \
1200 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1201 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \
1202 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \
1203 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \
1204 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1205 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1206 nvme_admin_opcode_name(nvme_admin_security_send), \
1207 nvme_admin_opcode_name(nvme_admin_security_recv), \
1208 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1209 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1210
1211 enum {
1212 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1213 NVME_CQ_IRQ_ENABLED = (1 << 1),
1214 NVME_SQ_PRIO_URGENT = (0 << 1),
1215 NVME_SQ_PRIO_HIGH = (1 << 1),
1216 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1217 NVME_SQ_PRIO_LOW = (3 << 1),
1218 NVME_FEAT_ARBITRATION = 0x01,
1219 NVME_FEAT_POWER_MGMT = 0x02,
1220 NVME_FEAT_LBA_RANGE = 0x03,
1221 NVME_FEAT_TEMP_THRESH = 0x04,
1222 NVME_FEAT_ERR_RECOVERY = 0x05,
1223 NVME_FEAT_VOLATILE_WC = 0x06,
1224 NVME_FEAT_NUM_QUEUES = 0x07,
1225 NVME_FEAT_IRQ_COALESCE = 0x08,
1226 NVME_FEAT_IRQ_CONFIG = 0x09,
1227 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1228 NVME_FEAT_ASYNC_EVENT = 0x0b,
1229 NVME_FEAT_AUTO_PST = 0x0c,
1230 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1231 NVME_FEAT_TIMESTAMP = 0x0e,
1232 NVME_FEAT_KATO = 0x0f,
1233 NVME_FEAT_HCTM = 0x10,
1234 NVME_FEAT_NOPSC = 0x11,
1235 NVME_FEAT_RRL = 0x12,
1236 NVME_FEAT_PLM_CONFIG = 0x13,
1237 NVME_FEAT_PLM_WINDOW = 0x14,
1238 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1239 NVME_FEAT_SANITIZE = 0x17,
1240 NVME_FEAT_SW_PROGRESS = 0x80,
1241 NVME_FEAT_HOST_ID = 0x81,
1242 NVME_FEAT_RESV_MASK = 0x82,
1243 NVME_FEAT_RESV_PERSIST = 0x83,
1244 NVME_FEAT_WRITE_PROTECT = 0x84,
1245 NVME_FEAT_VENDOR_START = 0xC0,
1246 NVME_FEAT_VENDOR_END = 0xFF,
1247 NVME_LOG_ERROR = 0x01,
1248 NVME_LOG_SMART = 0x02,
1249 NVME_LOG_FW_SLOT = 0x03,
1250 NVME_LOG_CHANGED_NS = 0x04,
1251 NVME_LOG_CMD_EFFECTS = 0x05,
1252 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1253 NVME_LOG_TELEMETRY_HOST = 0x07,
1254 NVME_LOG_TELEMETRY_CTRL = 0x08,
1255 NVME_LOG_ENDURANCE_GROUP = 0x09,
1256 NVME_LOG_ANA = 0x0c,
1257 NVME_LOG_DISC = 0x70,
1258 NVME_LOG_RESERVATION = 0x80,
1259 NVME_FWACT_REPL = (0 << 3),
1260 NVME_FWACT_REPL_ACTV = (1 << 3),
1261 NVME_FWACT_ACTV = (2 << 3),
1262 };
1263
1264 /* NVMe Namespace Write Protect State */
1265 enum {
1266 NVME_NS_NO_WRITE_PROTECT = 0,
1267 NVME_NS_WRITE_PROTECT,
1268 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1269 NVME_NS_WRITE_PROTECT_PERMANENT,
1270 };
1271
1272 #define NVME_MAX_CHANGED_NAMESPACES 1024
1273
1274 struct nvme_identify {
1275 __u8 opcode;
1276 __u8 flags;
1277 __u16 command_id;
1278 __le32 nsid;
1279 __u64 rsvd2[2];
1280 union nvme_data_ptr dptr;
1281 __u8 cns;
1282 __u8 rsvd3;
1283 __le16 ctrlid;
1284 __u8 rsvd11[3];
1285 __u8 csi;
1286 __u32 rsvd12[4];
1287 };
1288
1289 #define NVME_IDENTIFY_DATA_SIZE 4096
1290
1291 struct nvme_features {
1292 __u8 opcode;
1293 __u8 flags;
1294 __u16 command_id;
1295 __le32 nsid;
1296 __u64 rsvd2[2];
1297 union nvme_data_ptr dptr;
1298 __le32 fid;
1299 __le32 dword11;
1300 __le32 dword12;
1301 __le32 dword13;
1302 __le32 dword14;
1303 __le32 dword15;
1304 };
1305
1306 struct nvme_host_mem_buf_desc {
1307 __le64 addr;
1308 __le32 size;
1309 __u32 rsvd;
1310 };
1311
1312 struct nvme_create_cq {
1313 __u8 opcode;
1314 __u8 flags;
1315 __u16 command_id;
1316 __u32 rsvd1[5];
1317 __le64 prp1;
1318 __u64 rsvd8;
1319 __le16 cqid;
1320 __le16 qsize;
1321 __le16 cq_flags;
1322 __le16 irq_vector;
1323 __u32 rsvd12[4];
1324 };
1325
1326 struct nvme_create_sq {
1327 __u8 opcode;
1328 __u8 flags;
1329 __u16 command_id;
1330 __u32 rsvd1[5];
1331 __le64 prp1;
1332 __u64 rsvd8;
1333 __le16 sqid;
1334 __le16 qsize;
1335 __le16 sq_flags;
1336 __le16 cqid;
1337 __u32 rsvd12[4];
1338 };
1339
1340 struct nvme_delete_queue {
1341 __u8 opcode;
1342 __u8 flags;
1343 __u16 command_id;
1344 __u32 rsvd1[9];
1345 __le16 qid;
1346 __u16 rsvd10;
1347 __u32 rsvd11[5];
1348 };
1349
1350 struct nvme_abort_cmd {
1351 __u8 opcode;
1352 __u8 flags;
1353 __u16 command_id;
1354 __u32 rsvd1[9];
1355 __le16 sqid;
1356 __u16 cid;
1357 __u32 rsvd11[5];
1358 };
1359
1360 struct nvme_download_firmware {
1361 __u8 opcode;
1362 __u8 flags;
1363 __u16 command_id;
1364 __u32 rsvd1[5];
1365 union nvme_data_ptr dptr;
1366 __le32 numd;
1367 __le32 offset;
1368 __u32 rsvd12[4];
1369 };
1370
1371 struct nvme_format_cmd {
1372 __u8 opcode;
1373 __u8 flags;
1374 __u16 command_id;
1375 __le32 nsid;
1376 __u64 rsvd2[4];
1377 __le32 cdw10;
1378 __u32 rsvd11[5];
1379 };
1380
1381 struct nvme_get_log_page_command {
1382 __u8 opcode;
1383 __u8 flags;
1384 __u16 command_id;
1385 __le32 nsid;
1386 __u64 rsvd2[2];
1387 union nvme_data_ptr dptr;
1388 __u8 lid;
1389 __u8 lsp; /* upper 4 bits reserved */
1390 __le16 numdl;
1391 __le16 numdu;
1392 __u16 rsvd11;
1393 union {
1394 struct {
1395 __le32 lpol;
1396 __le32 lpou;
1397 };
1398 __le64 lpo;
1399 };
1400 __u8 rsvd14[3];
1401 __u8 csi;
1402 __u32 rsvd15;
1403 };
1404
1405 struct nvme_directive_cmd {
1406 __u8 opcode;
1407 __u8 flags;
1408 __u16 command_id;
1409 __le32 nsid;
1410 __u64 rsvd2[2];
1411 union nvme_data_ptr dptr;
1412 __le32 numd;
1413 __u8 doper;
1414 __u8 dtype;
1415 __le16 dspec;
1416 __u8 endir;
1417 __u8 tdtype;
1418 __u16 rsvd15;
1419
1420 __u32 rsvd16[3];
1421 };
1422
1423 /*
1424 * Fabrics subcommands.
1425 */
1426 enum nvmf_fabrics_opcode {
1427 nvme_fabrics_command = 0x7f,
1428 };
1429
1430 enum nvmf_capsule_command {
1431 nvme_fabrics_type_property_set = 0x00,
1432 nvme_fabrics_type_connect = 0x01,
1433 nvme_fabrics_type_property_get = 0x04,
1434 nvme_fabrics_type_auth_send = 0x05,
1435 nvme_fabrics_type_auth_receive = 0x06,
1436 };
1437
1438 #define nvme_fabrics_type_name(type) { type, #type }
1439 #define show_fabrics_type_name(type) \
1440 __print_symbolic(type, \
1441 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1442 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1443 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1444 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1445 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1446
1447 /*
1448 * If not fabrics command, fctype will be ignored.
1449 */
1450 #define show_opcode_name(qid, opcode, fctype) \
1451 ((opcode) == nvme_fabrics_command ? \
1452 show_fabrics_type_name(fctype) : \
1453 ((qid) ? \
1454 show_nvm_opcode_name(opcode) : \
1455 show_admin_opcode_name(opcode)))
1456
1457 struct nvmf_common_command {
1458 __u8 opcode;
1459 __u8 resv1;
1460 __u16 command_id;
1461 __u8 fctype;
1462 __u8 resv2[35];
1463 __u8 ts[24];
1464 };
1465
1466 /*
1467 * The legal cntlid range a NVMe Target will provide.
1468 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1469 * Devices based on earlier specs did not have the subsystem concept;
1470 * therefore, those devices had their cntlid value set to 0 as a result.
1471 */
1472 #define NVME_CNTLID_MIN 1
1473 #define NVME_CNTLID_MAX 0xffef
1474 #define NVME_CNTLID_DYNAMIC 0xffff
1475
1476 #define MAX_DISC_LOGS 255
1477
1478 /* Discovery log page entry flags (EFLAGS): */
1479 enum {
1480 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1481 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1482 };
1483
1484 /* Discovery log page entry */
1485 struct nvmf_disc_rsp_page_entry {
1486 __u8 trtype;
1487 __u8 adrfam;
1488 __u8 subtype;
1489 __u8 treq;
1490 __le16 portid;
1491 __le16 cntlid;
1492 __le16 asqsz;
1493 __le16 eflags;
1494 __u8 resv10[20];
1495 char trsvcid[NVMF_TRSVCID_SIZE];
1496 __u8 resv64[192];
1497 char subnqn[NVMF_NQN_FIELD_LEN];
1498 char traddr[NVMF_TRADDR_SIZE];
1499 union tsas {
1500 char common[NVMF_TSAS_SIZE];
1501 struct rdma {
1502 __u8 qptype;
1503 __u8 prtype;
1504 __u8 cms;
1505 __u8 resv3[5];
1506 __u16 pkey;
1507 __u8 resv10[246];
1508 } rdma;
1509 struct tcp {
1510 __u8 sectype;
1511 } tcp;
1512 } tsas;
1513 };
1514
1515 /* Discovery log page header */
1516 struct nvmf_disc_rsp_page_hdr {
1517 __le64 genctr;
1518 __le64 numrec;
1519 __le16 recfmt;
1520 __u8 resv14[1006];
1521 struct nvmf_disc_rsp_page_entry entries[];
1522 };
1523
1524 enum {
1525 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1526 };
1527
1528 struct nvmf_connect_command {
1529 __u8 opcode;
1530 __u8 resv1;
1531 __u16 command_id;
1532 __u8 fctype;
1533 __u8 resv2[19];
1534 union nvme_data_ptr dptr;
1535 __le16 recfmt;
1536 __le16 qid;
1537 __le16 sqsize;
1538 __u8 cattr;
1539 __u8 resv3;
1540 __le32 kato;
1541 __u8 resv4[12];
1542 };
1543
1544 enum {
1545 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1546 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
1547 };
1548
1549 struct nvmf_connect_data {
1550 uuid_t hostid;
1551 __le16 cntlid;
1552 char resv4[238];
1553 char subsysnqn[NVMF_NQN_FIELD_LEN];
1554 char hostnqn[NVMF_NQN_FIELD_LEN];
1555 char resv5[256];
1556 };
1557
1558 struct nvmf_property_set_command {
1559 __u8 opcode;
1560 __u8 resv1;
1561 __u16 command_id;
1562 __u8 fctype;
1563 __u8 resv2[35];
1564 __u8 attrib;
1565 __u8 resv3[3];
1566 __le32 offset;
1567 __le64 value;
1568 __u8 resv4[8];
1569 };
1570
1571 struct nvmf_property_get_command {
1572 __u8 opcode;
1573 __u8 resv1;
1574 __u16 command_id;
1575 __u8 fctype;
1576 __u8 resv2[35];
1577 __u8 attrib;
1578 __u8 resv3[3];
1579 __le32 offset;
1580 __u8 resv4[16];
1581 };
1582
1583 struct nvmf_auth_common_command {
1584 __u8 opcode;
1585 __u8 resv1;
1586 __u16 command_id;
1587 __u8 fctype;
1588 __u8 resv2[19];
1589 union nvme_data_ptr dptr;
1590 __u8 resv3;
1591 __u8 spsp0;
1592 __u8 spsp1;
1593 __u8 secp;
1594 __le32 al_tl;
1595 __u8 resv4[16];
1596 };
1597
1598 struct nvmf_auth_send_command {
1599 __u8 opcode;
1600 __u8 resv1;
1601 __u16 command_id;
1602 __u8 fctype;
1603 __u8 resv2[19];
1604 union nvme_data_ptr dptr;
1605 __u8 resv3;
1606 __u8 spsp0;
1607 __u8 spsp1;
1608 __u8 secp;
1609 __le32 tl;
1610 __u8 resv4[16];
1611 };
1612
1613 struct nvmf_auth_receive_command {
1614 __u8 opcode;
1615 __u8 resv1;
1616 __u16 command_id;
1617 __u8 fctype;
1618 __u8 resv2[19];
1619 union nvme_data_ptr dptr;
1620 __u8 resv3;
1621 __u8 spsp0;
1622 __u8 spsp1;
1623 __u8 secp;
1624 __le32 al;
1625 __u8 resv4[16];
1626 };
1627
1628 /* Value for secp */
1629 enum {
1630 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1631 };
1632
1633 /* Defined value for auth_type */
1634 enum {
1635 NVME_AUTH_COMMON_MESSAGES = 0x00,
1636 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1637 };
1638
1639 /* Defined messages for auth_id */
1640 enum {
1641 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1642 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1643 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1644 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1645 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1646 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1647 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1648 };
1649
1650 struct nvmf_auth_dhchap_protocol_descriptor {
1651 __u8 authid;
1652 __u8 rsvd;
1653 __u8 halen;
1654 __u8 dhlen;
1655 __u8 idlist[60];
1656 };
1657
1658 enum {
1659 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1660 };
1661
1662 /* Defined hash functions for DH-HMAC-CHAP authentication */
1663 enum {
1664 NVME_AUTH_HASH_SHA256 = 0x01,
1665 NVME_AUTH_HASH_SHA384 = 0x02,
1666 NVME_AUTH_HASH_SHA512 = 0x03,
1667 NVME_AUTH_HASH_INVALID = 0xff,
1668 };
1669
1670 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1671 enum {
1672 NVME_AUTH_DHGROUP_NULL = 0x00,
1673 NVME_AUTH_DHGROUP_2048 = 0x01,
1674 NVME_AUTH_DHGROUP_3072 = 0x02,
1675 NVME_AUTH_DHGROUP_4096 = 0x03,
1676 NVME_AUTH_DHGROUP_6144 = 0x04,
1677 NVME_AUTH_DHGROUP_8192 = 0x05,
1678 NVME_AUTH_DHGROUP_INVALID = 0xff,
1679 };
1680
1681 union nvmf_auth_protocol {
1682 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1683 };
1684
1685 struct nvmf_auth_dhchap_negotiate_data {
1686 __u8 auth_type;
1687 __u8 auth_id;
1688 __le16 rsvd;
1689 __le16 t_id;
1690 __u8 sc_c;
1691 __u8 napd;
1692 union nvmf_auth_protocol auth_protocol[];
1693 };
1694
1695 struct nvmf_auth_dhchap_challenge_data {
1696 __u8 auth_type;
1697 __u8 auth_id;
1698 __u16 rsvd1;
1699 __le16 t_id;
1700 __u8 hl;
1701 __u8 rsvd2;
1702 __u8 hashid;
1703 __u8 dhgid;
1704 __le16 dhvlen;
1705 __le32 seqnum;
1706 /* 'hl' bytes of challenge value */
1707 __u8 cval[];
1708 /* followed by 'dhvlen' bytes of DH value */
1709 };
1710
1711 struct nvmf_auth_dhchap_reply_data {
1712 __u8 auth_type;
1713 __u8 auth_id;
1714 __le16 rsvd1;
1715 __le16 t_id;
1716 __u8 hl;
1717 __u8 rsvd2;
1718 __u8 cvalid;
1719 __u8 rsvd3;
1720 __le16 dhvlen;
1721 __le32 seqnum;
1722 /* 'hl' bytes of response data */
1723 __u8 rval[];
1724 /* followed by 'hl' bytes of Challenge value */
1725 /* followed by 'dhvlen' bytes of DH value */
1726 };
1727
1728 enum {
1729 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1730 };
1731
1732 struct nvmf_auth_dhchap_success1_data {
1733 __u8 auth_type;
1734 __u8 auth_id;
1735 __le16 rsvd1;
1736 __le16 t_id;
1737 __u8 hl;
1738 __u8 rsvd2;
1739 __u8 rvalid;
1740 __u8 rsvd3[7];
1741 /* 'hl' bytes of response value */
1742 __u8 rval[];
1743 };
1744
1745 struct nvmf_auth_dhchap_success2_data {
1746 __u8 auth_type;
1747 __u8 auth_id;
1748 __le16 rsvd1;
1749 __le16 t_id;
1750 __u8 rsvd2[10];
1751 };
1752
1753 struct nvmf_auth_dhchap_failure_data {
1754 __u8 auth_type;
1755 __u8 auth_id;
1756 __le16 rsvd1;
1757 __le16 t_id;
1758 __u8 rescode;
1759 __u8 rescode_exp;
1760 };
1761
1762 enum {
1763 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1764 };
1765
1766 enum {
1767 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1768 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1769 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1770 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1771 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1772 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1773 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1774 };
1775
1776
1777 struct nvme_dbbuf {
1778 __u8 opcode;
1779 __u8 flags;
1780 __u16 command_id;
1781 __u32 rsvd1[5];
1782 __le64 prp1;
1783 __le64 prp2;
1784 __u32 rsvd12[6];
1785 };
1786
1787 struct streams_directive_params {
1788 __le16 msl;
1789 __le16 nssa;
1790 __le16 nsso;
1791 __u8 rsvd[10];
1792 __le32 sws;
1793 __le16 sgs;
1794 __le16 nsa;
1795 __le16 nso;
1796 __u8 rsvd2[6];
1797 };
1798
1799 struct nvme_command {
1800 union {
1801 struct nvme_common_command common;
1802 struct nvme_rw_command rw;
1803 struct nvme_identify identify;
1804 struct nvme_features features;
1805 struct nvme_create_cq create_cq;
1806 struct nvme_create_sq create_sq;
1807 struct nvme_delete_queue delete_queue;
1808 struct nvme_download_firmware dlfw;
1809 struct nvme_format_cmd format;
1810 struct nvme_dsm_cmd dsm;
1811 struct nvme_write_zeroes_cmd write_zeroes;
1812 struct nvme_zone_mgmt_send_cmd zms;
1813 struct nvme_zone_mgmt_recv_cmd zmr;
1814 struct nvme_abort_cmd abort;
1815 struct nvme_get_log_page_command get_log_page;
1816 struct nvmf_common_command fabrics;
1817 struct nvmf_connect_command connect;
1818 struct nvmf_property_set_command prop_set;
1819 struct nvmf_property_get_command prop_get;
1820 struct nvmf_auth_common_command auth_common;
1821 struct nvmf_auth_send_command auth_send;
1822 struct nvmf_auth_receive_command auth_receive;
1823 struct nvme_dbbuf dbbuf;
1824 struct nvme_directive_cmd directive;
1825 };
1826 };
1827
1828 static inline bool nvme_is_fabrics(const struct nvme_command *cmd)
1829 {
1830 return cmd->common.opcode == nvme_fabrics_command;
1831 }
1832
1833 struct nvme_error_slot {
1834 __le64 error_count;
1835 __le16 sqid;
1836 __le16 cmdid;
1837 __le16 status_field;
1838 __le16 param_error_location;
1839 __le64 lba;
1840 __le32 nsid;
1841 __u8 vs;
1842 __u8 resv[3];
1843 __le64 cs;
1844 __u8 resv2[24];
1845 };
1846
1847 static inline bool nvme_is_write(const struct nvme_command *cmd)
1848 {
1849 /*
1850 * What a mess...
1851 *
1852 * Why can't we simply have a Fabrics In and Fabrics out command?
1853 */
1854 if (unlikely(nvme_is_fabrics(cmd)))
1855 return cmd->fabrics.fctype & 1;
1856 return cmd->common.opcode & 1;
1857 }
1858
1859 enum {
1860 /*
1861 * Generic Command Status:
1862 */
1863 NVME_SCT_GENERIC = 0x0,
1864 NVME_SC_SUCCESS = 0x0,
1865 NVME_SC_INVALID_OPCODE = 0x1,
1866 NVME_SC_INVALID_FIELD = 0x2,
1867 NVME_SC_CMDID_CONFLICT = 0x3,
1868 NVME_SC_DATA_XFER_ERROR = 0x4,
1869 NVME_SC_POWER_LOSS = 0x5,
1870 NVME_SC_INTERNAL = 0x6,
1871 NVME_SC_ABORT_REQ = 0x7,
1872 NVME_SC_ABORT_QUEUE = 0x8,
1873 NVME_SC_FUSED_FAIL = 0x9,
1874 NVME_SC_FUSED_MISSING = 0xa,
1875 NVME_SC_INVALID_NS = 0xb,
1876 NVME_SC_CMD_SEQ_ERROR = 0xc,
1877 NVME_SC_SGL_INVALID_LAST = 0xd,
1878 NVME_SC_SGL_INVALID_COUNT = 0xe,
1879 NVME_SC_SGL_INVALID_DATA = 0xf,
1880 NVME_SC_SGL_INVALID_METADATA = 0x10,
1881 NVME_SC_SGL_INVALID_TYPE = 0x11,
1882 NVME_SC_CMB_INVALID_USE = 0x12,
1883 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1884 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1885 NVME_SC_OP_DENIED = 0x15,
1886 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1887 NVME_SC_RESERVED = 0x17,
1888 NVME_SC_HOST_ID_INCONSIST = 0x18,
1889 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1890 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1891 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1892 NVME_SC_SANITIZE_FAILED = 0x1C,
1893 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1894 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1895 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1896 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1897 NVME_SC_CMD_INTERRUPTED = 0x21,
1898 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1899 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1900 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1901
1902 NVME_SC_LBA_RANGE = 0x80,
1903 NVME_SC_CAP_EXCEEDED = 0x81,
1904 NVME_SC_NS_NOT_READY = 0x82,
1905 NVME_SC_RESERVATION_CONFLICT = 0x83,
1906 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1907
1908 /*
1909 * Command Specific Status:
1910 */
1911 NVME_SCT_COMMAND_SPECIFIC = 0x100,
1912 NVME_SC_CQ_INVALID = 0x100,
1913 NVME_SC_QID_INVALID = 0x101,
1914 NVME_SC_QUEUE_SIZE = 0x102,
1915 NVME_SC_ABORT_LIMIT = 0x103,
1916 NVME_SC_ABORT_MISSING = 0x104,
1917 NVME_SC_ASYNC_LIMIT = 0x105,
1918 NVME_SC_FIRMWARE_SLOT = 0x106,
1919 NVME_SC_FIRMWARE_IMAGE = 0x107,
1920 NVME_SC_INVALID_VECTOR = 0x108,
1921 NVME_SC_INVALID_LOG_PAGE = 0x109,
1922 NVME_SC_INVALID_FORMAT = 0x10a,
1923 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1924 NVME_SC_INVALID_QUEUE = 0x10c,
1925 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1926 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1927 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1928 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1929 NVME_SC_FW_NEEDS_RESET = 0x111,
1930 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1931 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1932 NVME_SC_OVERLAPPING_RANGE = 0x114,
1933 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1934 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1935 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1936 NVME_SC_NS_IS_PRIVATE = 0x119,
1937 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1938 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1939 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1940 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1941 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1942 NVME_SC_CTRL_ID_INVALID = 0x11f,
1943 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1944 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1945 NVME_SC_RES_ID_INVALID = 0x122,
1946 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1947 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1948 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1949
1950 /*
1951 * I/O Command Set Specific - NVM commands:
1952 */
1953 NVME_SC_BAD_ATTRIBUTES = 0x180,
1954 NVME_SC_INVALID_PI = 0x181,
1955 NVME_SC_READ_ONLY = 0x182,
1956 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1957
1958 /*
1959 * I/O Command Set Specific - Fabrics commands:
1960 */
1961 NVME_SC_CONNECT_FORMAT = 0x180,
1962 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1963 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1964 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1965 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1966
1967 NVME_SC_DISCOVERY_RESTART = 0x190,
1968 NVME_SC_AUTH_REQUIRED = 0x191,
1969
1970 /*
1971 * I/O Command Set Specific - Zoned commands:
1972 */
1973 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1974 NVME_SC_ZONE_FULL = 0x1b9,
1975 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1976 NVME_SC_ZONE_OFFLINE = 0x1bb,
1977 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1978 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1979 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1980 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1981
1982 /*
1983 * Media and Data Integrity Errors:
1984 */
1985 NVME_SCT_MEDIA_ERROR = 0x200,
1986 NVME_SC_WRITE_FAULT = 0x280,
1987 NVME_SC_READ_ERROR = 0x281,
1988 NVME_SC_GUARD_CHECK = 0x282,
1989 NVME_SC_APPTAG_CHECK = 0x283,
1990 NVME_SC_REFTAG_CHECK = 0x284,
1991 NVME_SC_COMPARE_FAILED = 0x285,
1992 NVME_SC_ACCESS_DENIED = 0x286,
1993 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1994
1995 /*
1996 * Path-related Errors:
1997 */
1998 NVME_SCT_PATH = 0x300,
1999 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
2000 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
2001 NVME_SC_ANA_INACCESSIBLE = 0x302,
2002 NVME_SC_ANA_TRANSITION = 0x303,
2003 NVME_SC_CTRL_PATH_ERROR = 0x360,
2004 NVME_SC_HOST_PATH_ERROR = 0x370,
2005 NVME_SC_HOST_ABORTED_CMD = 0x371,
2006
2007 NVME_SC_MASK = 0x00ff, /* Status Code */
2008 NVME_SCT_MASK = 0x0700, /* Status Code Type */
2009 NVME_SCT_SC_MASK = NVME_SCT_MASK | NVME_SC_MASK,
2010
2011 NVME_STATUS_CRD = 0x1800, /* Command Retry Delayed */
2012 NVME_STATUS_MORE = 0x2000,
2013 NVME_STATUS_DNR = 0x4000, /* Do Not Retry */
2014 };
2015
2016 #define NVME_SCT(status) ((status) >> 8 & 7)
2017
2018 struct nvme_completion {
2019 /*
2020 * Used by Admin and Fabrics commands to return data:
2021 */
2022 union nvme_result {
2023 __le16 u16;
2024 __le32 u32;
2025 __le64 u64;
2026 } result;
2027 __le16 sq_head; /* how much of this queue may be reclaimed */
2028 __le16 sq_id; /* submission queue that generated this entry */
2029 __u16 command_id; /* of the command which completed */
2030 __le16 status; /* did the command fail, and if so, why? */
2031 };
2032
2033 #define NVME_VS(major, minor, tertiary) \
2034 (((major) << 16) | ((minor) << 8) | (tertiary))
2035
2036 #define NVME_MAJOR(ver) ((ver) >> 16)
2037 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
2038 #define NVME_TERTIARY(ver) ((ver) & 0xff)
2039
2040 #endif /* _LINUX_NVME_H */
2041
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