1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26 #include <linux/args.h>
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <linux/msi_api.h>
42 #include <uapi/linux/pci.h>
43
44 #include <linux/pci_ids.h>
45
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 8
55
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
58
59 /*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
70 */
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
75 /* pci_slot represents a physical slot */
76 struct pci_slot {
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
82 };
83
84 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 {
86 return kobject_name(&slot->kobj);
87 }
88
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
90 enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93 };
94
95 /* For PCI devices, the region numbers are assigned this way: */
96 enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108 #endif
109
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_BRIDGE_RESOURCE_NUM 4
123
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
129 /* Total resources associated with a PCI device */
130 PCI_NUM_RESOURCES,
131
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
134 };
135
136 /**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147 enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153 };
154
155 /* The number of legacy PCI INTx interrupts */
156 #define PCI_NUM_INTX 4
157
158 /*
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
162 */
163 #define PCI_ERROR_RESPONSE (~0ULL)
164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
166
167 /*
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
170 */
171 typedef int __bitwise pci_power_t;
172
173 #define PCI_D0 ((pci_power_t __force) 0)
174 #define PCI_D1 ((pci_power_t __force) 1)
175 #define PCI_D2 ((pci_power_t __force) 2)
176 #define PCI_D3hot ((pci_power_t __force) 3)
177 #define PCI_D3cold ((pci_power_t __force) 4)
178 #define PCI_UNKNOWN ((pci_power_t __force) 5)
179 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
180
181 /* Remember to update this when the list above changes! */
182 extern const char *pci_power_names[];
183
184 static inline const char *pci_power_name(pci_power_t state)
185 {
186 return pci_power_names[1 + (__force int) state];
187 }
188
189 /**
190 * typedef pci_channel_state_t
191 *
192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
195 */
196 typedef unsigned int __bitwise pci_channel_state_t;
197
198 enum {
199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
201
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
207 };
208
209 typedef unsigned int __bitwise pcie_reset_state_t;
210
211 enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214
215 /* Use #PERST to reset PCIe device */
216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
217
218 /* Use PCIe Hot Reset to reset device */
219 pcie_hot_reset = (__force pcie_reset_state_t) 3
220 };
221
222 typedef unsigned short __bitwise pci_dev_flags_t;
223 enum pci_dev_flags {
224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
226 /* Device configuration is irrevocably lost if disabled into D3 */
227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
228 /* Provide indication device is assigned by a Virtual Machine Manager */
229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
240 /* A non-root bridge where translation occurs, stop alias search here */
241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
244 /* Don't use Relaxed Ordering for TLPs directed at this device */
245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
248 };
249
250 enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
253 };
254
255 typedef unsigned short __bitwise pci_bus_flags_t;
256 enum pci_bus_flags {
257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
261 };
262
263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
264 enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
266 PCIE_LNK_X1 = 0x01,
267 PCIE_LNK_X2 = 0x02,
268 PCIE_LNK_X4 = 0x04,
269 PCIE_LNK_X8 = 0x08,
270 PCIE_LNK_X12 = 0x0c,
271 PCIE_LNK_X16 = 0x10,
272 PCIE_LNK_X32 = 0x20,
273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
274 };
275
276 /* See matching string table in pci_speed_string() */
277 enum pci_bus_speed {
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
289 AGP_UNKNOWN = 0x0c,
290 AGP_1X = 0x0d,
291 AGP_2X = 0x0e,
292 AGP_4X = 0x0f,
293 AGP_8X = 0x10,
294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
299 PCIE_SPEED_8_0GT = 0x16,
300 PCIE_SPEED_16_0GT = 0x17,
301 PCIE_SPEED_32_0GT = 0x18,
302 PCIE_SPEED_64_0GT = 0x19,
303 PCI_SPEED_UNKNOWN = 0xff,
304 };
305
306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
308
309 struct pci_vpd {
310 struct mutex lock;
311 unsigned int len;
312 u8 cap;
313 };
314
315 struct irq_affinity;
316 struct pcie_link_state;
317 struct pci_sriov;
318 struct pci_p2pdma;
319 struct rcec_ea;
320
321 /* The pci_dev structure describes PCI devices */
322 struct pci_dev {
323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
326
327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
329 struct pci_slot *slot; /* Physical slot this device is in */
330
331 unsigned int devfn; /* Encoded device & function index */
332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
337 u8 revision; /* PCI revision, low byte of class word */
338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
339 #ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
341 struct aer_stats *aer_stats; /* AER stats for this device */
342 #endif
343 #ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
345 struct pci_dev *rcec; /* Associated RCEC device */
346 #endif
347 u32 devcap; /* PCIe Device Capabilities */
348 u8 pcie_cap; /* PCIe capability offset */
349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
356
357 struct pci_driver *driver; /* Driver bound to this device */
358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
363
364 struct device_dma_parameters dma_parms;
365
366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
369 u8 pm_cap; /* PM capability offset */
370 unsigned int pme_support:5; /* Bitmask of states from which PME#
371 can be generated */
372 unsigned int pme_poll:1; /* Poll device's PME status bit */
373 unsigned int pinned:1; /* Whether this dev is pinned */
374 unsigned int imm_ready:1; /* Supports Immediate Readiness */
375 unsigned int d1_support:1; /* Low power state D1 is supported */
376 unsigned int d2_support:1; /* Low power state D2 is supported */
377 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
378 unsigned int no_d3cold:1; /* D3cold is forbidden */
379 unsigned int bridge_d3:1; /* Allow D3 for bridge */
380 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
381 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
382 decoding during BAR sizing */
383 unsigned int wakeup_prepared:1;
384 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
385 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
386 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
387 controlled exclusively by
388 user sysfs */
389 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
390 bit manually */
391 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
392 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
393
394 u16 l1ss; /* L1SS Capability pointer */
395 #ifdef CONFIG_PCIEASPM
396 struct pcie_link_state *link_state; /* ASPM link state */
397 unsigned int ltr_path:1; /* Latency Tolerance Reporting
398 supported from root to here */
399 #endif
400 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
401 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
402
403 pci_channel_state_t error_state; /* Current connectivity state */
404 struct device dev; /* Generic device interface */
405
406 int cfg_size; /* Size of config space */
407
408 /*
409 * Instead of touching interrupt line and base address registers
410 * directly, use the values stored here. They might be different!
411 */
412 unsigned int irq;
413 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
414 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
415
416 bool match_driver; /* Skip attaching driver */
417
418 unsigned int transparent:1; /* Subtractive decode bridge */
419 unsigned int io_window:1; /* Bridge has I/O window */
420 unsigned int pref_window:1; /* Bridge has pref mem window */
421 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
422 unsigned int multifunction:1; /* Multi-function device */
423
424 unsigned int is_busmaster:1; /* Is busmaster */
425 unsigned int no_msi:1; /* May not use MSI */
426 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
427 unsigned int block_cfg_access:1; /* Config space access blocked */
428 unsigned int broken_parity_status:1; /* Generates false positive parity */
429 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
430 unsigned int msi_enabled:1;
431 unsigned int msix_enabled:1;
432 unsigned int ari_enabled:1; /* ARI forwarding */
433 unsigned int ats_enabled:1; /* Address Translation Svc */
434 unsigned int pasid_enabled:1; /* Process Address Space ID */
435 unsigned int pri_enabled:1; /* Page Request Interface */
436 unsigned int is_managed:1; /* Managed via devres */
437 unsigned int is_msi_managed:1; /* MSI release via devres installed */
438 unsigned int needs_freset:1; /* Requires fundamental reset */
439 unsigned int state_saved:1;
440 unsigned int is_physfn:1;
441 unsigned int is_virtfn:1;
442 unsigned int is_hotplug_bridge:1;
443 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
444 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
445 /*
446 * Devices marked being untrusted are the ones that can potentially
447 * execute DMA attacks and similar. They are typically connected
448 * through external ports such as Thunderbolt but not limited to
449 * that. When an IOMMU is enabled they should be getting full
450 * mappings to make sure they cannot access arbitrary memory.
451 */
452 unsigned int untrusted:1;
453 /*
454 * Info from the platform, e.g., ACPI or device tree, may mark a
455 * device as "external-facing". An external-facing device is
456 * itself internal but devices downstream from it are external.
457 */
458 unsigned int external_facing:1;
459 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
460 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
461 unsigned int irq_managed:1;
462 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
463 unsigned int is_probed:1; /* Device probing in progress */
464 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
465 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
466 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
467 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
468 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */
469 pci_dev_flags_t dev_flags;
470 atomic_t enable_cnt; /* pci_enable_device has been called */
471
472 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
473 u32 saved_config_space[16]; /* Config space saved at suspend time */
474 struct hlist_head saved_cap_space;
475 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
476 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
477
478 #ifdef CONFIG_HOTPLUG_PCI_PCIE
479 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
480 #endif
481 #ifdef CONFIG_PCIE_PTM
482 u16 ptm_cap; /* PTM Capability */
483 unsigned int ptm_root:1;
484 unsigned int ptm_enabled:1;
485 u8 ptm_granularity;
486 #endif
487 #ifdef CONFIG_PCI_MSI
488 void __iomem *msix_base;
489 raw_spinlock_t msi_lock;
490 #endif
491 struct pci_vpd vpd;
492 #ifdef CONFIG_PCIE_DPC
493 u16 dpc_cap;
494 unsigned int dpc_rp_extensions:1;
495 u8 dpc_rp_log_size;
496 #endif
497 #ifdef CONFIG_PCI_ATS
498 union {
499 struct pci_sriov *sriov; /* PF: SR-IOV info */
500 struct pci_dev *physfn; /* VF: related PF */
501 };
502 u16 ats_cap; /* ATS Capability offset */
503 u8 ats_stu; /* ATS Smallest Translation Unit */
504 #endif
505 #ifdef CONFIG_PCI_PRI
506 u16 pri_cap; /* PRI Capability offset */
507 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
508 unsigned int pasid_required:1; /* PRG Response PASID Required */
509 #endif
510 #ifdef CONFIG_PCI_PASID
511 u16 pasid_cap; /* PASID Capability offset */
512 u16 pasid_features;
513 #endif
514 #ifdef CONFIG_PCI_P2PDMA
515 struct pci_p2pdma __rcu *p2pdma;
516 #endif
517 #ifdef CONFIG_PCI_DOE
518 struct xarray doe_mbs; /* Data Object Exchange mailboxes */
519 #endif
520 u16 acs_cap; /* ACS Capability offset */
521 phys_addr_t rom; /* Physical address if not from BAR */
522 size_t romlen; /* Length if not from BAR */
523 /*
524 * Driver name to force a match. Do not set directly, because core
525 * frees it. Use driver_set_override() to set or clear it.
526 */
527 const char *driver_override;
528
529 unsigned long priv_flags; /* Private flags for the PCI driver */
530
531 /* These methods index pci_reset_fn_methods[] */
532 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
533 };
534
535 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
536 {
537 #ifdef CONFIG_PCI_IOV
538 if (dev->is_virtfn)
539 dev = dev->physfn;
540 #endif
541 return dev;
542 }
543
544 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
545
546 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
547 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
548
549 static inline int pci_channel_offline(struct pci_dev *pdev)
550 {
551 return (pdev->error_state != pci_channel_io_normal);
552 }
553
554 /*
555 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
556 * Group number is limited to a 16-bit value, therefore (int)-1 is
557 * not a valid PCI domain number, and can be used as a sentinel
558 * value indicating ->domain_nr is not set by the driver (and
559 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
560 * pci_bus_find_domain_nr()).
561 */
562 #define PCI_DOMAIN_NR_NOT_SET (-1)
563
564 struct pci_host_bridge {
565 struct device dev;
566 struct pci_bus *bus; /* Root bus */
567 struct pci_ops *ops;
568 struct pci_ops *child_ops;
569 void *sysdata;
570 int busnr;
571 int domain_nr;
572 struct list_head windows; /* resource_entry */
573 struct list_head dma_ranges; /* dma ranges resource list */
574 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
575 int (*map_irq)(const struct pci_dev *, u8, u8);
576 void (*release_fn)(struct pci_host_bridge *);
577 void *release_data;
578 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
579 unsigned int no_ext_tags:1; /* No Extended Tags */
580 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
581 unsigned int native_aer:1; /* OS may use PCIe AER */
582 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
583 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
584 unsigned int native_pme:1; /* OS may use PCIe PME */
585 unsigned int native_ltr:1; /* OS may use PCIe LTR */
586 unsigned int native_dpc:1; /* OS may use PCIe DPC */
587 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
588 unsigned int preserve_config:1; /* Preserve FW resource setup */
589 unsigned int size_windows:1; /* Enable root bus sizing */
590 unsigned int msi_domain:1; /* Bridge wants MSI domain */
591
592 /* Resource alignment requirements */
593 resource_size_t (*align_resource)(struct pci_dev *dev,
594 const struct resource *res,
595 resource_size_t start,
596 resource_size_t size,
597 resource_size_t align);
598 unsigned long private[] ____cacheline_aligned;
599 };
600
601 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
602
603 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
604 {
605 return (void *)bridge->private;
606 }
607
608 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
609 {
610 return container_of(priv, struct pci_host_bridge, private);
611 }
612
613 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
614 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
615 size_t priv);
616 void pci_free_host_bridge(struct pci_host_bridge *bridge);
617 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
618
619 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
620 void (*release_fn)(struct pci_host_bridge *),
621 void *release_data);
622
623 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
624
625 /*
626 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
627 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
628 * buses below host bridges or subtractive decode bridges) go in the list.
629 * Use pci_bus_for_each_resource() to iterate through all the resources.
630 */
631
632 /*
633 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
634 * and there's no way to program the bridge with the details of the window.
635 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
636 * decode bit set, because they are explicit and can be programmed with _SRS.
637 */
638 #define PCI_SUBTRACTIVE_DECODE 0x1
639
640 struct pci_bus_resource {
641 struct list_head list;
642 struct resource *res;
643 unsigned int flags;
644 };
645
646 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
647
648 struct pci_bus {
649 struct list_head node; /* Node in list of buses */
650 struct pci_bus *parent; /* Parent bus this bridge is on */
651 struct list_head children; /* List of child buses */
652 struct list_head devices; /* List of devices on this bus */
653 struct pci_dev *self; /* Bridge device as seen by parent */
654 struct list_head slots; /* List of slots on this bus;
655 protected by pci_slot_mutex */
656 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
657 struct list_head resources; /* Address space routed to this bus */
658 struct resource busn_res; /* Bus numbers routed to this bus */
659
660 struct pci_ops *ops; /* Configuration access functions */
661 void *sysdata; /* Hook for sys-specific extension */
662 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
663
664 unsigned char number; /* Bus number */
665 unsigned char primary; /* Number of primary bridge */
666 unsigned char max_bus_speed; /* enum pci_bus_speed */
667 unsigned char cur_bus_speed; /* enum pci_bus_speed */
668 #ifdef CONFIG_PCI_DOMAINS_GENERIC
669 int domain_nr;
670 #endif
671
672 char name[48];
673
674 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
675 pci_bus_flags_t bus_flags; /* Inherited by child buses */
676 struct device *bridge;
677 struct device dev;
678 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
679 struct bin_attribute *legacy_mem; /* Legacy mem */
680 unsigned int is_added:1;
681 unsigned int unsafe_warn:1; /* warned about RW1C config write */
682 };
683
684 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
685
686 static inline u16 pci_dev_id(struct pci_dev *dev)
687 {
688 return PCI_DEVID(dev->bus->number, dev->devfn);
689 }
690
691 /*
692 * Returns true if the PCI bus is root (behind host-PCI bridge),
693 * false otherwise
694 *
695 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
696 * This is incorrect because "virtual" buses added for SR-IOV (via
697 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
698 */
699 static inline bool pci_is_root_bus(struct pci_bus *pbus)
700 {
701 return !(pbus->parent);
702 }
703
704 /**
705 * pci_is_bridge - check if the PCI device is a bridge
706 * @dev: PCI device
707 *
708 * Return true if the PCI device is bridge whether it has subordinate
709 * or not.
710 */
711 static inline bool pci_is_bridge(struct pci_dev *dev)
712 {
713 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
714 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
715 }
716
717 /**
718 * pci_is_vga - check if the PCI device is a VGA device
719 * @pdev: PCI device
720 *
721 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define
722 * VGA Base Class and Sub-Classes:
723 *
724 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible
725 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code)
726 *
727 * Return true if the PCI device is a VGA device and uses the legacy VGA
728 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and
729 * aliases).
730 */
731 static inline bool pci_is_vga(struct pci_dev *pdev)
732 {
733 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
734 return true;
735
736 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA)
737 return true;
738
739 return false;
740 }
741
742 #define for_each_pci_bridge(dev, bus) \
743 list_for_each_entry(dev, &bus->devices, bus_list) \
744 if (!pci_is_bridge(dev)) {} else
745
746 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
747 {
748 dev = pci_physfn(dev);
749 if (pci_is_root_bus(dev->bus))
750 return NULL;
751
752 return dev->bus->self;
753 }
754
755 #ifdef CONFIG_PCI_MSI
756 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
757 {
758 return pci_dev->msi_enabled || pci_dev->msix_enabled;
759 }
760 #else
761 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
762 #endif
763
764 /* Error values that may be returned by PCI functions */
765 #define PCIBIOS_SUCCESSFUL 0x00
766 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
767 #define PCIBIOS_BAD_VENDOR_ID 0x83
768 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
769 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
770 #define PCIBIOS_SET_FAILED 0x88
771 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
772
773 /* Translate above to generic errno for passing back through non-PCI code */
774 static inline int pcibios_err_to_errno(int err)
775 {
776 if (err <= PCIBIOS_SUCCESSFUL)
777 return err; /* Assume already errno */
778
779 switch (err) {
780 case PCIBIOS_FUNC_NOT_SUPPORTED:
781 return -ENOENT;
782 case PCIBIOS_BAD_VENDOR_ID:
783 return -ENOTTY;
784 case PCIBIOS_DEVICE_NOT_FOUND:
785 return -ENODEV;
786 case PCIBIOS_BAD_REGISTER_NUMBER:
787 return -EFAULT;
788 case PCIBIOS_SET_FAILED:
789 return -EIO;
790 case PCIBIOS_BUFFER_TOO_SMALL:
791 return -ENOSPC;
792 }
793
794 return -ERANGE;
795 }
796
797 /* Low-level architecture-dependent routines */
798
799 struct pci_ops {
800 int (*add_bus)(struct pci_bus *bus);
801 void (*remove_bus)(struct pci_bus *bus);
802 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
803 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
804 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
805 };
806
807 /*
808 * ACPI needs to be able to access PCI config space before we've done a
809 * PCI bus scan and created pci_bus structures.
810 */
811 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
812 int reg, int len, u32 *val);
813 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
814 int reg, int len, u32 val);
815
816 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
817 typedef u64 pci_bus_addr_t;
818 #else
819 typedef u32 pci_bus_addr_t;
820 #endif
821
822 struct pci_bus_region {
823 pci_bus_addr_t start;
824 pci_bus_addr_t end;
825 };
826
827 struct pci_dynids {
828 spinlock_t lock; /* Protects list, index */
829 struct list_head list; /* For IDs added at runtime */
830 };
831
832
833 /*
834 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
835 * a set of callbacks in struct pci_error_handlers, that device driver
836 * will be notified of PCI bus errors, and will be driven to recovery
837 * when an error occurs.
838 */
839
840 typedef unsigned int __bitwise pci_ers_result_t;
841
842 enum pci_ers_result {
843 /* No result/none/not supported in device driver */
844 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
845
846 /* Device driver can recover without slot reset */
847 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
848
849 /* Device driver wants slot to be reset */
850 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
851
852 /* Device has completely failed, is unrecoverable */
853 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
854
855 /* Device driver is fully recovered and operational */
856 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
857
858 /* No AER capabilities registered for the driver */
859 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
860 };
861
862 /* PCI bus error event callbacks */
863 struct pci_error_handlers {
864 /* PCI bus error detected on this device */
865 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
866 pci_channel_state_t error);
867
868 /* MMIO has been re-enabled, but not DMA */
869 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
870
871 /* PCI slot has been reset */
872 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
873
874 /* PCI function reset prepare or completed */
875 void (*reset_prepare)(struct pci_dev *dev);
876 void (*reset_done)(struct pci_dev *dev);
877
878 /* Device driver may resume normal operations */
879 void (*resume)(struct pci_dev *dev);
880
881 /* Allow device driver to record more details of a correctable error */
882 void (*cor_error_detected)(struct pci_dev *dev);
883 };
884
885
886 struct module;
887
888 /**
889 * struct pci_driver - PCI driver structure
890 * @name: Driver name.
891 * @id_table: Pointer to table of device IDs the driver is
892 * interested in. Most drivers should export this
893 * table using MODULE_DEVICE_TABLE(pci,...).
894 * @probe: This probing function gets called (during execution
895 * of pci_register_driver() for already existing
896 * devices or later if a new device gets inserted) for
897 * all PCI devices which match the ID table and are not
898 * "owned" by the other drivers yet. This function gets
899 * passed a "struct pci_dev \*" for each device whose
900 * entry in the ID table matches the device. The probe
901 * function returns zero when the driver chooses to
902 * take "ownership" of the device or an error code
903 * (negative number) otherwise.
904 * The probe function always gets called from process
905 * context, so it can sleep.
906 * @remove: The remove() function gets called whenever a device
907 * being handled by this driver is removed (either during
908 * deregistration of the driver or when it's manually
909 * pulled out of a hot-pluggable slot).
910 * The remove function always gets called from process
911 * context, so it can sleep.
912 * @suspend: Put device into low power state.
913 * @resume: Wake device from low power state.
914 * (Please see Documentation/power/pci.rst for descriptions
915 * of PCI Power Management and the related functions.)
916 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
917 * Intended to stop any idling DMA operations.
918 * Useful for enabling wake-on-lan (NIC) or changing
919 * the power state of a device before reboot.
920 * e.g. drivers/net/e100.c.
921 * @sriov_configure: Optional driver callback to allow configuration of
922 * number of VFs to enable via sysfs "sriov_numvfs" file.
923 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
924 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
925 * This will change MSI-X Table Size in the VF Message Control
926 * registers.
927 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
928 * MSI-X vectors available for distribution to the VFs.
929 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
930 * @groups: Sysfs attribute groups.
931 * @dev_groups: Attributes attached to the device that will be
932 * created once it is bound to the driver.
933 * @driver: Driver model structure.
934 * @dynids: List of dynamically added device IDs.
935 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
936 * For most device drivers, no need to care about this flag
937 * as long as all DMAs are handled through the kernel DMA API.
938 * For some special ones, for example VFIO drivers, they know
939 * how to manage the DMA themselves and set this flag so that
940 * the IOMMU layer will allow them to setup and manage their
941 * own I/O address space.
942 */
943 struct pci_driver {
944 const char *name;
945 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
946 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
947 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
948 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
949 int (*resume)(struct pci_dev *dev); /* Device woken up */
950 void (*shutdown)(struct pci_dev *dev);
951 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
952 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
953 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
954 const struct pci_error_handlers *err_handler;
955 const struct attribute_group **groups;
956 const struct attribute_group **dev_groups;
957 struct device_driver driver;
958 struct pci_dynids dynids;
959 bool driver_managed_dma;
960 };
961
962 #define to_pci_driver(__drv) \
963 ( __drv ? container_of_const(__drv, struct pci_driver, driver) : NULL )
964
965 /**
966 * PCI_DEVICE - macro used to describe a specific PCI device
967 * @vend: the 16 bit PCI Vendor ID
968 * @dev: the 16 bit PCI Device ID
969 *
970 * This macro is used to create a struct pci_device_id that matches a
971 * specific device. The subvendor and subdevice fields will be set to
972 * PCI_ANY_ID.
973 */
974 #define PCI_DEVICE(vend,dev) \
975 .vendor = (vend), .device = (dev), \
976 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
977
978 /**
979 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
980 * override_only flags.
981 * @vend: the 16 bit PCI Vendor ID
982 * @dev: the 16 bit PCI Device ID
983 * @driver_override: the 32 bit PCI Device override_only
984 *
985 * This macro is used to create a struct pci_device_id that matches only a
986 * driver_override device. The subvendor and subdevice fields will be set to
987 * PCI_ANY_ID.
988 */
989 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
990 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
991 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
992
993 /**
994 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
995 * "driver_override" PCI device.
996 * @vend: the 16 bit PCI Vendor ID
997 * @dev: the 16 bit PCI Device ID
998 *
999 * This macro is used to create a struct pci_device_id that matches a
1000 * specific device. The subvendor and subdevice fields will be set to
1001 * PCI_ANY_ID and the driver_override will be set to
1002 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
1003 */
1004 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
1005 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
1006
1007 /**
1008 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
1009 * @vend: the 16 bit PCI Vendor ID
1010 * @dev: the 16 bit PCI Device ID
1011 * @subvend: the 16 bit PCI Subvendor ID
1012 * @subdev: the 16 bit PCI Subdevice ID
1013 *
1014 * This macro is used to create a struct pci_device_id that matches a
1015 * specific device with subsystem information.
1016 */
1017 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1018 .vendor = (vend), .device = (dev), \
1019 .subvendor = (subvend), .subdevice = (subdev)
1020
1021 /**
1022 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1023 * @dev_class: the class, subclass, prog-if triple for this device
1024 * @dev_class_mask: the class mask for this device
1025 *
1026 * This macro is used to create a struct pci_device_id that matches a
1027 * specific PCI class. The vendor, device, subvendor, and subdevice
1028 * fields will be set to PCI_ANY_ID.
1029 */
1030 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1031 .class = (dev_class), .class_mask = (dev_class_mask), \
1032 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1033 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1034
1035 /**
1036 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1037 * @vend: the vendor name
1038 * @dev: the 16 bit PCI Device ID
1039 *
1040 * This macro is used to create a struct pci_device_id that matches a
1041 * specific PCI device. The subvendor, and subdevice fields will be set
1042 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1043 * private data.
1044 */
1045 #define PCI_VDEVICE(vend, dev) \
1046 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1047 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1048
1049 /**
1050 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1051 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1052 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1053 * @data: the driver data to be filled
1054 *
1055 * This macro is used to create a struct pci_device_id that matches a
1056 * specific PCI device. The subvendor, and subdevice fields will be set
1057 * to PCI_ANY_ID.
1058 */
1059 #define PCI_DEVICE_DATA(vend, dev, data) \
1060 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1061 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1062 .driver_data = (kernel_ulong_t)(data)
1063
1064 enum {
1065 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1066 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1067 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1068 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1069 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1070 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1071 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1072 };
1073
1074 #define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
1075 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1076 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1077 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1078
1079 /* These external functions are only available when PCI support is enabled */
1080 #ifdef CONFIG_PCI
1081
1082 extern unsigned int pci_flags;
1083
1084 static inline void pci_set_flags(int flags) { pci_flags = flags; }
1085 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1086 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1087 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1088
1089 void pcie_bus_configure_settings(struct pci_bus *bus);
1090
1091 enum pcie_bus_config_types {
1092 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1093 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1094 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1095 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1096 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1097 };
1098
1099 extern enum pcie_bus_config_types pcie_bus_config;
1100
1101 extern struct bus_type pci_bus_type;
1102
1103 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1104 * code, or PCI core code. */
1105 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1106 /* Some device drivers need know if PCI is initiated */
1107 int no_pci_devices(void);
1108
1109 void pcibios_resource_survey_bus(struct pci_bus *bus);
1110 void pcibios_bus_add_device(struct pci_dev *pdev);
1111 void pcibios_add_bus(struct pci_bus *bus);
1112 void pcibios_remove_bus(struct pci_bus *bus);
1113 void pcibios_fixup_bus(struct pci_bus *);
1114 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1115 /* Architecture-specific versions may override this (weak) */
1116 char *pcibios_setup(char *str);
1117
1118 /* Used only when drivers/pci/setup.c is used */
1119 resource_size_t pcibios_align_resource(void *, const struct resource *,
1120 resource_size_t,
1121 resource_size_t);
1122
1123 /* Weak but can be overridden by arch */
1124 void pci_fixup_cardbus(struct pci_bus *);
1125
1126 /* Generic PCI functions used internally */
1127
1128 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1129 struct resource *res);
1130 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1131 struct pci_bus_region *region);
1132 void pcibios_scan_specific_bus(int busn);
1133 struct pci_bus *pci_find_bus(int domain, int busnr);
1134 void pci_bus_add_devices(const struct pci_bus *bus);
1135 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1136 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1137 struct pci_ops *ops, void *sysdata,
1138 struct list_head *resources);
1139 int pci_host_probe(struct pci_host_bridge *bridge);
1140 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1141 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1142 void pci_bus_release_busn_res(struct pci_bus *b);
1143 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1144 struct pci_ops *ops, void *sysdata,
1145 struct list_head *resources);
1146 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1147 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1148 int busnr);
1149 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1150 const char *name,
1151 struct hotplug_slot *hotplug);
1152 void pci_destroy_slot(struct pci_slot *slot);
1153 #ifdef CONFIG_SYSFS
1154 void pci_dev_assign_slot(struct pci_dev *dev);
1155 #else
1156 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1157 #endif
1158 int pci_scan_slot(struct pci_bus *bus, int devfn);
1159 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1160 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1161 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1162 void pci_bus_add_device(struct pci_dev *dev);
1163 void pci_read_bridge_bases(struct pci_bus *child);
1164 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1165 struct resource *res);
1166 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1167 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1168 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1169 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1170 void pci_dev_put(struct pci_dev *dev);
1171 DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T))
1172 void pci_remove_bus(struct pci_bus *b);
1173 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1174 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1175 void pci_stop_root_bus(struct pci_bus *bus);
1176 void pci_remove_root_bus(struct pci_bus *bus);
1177 void pci_setup_cardbus(struct pci_bus *bus);
1178 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1179 void pci_sort_breadthfirst(void);
1180 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1181 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1182
1183 /* Generic PCI functions exported to card drivers */
1184
1185 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1186 u8 pci_find_capability(struct pci_dev *dev, int cap);
1187 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1188 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1189 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1190 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1191 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1192 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1193 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1194 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1195
1196 u64 pci_get_dsn(struct pci_dev *dev);
1197
1198 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1199 struct pci_dev *from);
1200 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1201 unsigned int ss_vendor, unsigned int ss_device,
1202 struct pci_dev *from);
1203 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1204 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1205 unsigned int devfn);
1206 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1207 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from);
1208
1209 int pci_dev_present(const struct pci_device_id *ids);
1210
1211 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1212 int where, u8 *val);
1213 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1214 int where, u16 *val);
1215 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1216 int where, u32 *val);
1217 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1218 int where, u8 val);
1219 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1220 int where, u16 val);
1221 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1222 int where, u32 val);
1223
1224 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1225 int where, int size, u32 *val);
1226 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1227 int where, int size, u32 val);
1228 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1229 int where, int size, u32 *val);
1230 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1231 int where, int size, u32 val);
1232
1233 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1234
1235 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1236 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1237 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1238 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1239 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1240 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1241 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
1242 u32 clear, u32 set);
1243
1244 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1245 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1246 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1247 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1248 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
1249 u16 clear, u16 set);
1250 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
1251 u16 clear, u16 set);
1252 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1253 u32 clear, u32 set);
1254
1255 /**
1256 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers
1257 * @dev: PCI device structure of the PCI Express device
1258 * @pos: PCI Express Capability Register
1259 * @clear: Clear bitmask
1260 * @set: Set bitmask
1261 *
1262 * Perform a Read-Modify-Write (RMW) operation using @clear and @set
1263 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express
1264 * Capability Registers are accessed concurrently in RMW fashion, hence
1265 * require locking which is handled transparently to the caller.
1266 */
1267 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
1268 int pos,
1269 u16 clear, u16 set)
1270 {
1271 switch (pos) {
1272 case PCI_EXP_LNKCTL:
1273 case PCI_EXP_RTCTL:
1274 return pcie_capability_clear_and_set_word_locked(dev, pos,
1275 clear, set);
1276 default:
1277 return pcie_capability_clear_and_set_word_unlocked(dev, pos,
1278 clear, set);
1279 }
1280 }
1281
1282 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1283 u16 set)
1284 {
1285 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1286 }
1287
1288 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1289 u32 set)
1290 {
1291 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1292 }
1293
1294 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1295 u16 clear)
1296 {
1297 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1298 }
1299
1300 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1301 u32 clear)
1302 {
1303 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1304 }
1305
1306 /* User-space driven config access */
1307 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1308 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1309 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1310 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1311 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1312 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1313
1314 int __must_check pci_enable_device(struct pci_dev *dev);
1315 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1316 int __must_check pci_reenable_device(struct pci_dev *);
1317 int __must_check pcim_enable_device(struct pci_dev *pdev);
1318 void pcim_pin_device(struct pci_dev *pdev);
1319
1320 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1321 {
1322 /*
1323 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1324 * writable and no quirk has marked the feature broken.
1325 */
1326 return !pdev->broken_intx_masking;
1327 }
1328
1329 static inline int pci_is_enabled(struct pci_dev *pdev)
1330 {
1331 return (atomic_read(&pdev->enable_cnt) > 0);
1332 }
1333
1334 static inline int pci_is_managed(struct pci_dev *pdev)
1335 {
1336 return pdev->is_managed;
1337 }
1338
1339 void pci_disable_device(struct pci_dev *dev);
1340
1341 extern unsigned int pcibios_max_latency;
1342 void pci_set_master(struct pci_dev *dev);
1343 void pci_clear_master(struct pci_dev *dev);
1344
1345 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1346 int pci_set_cacheline_size(struct pci_dev *dev);
1347 int __must_check pci_set_mwi(struct pci_dev *dev);
1348 int __must_check pcim_set_mwi(struct pci_dev *dev);
1349 int pci_try_set_mwi(struct pci_dev *dev);
1350 void pci_clear_mwi(struct pci_dev *dev);
1351 void pci_disable_parity(struct pci_dev *dev);
1352 void pci_intx(struct pci_dev *dev, int enable);
1353 bool pci_check_and_mask_intx(struct pci_dev *dev);
1354 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1355 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1356 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1357 int pcix_get_max_mmrbc(struct pci_dev *dev);
1358 int pcix_get_mmrbc(struct pci_dev *dev);
1359 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1360 int pcie_get_readrq(struct pci_dev *dev);
1361 int pcie_set_readrq(struct pci_dev *dev, int rq);
1362 int pcie_get_mps(struct pci_dev *dev);
1363 int pcie_set_mps(struct pci_dev *dev, int mps);
1364 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1365 enum pci_bus_speed *speed,
1366 enum pcie_link_width *width);
1367 int pcie_link_speed_mbps(struct pci_dev *pdev);
1368 void pcie_print_link_status(struct pci_dev *dev);
1369 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1370 int pcie_flr(struct pci_dev *dev);
1371 int __pci_reset_function_locked(struct pci_dev *dev);
1372 int pci_reset_function(struct pci_dev *dev);
1373 int pci_reset_function_locked(struct pci_dev *dev);
1374 int pci_try_reset_function(struct pci_dev *dev);
1375 int pci_probe_reset_slot(struct pci_slot *slot);
1376 int pci_probe_reset_bus(struct pci_bus *bus);
1377 int pci_reset_bus(struct pci_dev *dev);
1378 void pci_reset_secondary_bus(struct pci_dev *dev);
1379 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1380 void pci_update_resource(struct pci_dev *dev, int resno);
1381 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1382 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1383 void pci_release_resource(struct pci_dev *dev, int resno);
1384 static inline int pci_rebar_bytes_to_size(u64 bytes)
1385 {
1386 bytes = roundup_pow_of_two(bytes);
1387
1388 /* Return BAR size as defined in the resizable BAR specification */
1389 return max(ilog2(bytes), 20) - 20;
1390 }
1391
1392 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1393 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1394 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1395 bool pci_device_is_present(struct pci_dev *pdev);
1396 void pci_ignore_hotplug(struct pci_dev *dev);
1397 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1398 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1399
1400 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1401 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1402 const char *fmt, ...);
1403 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1404
1405 /* ROM control related routines */
1406 int pci_enable_rom(struct pci_dev *pdev);
1407 void pci_disable_rom(struct pci_dev *pdev);
1408 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1409 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1410
1411 /* Power management related routines */
1412 int pci_save_state(struct pci_dev *dev);
1413 void pci_restore_state(struct pci_dev *dev);
1414 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1415 int pci_load_saved_state(struct pci_dev *dev,
1416 struct pci_saved_state *state);
1417 int pci_load_and_free_saved_state(struct pci_dev *dev,
1418 struct pci_saved_state **state);
1419 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1420 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1421 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state);
1422 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1423 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1424 void pci_pme_active(struct pci_dev *dev, bool enable);
1425 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1426 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1427 int pci_prepare_to_sleep(struct pci_dev *dev);
1428 int pci_back_from_sleep(struct pci_dev *dev);
1429 bool pci_dev_run_wake(struct pci_dev *dev);
1430 void pci_d3cold_enable(struct pci_dev *dev);
1431 void pci_d3cold_disable(struct pci_dev *dev);
1432 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1433 void pci_resume_bus(struct pci_bus *bus);
1434 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1435
1436 /* For use by arch with custom probe code */
1437 void set_pcie_port_type(struct pci_dev *pdev);
1438 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1439
1440 /* Functions for PCI Hotplug drivers to use */
1441 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1442 unsigned int pci_rescan_bus(struct pci_bus *bus);
1443 void pci_lock_rescan_remove(void);
1444 void pci_unlock_rescan_remove(void);
1445
1446 /* Vital Product Data routines */
1447 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1448 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1449 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1450 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1451
1452 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1453 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1454 void pci_bus_assign_resources(const struct pci_bus *bus);
1455 void pci_bus_claim_resources(struct pci_bus *bus);
1456 void pci_bus_size_bridges(struct pci_bus *bus);
1457 int pci_claim_resource(struct pci_dev *, int);
1458 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1459 void pci_assign_unassigned_resources(void);
1460 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1461 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1462 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1463 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1464 int pci_enable_resources(struct pci_dev *, int mask);
1465 void pci_assign_irq(struct pci_dev *dev);
1466 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1467 #define HAVE_PCI_REQ_REGIONS 2
1468 int __must_check pci_request_regions(struct pci_dev *, const char *);
1469 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1470 void pci_release_regions(struct pci_dev *);
1471 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1472 void pci_release_region(struct pci_dev *, int);
1473 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1474 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1475 void pci_release_selected_regions(struct pci_dev *, int);
1476
1477 static inline __must_check struct resource *
1478 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1479 unsigned int len, const char *name)
1480 {
1481 return __request_region(&pdev->driver_exclusive_resource, offset, len,
1482 name, IORESOURCE_EXCLUSIVE);
1483 }
1484
1485 static inline void pci_release_config_region(struct pci_dev *pdev,
1486 unsigned int offset,
1487 unsigned int len)
1488 {
1489 __release_region(&pdev->driver_exclusive_resource, offset, len);
1490 }
1491
1492 /* drivers/pci/bus.c */
1493 void pci_add_resource(struct list_head *resources, struct resource *res);
1494 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1495 resource_size_t offset);
1496 void pci_free_resource_list(struct list_head *resources);
1497 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1498 unsigned int flags);
1499 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1500 void pci_bus_remove_resources(struct pci_bus *bus);
1501 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1502 int devm_request_pci_bus_resources(struct device *dev,
1503 struct list_head *resources);
1504
1505 /* Temporary until new and working PCI SBR API in place */
1506 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1507
1508 #define __pci_bus_for_each_res0(bus, res, ...) \
1509 for (unsigned int __b = 0; \
1510 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1511 __b++)
1512
1513 #define __pci_bus_for_each_res1(bus, res, __b) \
1514 for (__b = 0; \
1515 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1516 __b++)
1517
1518 /**
1519 * pci_bus_for_each_resource - iterate over PCI bus resources
1520 * @bus: the PCI bus
1521 * @res: pointer to the current resource
1522 * @...: optional index of the current resource
1523 *
1524 * Iterate over PCI bus resources. The first part is to go over PCI bus
1525 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries.
1526 * After that continue with the separate list of the additional resources,
1527 * if not empty. That's why the Logical OR is being used.
1528 *
1529 * Possible usage:
1530 *
1531 * struct pci_bus *bus = ...;
1532 * struct resource *res;
1533 * unsigned int i;
1534 *
1535 * // With optional index
1536 * pci_bus_for_each_resource(bus, res, i)
1537 * pr_info("PCI bus resource[%u]: %pR\n", i, res);
1538 *
1539 * // Without index
1540 * pci_bus_for_each_resource(bus, res)
1541 * _do_something_(res);
1542 */
1543 #define pci_bus_for_each_resource(bus, res, ...) \
1544 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
1545 (bus, res, __VA_ARGS__)
1546
1547 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1548 struct resource *res, resource_size_t size,
1549 resource_size_t align, resource_size_t min,
1550 unsigned long type_mask,
1551 resource_alignf alignf,
1552 void *alignf_data);
1553
1554
1555 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1556 resource_size_t size);
1557 unsigned long pci_address_to_pio(phys_addr_t addr);
1558 phys_addr_t pci_pio_to_address(unsigned long pio);
1559 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1560 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1561 phys_addr_t phys_addr);
1562 void pci_unmap_iospace(struct resource *res);
1563 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1564 resource_size_t offset,
1565 resource_size_t size);
1566 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1567 struct resource *res);
1568
1569 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1570 {
1571 struct pci_bus_region region;
1572
1573 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1574 return region.start;
1575 }
1576
1577 /* Proper probing supporting hot-pluggable devices */
1578 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1579 const char *mod_name);
1580
1581 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1582 #define pci_register_driver(driver) \
1583 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1584
1585 void pci_unregister_driver(struct pci_driver *dev);
1586
1587 /**
1588 * module_pci_driver() - Helper macro for registering a PCI driver
1589 * @__pci_driver: pci_driver struct
1590 *
1591 * Helper macro for PCI drivers which do not do anything special in module
1592 * init/exit. This eliminates a lot of boilerplate. Each module may only
1593 * use this macro once, and calling it replaces module_init() and module_exit()
1594 */
1595 #define module_pci_driver(__pci_driver) \
1596 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1597
1598 /**
1599 * builtin_pci_driver() - Helper macro for registering a PCI driver
1600 * @__pci_driver: pci_driver struct
1601 *
1602 * Helper macro for PCI drivers which do not do anything special in their
1603 * init code. This eliminates a lot of boilerplate. Each driver may only
1604 * use this macro once, and calling it replaces device_initcall(...)
1605 */
1606 #define builtin_pci_driver(__pci_driver) \
1607 builtin_driver(__pci_driver, pci_register_driver)
1608
1609 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1610 int pci_add_dynid(struct pci_driver *drv,
1611 unsigned int vendor, unsigned int device,
1612 unsigned int subvendor, unsigned int subdevice,
1613 unsigned int class, unsigned int class_mask,
1614 unsigned long driver_data);
1615 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1616 struct pci_dev *dev);
1617 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1618 int pass);
1619
1620 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1621 void *userdata);
1622 void pci_walk_bus_locked(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1623 void *userdata);
1624 int pci_cfg_space_size(struct pci_dev *dev);
1625 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1626 void pci_setup_bridge(struct pci_bus *bus);
1627 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1628 unsigned long type);
1629
1630 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1631 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1632
1633 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1634 unsigned int command_bits, u32 flags);
1635
1636 /*
1637 * Virtual interrupts allow for more interrupts to be allocated
1638 * than the device has interrupts for. These are not programmed
1639 * into the device's MSI-X table and must be handled by some
1640 * other driver means.
1641 */
1642 #define PCI_IRQ_VIRTUAL (1 << 4)
1643
1644 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1645
1646 #include <linux/dmapool.h>
1647
1648 struct msix_entry {
1649 u32 vector; /* Kernel uses to write allocated vector */
1650 u16 entry; /* Driver uses to specify entry, OS writes */
1651 };
1652
1653 #ifdef CONFIG_PCI_MSI
1654 int pci_msi_vec_count(struct pci_dev *dev);
1655 void pci_disable_msi(struct pci_dev *dev);
1656 int pci_msix_vec_count(struct pci_dev *dev);
1657 void pci_disable_msix(struct pci_dev *dev);
1658 void pci_restore_msi_state(struct pci_dev *dev);
1659 int pci_msi_enabled(void);
1660 int pci_enable_msi(struct pci_dev *dev);
1661 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1662 int minvec, int maxvec);
1663 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1664 struct msix_entry *entries, int nvec)
1665 {
1666 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1667 if (rc < 0)
1668 return rc;
1669 return 0;
1670 }
1671 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1672 unsigned int max_vecs, unsigned int flags);
1673 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1674 unsigned int max_vecs, unsigned int flags,
1675 struct irq_affinity *affd);
1676
1677 bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1678 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1679 const struct irq_affinity_desc *affdesc);
1680 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1681
1682 void pci_free_irq_vectors(struct pci_dev *dev);
1683 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1684 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1685
1686 #else
1687 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1688 static inline void pci_disable_msi(struct pci_dev *dev) { }
1689 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1690 static inline void pci_disable_msix(struct pci_dev *dev) { }
1691 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1692 static inline int pci_msi_enabled(void) { return 0; }
1693 static inline int pci_enable_msi(struct pci_dev *dev)
1694 { return -ENOSYS; }
1695 static inline int pci_enable_msix_range(struct pci_dev *dev,
1696 struct msix_entry *entries, int minvec, int maxvec)
1697 { return -ENOSYS; }
1698 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1699 struct msix_entry *entries, int nvec)
1700 { return -ENOSYS; }
1701
1702 static inline int
1703 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1704 unsigned int max_vecs, unsigned int flags,
1705 struct irq_affinity *aff_desc)
1706 {
1707 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq)
1708 return 1;
1709 return -ENOSPC;
1710 }
1711 static inline int
1712 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1713 unsigned int max_vecs, unsigned int flags)
1714 {
1715 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1716 flags, NULL);
1717 }
1718
1719 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev)
1720 { return false; }
1721 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1722 const struct irq_affinity_desc *affdesc)
1723 {
1724 struct msi_map map = { .index = -ENOSYS, };
1725
1726 return map;
1727 }
1728
1729 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1730 {
1731 }
1732
1733 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1734 {
1735 }
1736
1737 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1738 {
1739 if (WARN_ON_ONCE(nr > 0))
1740 return -EINVAL;
1741 return dev->irq;
1742 }
1743 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1744 int vec)
1745 {
1746 return cpu_possible_mask;
1747 }
1748 #endif
1749
1750 /**
1751 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1752 * @d: the INTx IRQ domain
1753 * @node: the DT node for the device whose interrupt we're translating
1754 * @intspec: the interrupt specifier data from the DT
1755 * @intsize: the number of entries in @intspec
1756 * @out_hwirq: pointer at which to write the hwirq number
1757 * @out_type: pointer at which to write the interrupt type
1758 *
1759 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1760 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1761 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1762 * INTx value to obtain the hwirq number.
1763 *
1764 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1765 */
1766 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1767 struct device_node *node,
1768 const u32 *intspec,
1769 unsigned int intsize,
1770 unsigned long *out_hwirq,
1771 unsigned int *out_type)
1772 {
1773 const u32 intx = intspec[0];
1774
1775 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1776 return -EINVAL;
1777
1778 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1779 return 0;
1780 }
1781
1782 #ifdef CONFIG_PCIEPORTBUS
1783 extern bool pcie_ports_disabled;
1784 extern bool pcie_ports_native;
1785 #else
1786 #define pcie_ports_disabled true
1787 #define pcie_ports_native false
1788 #endif
1789
1790 #define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */
1791 #define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */
1792 #define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */
1793 #define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */
1794 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */
1795 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */
1796 #define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\
1797 PCIE_LINK_STATE_L1 |\
1798 PCIE_LINK_STATE_L1_1 |\
1799 PCIE_LINK_STATE_L1_2 |\
1800 PCIE_LINK_STATE_L1_1_PCIPM |\
1801 PCIE_LINK_STATE_L1_2_PCIPM)
1802 #define PCIE_LINK_STATE_CLKPM BIT(7)
1803 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\
1804 PCIE_LINK_STATE_CLKPM)
1805
1806 #ifdef CONFIG_PCIEASPM
1807 int pci_disable_link_state(struct pci_dev *pdev, int state);
1808 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1809 int pci_enable_link_state(struct pci_dev *pdev, int state);
1810 int pci_enable_link_state_locked(struct pci_dev *pdev, int state);
1811 void pcie_no_aspm(void);
1812 bool pcie_aspm_support_enabled(void);
1813 bool pcie_aspm_enabled(struct pci_dev *pdev);
1814 #else
1815 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1816 { return 0; }
1817 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1818 { return 0; }
1819 static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
1820 { return 0; }
1821 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state)
1822 { return 0; }
1823 static inline void pcie_no_aspm(void) { }
1824 static inline bool pcie_aspm_support_enabled(void) { return false; }
1825 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1826 #endif
1827
1828 #ifdef CONFIG_PCIEAER
1829 bool pci_aer_available(void);
1830 #else
1831 static inline bool pci_aer_available(void) { return false; }
1832 #endif
1833
1834 bool pci_ats_disabled(void);
1835
1836 #ifdef CONFIG_PCIE_PTM
1837 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1838 void pci_disable_ptm(struct pci_dev *dev);
1839 bool pcie_ptm_enabled(struct pci_dev *dev);
1840 #else
1841 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1842 { return -EINVAL; }
1843 static inline void pci_disable_ptm(struct pci_dev *dev) { }
1844 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1845 { return false; }
1846 #endif
1847
1848 void pci_cfg_access_lock(struct pci_dev *dev);
1849 bool pci_cfg_access_trylock(struct pci_dev *dev);
1850 void pci_cfg_access_unlock(struct pci_dev *dev);
1851
1852 void pci_dev_lock(struct pci_dev *dev);
1853 int pci_dev_trylock(struct pci_dev *dev);
1854 void pci_dev_unlock(struct pci_dev *dev);
1855 DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T))
1856
1857 /*
1858 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1859 * a PCI domain is defined to be a set of PCI buses which share
1860 * configuration space.
1861 */
1862 #ifdef CONFIG_PCI_DOMAINS
1863 extern int pci_domains_supported;
1864 #else
1865 enum { pci_domains_supported = 0 };
1866 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1867 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1868 #endif /* CONFIG_PCI_DOMAINS */
1869
1870 /*
1871 * Generic implementation for PCI domain support. If your
1872 * architecture does not need custom management of PCI
1873 * domains then this implementation will be used
1874 */
1875 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1876 static inline int pci_domain_nr(struct pci_bus *bus)
1877 {
1878 return bus->domain_nr;
1879 }
1880 #ifdef CONFIG_ACPI
1881 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1882 #else
1883 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1884 { return 0; }
1885 #endif
1886 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1887 void pci_bus_release_domain_nr(struct device *parent, int domain_nr);
1888 #endif
1889
1890 /* Some architectures require additional setup to direct VGA traffic */
1891 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1892 unsigned int command_bits, u32 flags);
1893 void pci_register_set_vga_state(arch_set_vga_state_t func);
1894
1895 static inline int
1896 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1897 {
1898 return pci_request_selected_regions(pdev,
1899 pci_select_bars(pdev, IORESOURCE_IO), name);
1900 }
1901
1902 static inline void
1903 pci_release_io_regions(struct pci_dev *pdev)
1904 {
1905 return pci_release_selected_regions(pdev,
1906 pci_select_bars(pdev, IORESOURCE_IO));
1907 }
1908
1909 static inline int
1910 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1911 {
1912 return pci_request_selected_regions(pdev,
1913 pci_select_bars(pdev, IORESOURCE_MEM), name);
1914 }
1915
1916 static inline void
1917 pci_release_mem_regions(struct pci_dev *pdev)
1918 {
1919 return pci_release_selected_regions(pdev,
1920 pci_select_bars(pdev, IORESOURCE_MEM));
1921 }
1922
1923 #else /* CONFIG_PCI is not enabled */
1924
1925 static inline void pci_set_flags(int flags) { }
1926 static inline void pci_add_flags(int flags) { }
1927 static inline void pci_clear_flags(int flags) { }
1928 static inline int pci_has_flag(int flag) { return 0; }
1929
1930 /*
1931 * If the system does not have PCI, clearly these return errors. Define
1932 * these as simple inline functions to avoid hair in drivers.
1933 */
1934 #define _PCI_NOP(o, s, t) \
1935 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1936 int where, t val) \
1937 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1938
1939 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1940 _PCI_NOP(o, word, u16 x) \
1941 _PCI_NOP(o, dword, u32 x)
1942 _PCI_NOP_ALL(read, *)
1943 _PCI_NOP_ALL(write,)
1944
1945 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1946 unsigned int device,
1947 struct pci_dev *from)
1948 { return NULL; }
1949
1950 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1951 unsigned int device,
1952 unsigned int ss_vendor,
1953 unsigned int ss_device,
1954 struct pci_dev *from)
1955 { return NULL; }
1956
1957 static inline struct pci_dev *pci_get_class(unsigned int class,
1958 struct pci_dev *from)
1959 { return NULL; }
1960
1961 static inline struct pci_dev *pci_get_base_class(unsigned int class,
1962 struct pci_dev *from)
1963 { return NULL; }
1964
1965 static inline int pci_dev_present(const struct pci_device_id *ids)
1966 { return 0; }
1967
1968 #define no_pci_devices() (1)
1969 #define pci_dev_put(dev) do { } while (0)
1970
1971 static inline void pci_set_master(struct pci_dev *dev) { }
1972 static inline void pci_clear_master(struct pci_dev *dev) { }
1973 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1974 static inline void pci_disable_device(struct pci_dev *dev) { }
1975 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1976 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1977 { return -EBUSY; }
1978 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1979 struct module *owner,
1980 const char *mod_name)
1981 { return 0; }
1982 static inline int pci_register_driver(struct pci_driver *drv)
1983 { return 0; }
1984 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1985 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1986 { return 0; }
1987 static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap)
1988 { return 0; }
1989 static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
1990 { return 0; }
1991
1992 static inline u64 pci_get_dsn(struct pci_dev *dev)
1993 { return 0; }
1994
1995 /* Power management related routines */
1996 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1997 static inline void pci_restore_state(struct pci_dev *dev) { }
1998 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1999 { return 0; }
2000 static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state)
2001 { return 0; }
2002 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2003 { return 0; }
2004 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
2005 pm_message_t state)
2006 { return PCI_D0; }
2007 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
2008 int enable)
2009 { return 0; }
2010
2011 static inline struct resource *pci_find_resource(struct pci_dev *dev,
2012 struct resource *res)
2013 { return NULL; }
2014 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2015 { return -EIO; }
2016 static inline void pci_release_regions(struct pci_dev *dev) { }
2017
2018 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
2019 phys_addr_t addr, resource_size_t size)
2020 { return -EINVAL; }
2021
2022 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
2023
2024 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
2025 { return NULL; }
2026 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
2027 unsigned int devfn)
2028 { return NULL; }
2029 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
2030 unsigned int bus, unsigned int devfn)
2031 { return NULL; }
2032
2033 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
2034 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
2035
2036 #define dev_is_pci(d) (false)
2037 #define dev_is_pf(d) (false)
2038 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2039 { return false; }
2040 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
2041 struct device_node *node,
2042 const u32 *intspec,
2043 unsigned int intsize,
2044 unsigned long *out_hwirq,
2045 unsigned int *out_type)
2046 { return -EINVAL; }
2047
2048 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
2049 struct pci_dev *dev)
2050 { return NULL; }
2051 static inline bool pci_ats_disabled(void) { return true; }
2052
2053 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
2054 {
2055 return -EINVAL;
2056 }
2057
2058 static inline int
2059 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
2060 unsigned int max_vecs, unsigned int flags,
2061 struct irq_affinity *aff_desc)
2062 {
2063 return -ENOSPC;
2064 }
2065 static inline int
2066 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
2067 unsigned int max_vecs, unsigned int flags)
2068 {
2069 return -ENOSPC;
2070 }
2071 #endif /* CONFIG_PCI */
2072
2073 /* Include architecture-dependent settings and functions */
2074
2075 #include <asm/pci.h>
2076
2077 /*
2078 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
2079 * is expected to be an offset within that region.
2080 *
2081 */
2082 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
2083 struct vm_area_struct *vma,
2084 enum pci_mmap_state mmap_state, int write_combine);
2085
2086 #ifndef arch_can_pci_mmap_wc
2087 #define arch_can_pci_mmap_wc() 0
2088 #endif
2089
2090 #ifndef arch_can_pci_mmap_io
2091 #define arch_can_pci_mmap_io() 0
2092 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
2093 #else
2094 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
2095 #endif
2096
2097 #ifndef pci_root_bus_fwnode
2098 #define pci_root_bus_fwnode(bus) NULL
2099 #endif
2100
2101 /*
2102 * These helpers provide future and backwards compatibility
2103 * for accessing popular PCI BAR info
2104 */
2105 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)])
2106 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start)
2107 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end)
2108 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags)
2109 #define pci_resource_len(dev,bar) \
2110 (pci_resource_end((dev), (bar)) ? \
2111 resource_size(pci_resource_n((dev), (bar))) : 0)
2112
2113 #define __pci_dev_for_each_res0(dev, res, ...) \
2114 for (unsigned int __b = 0; \
2115 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2116 __b++)
2117
2118 #define __pci_dev_for_each_res1(dev, res, __b) \
2119 for (__b = 0; \
2120 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2121 __b++)
2122
2123 #define pci_dev_for_each_resource(dev, res, ...) \
2124 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
2125 (dev, res, __VA_ARGS__)
2126
2127 /*
2128 * Similar to the helpers above, these manipulate per-pci_dev
2129 * driver-specific data. They are really just a wrapper around
2130 * the generic device structure functions of these calls.
2131 */
2132 static inline void *pci_get_drvdata(struct pci_dev *pdev)
2133 {
2134 return dev_get_drvdata(&pdev->dev);
2135 }
2136
2137 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
2138 {
2139 dev_set_drvdata(&pdev->dev, data);
2140 }
2141
2142 static inline const char *pci_name(const struct pci_dev *pdev)
2143 {
2144 return dev_name(&pdev->dev);
2145 }
2146
2147 void pci_resource_to_user(const struct pci_dev *dev, int bar,
2148 const struct resource *rsrc,
2149 resource_size_t *start, resource_size_t *end);
2150
2151 /*
2152 * The world is not perfect and supplies us with broken PCI devices.
2153 * For at least a part of these bugs we need a work-around, so both
2154 * generic (drivers/pci/quirks.c) and per-architecture code can define
2155 * fixup hooks to be called for particular buggy devices.
2156 */
2157
2158 struct pci_fixup {
2159 u16 vendor; /* Or PCI_ANY_ID */
2160 u16 device; /* Or PCI_ANY_ID */
2161 u32 class; /* Or PCI_ANY_ID */
2162 unsigned int class_shift; /* should be 0, 8, 16 */
2163 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2164 int hook_offset;
2165 #else
2166 void (*hook)(struct pci_dev *dev);
2167 #endif
2168 };
2169
2170 enum pci_fixup_pass {
2171 pci_fixup_early, /* Before probing BARs */
2172 pci_fixup_header, /* After reading configuration header */
2173 pci_fixup_final, /* Final phase of device fixups */
2174 pci_fixup_enable, /* pci_enable_device() time */
2175 pci_fixup_resume, /* pci_device_resume() */
2176 pci_fixup_suspend, /* pci_device_suspend() */
2177 pci_fixup_resume_early, /* pci_device_resume_early() */
2178 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2179 };
2180
2181 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2182 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2183 class_shift, hook) \
2184 __ADDRESSABLE(hook) \
2185 asm(".section " #sec ", \"a\" \n" \
2186 ".balign 16 \n" \
2187 ".short " #vendor ", " #device " \n" \
2188 ".long " #class ", " #class_shift " \n" \
2189 ".long " #hook " - . \n" \
2190 ".previous \n");
2191
2192 /*
2193 * Clang's LTO may rename static functions in C, but has no way to
2194 * handle such renamings when referenced from inline asm. To work
2195 * around this, create global C stubs for these cases.
2196 */
2197 #ifdef CONFIG_LTO_CLANG
2198 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2199 class_shift, hook, stub) \
2200 void stub(struct pci_dev *dev); \
2201 void stub(struct pci_dev *dev) \
2202 { \
2203 hook(dev); \
2204 } \
2205 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2206 class_shift, stub)
2207 #else
2208 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2209 class_shift, hook, stub) \
2210 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2211 class_shift, hook)
2212 #endif
2213
2214 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2215 class_shift, hook) \
2216 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2217 class_shift, hook, __UNIQUE_ID(hook))
2218 #else
2219 /* Anonymous variables would be nice... */
2220 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2221 class_shift, hook) \
2222 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2223 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2224 = { vendor, device, class, class_shift, hook };
2225 #endif
2226
2227 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2228 class_shift, hook) \
2229 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2230 hook, vendor, device, class, class_shift, hook)
2231 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2232 class_shift, hook) \
2233 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2234 hook, vendor, device, class, class_shift, hook)
2235 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2236 class_shift, hook) \
2237 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2238 hook, vendor, device, class, class_shift, hook)
2239 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2240 class_shift, hook) \
2241 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2242 hook, vendor, device, class, class_shift, hook)
2243 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2244 class_shift, hook) \
2245 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2246 resume##hook, vendor, device, class, class_shift, hook)
2247 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2248 class_shift, hook) \
2249 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2250 resume_early##hook, vendor, device, class, class_shift, hook)
2251 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2252 class_shift, hook) \
2253 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2254 suspend##hook, vendor, device, class, class_shift, hook)
2255 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2256 class_shift, hook) \
2257 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2258 suspend_late##hook, vendor, device, class, class_shift, hook)
2259
2260 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2261 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2262 hook, vendor, device, PCI_ANY_ID, 0, hook)
2263 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2264 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2265 hook, vendor, device, PCI_ANY_ID, 0, hook)
2266 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2267 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2268 hook, vendor, device, PCI_ANY_ID, 0, hook)
2269 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2270 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2271 hook, vendor, device, PCI_ANY_ID, 0, hook)
2272 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2273 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2274 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2275 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2276 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2277 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2278 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2279 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2280 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2281 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2282 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2283 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2284
2285 #ifdef CONFIG_PCI_QUIRKS
2286 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2287 #else
2288 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2289 struct pci_dev *dev) { }
2290 #endif
2291
2292 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2293 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2294 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2295 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2296 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2297 const char *name);
2298 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2299 void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar,
2300 unsigned long offset, unsigned long len);
2301
2302 extern int pci_pci_problems;
2303 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2304 #define PCIPCI_TRITON 2
2305 #define PCIPCI_NATOMA 4
2306 #define PCIPCI_VIAETBF 8
2307 #define PCIPCI_VSFX 16
2308 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2309 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2310
2311 extern unsigned long pci_cardbus_io_size;
2312 extern unsigned long pci_cardbus_mem_size;
2313 extern u8 pci_dfl_cache_line_size;
2314 extern u8 pci_cache_line_size;
2315
2316 /* Architecture-specific versions may override these (weak) */
2317 void pcibios_disable_device(struct pci_dev *dev);
2318 void pcibios_set_master(struct pci_dev *dev);
2319 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2320 enum pcie_reset_state state);
2321 int pcibios_device_add(struct pci_dev *dev);
2322 void pcibios_release_device(struct pci_dev *dev);
2323 #ifdef CONFIG_PCI
2324 void pcibios_penalize_isa_irq(int irq, int active);
2325 #else
2326 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2327 #endif
2328 int pcibios_alloc_irq(struct pci_dev *dev);
2329 void pcibios_free_irq(struct pci_dev *dev);
2330 resource_size_t pcibios_default_alignment(void);
2331
2332 #if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)
2333 extern int pci_create_resource_files(struct pci_dev *dev);
2334 extern void pci_remove_resource_files(struct pci_dev *dev);
2335 #endif
2336
2337 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2338 void __init pci_mmcfg_early_init(void);
2339 void __init pci_mmcfg_late_init(void);
2340 #else
2341 static inline void pci_mmcfg_early_init(void) { }
2342 static inline void pci_mmcfg_late_init(void) { }
2343 #endif
2344
2345 int pci_ext_cfg_avail(void);
2346
2347 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2348 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2349
2350 #ifdef CONFIG_PCI_IOV
2351 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2352 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2353 int pci_iov_vf_id(struct pci_dev *dev);
2354 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2355 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2356 void pci_disable_sriov(struct pci_dev *dev);
2357
2358 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2359 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2360 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2361 int pci_num_vf(struct pci_dev *dev);
2362 int pci_vfs_assigned(struct pci_dev *dev);
2363 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2364 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2365 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2366 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2367 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2368
2369 /* Arch may override these (weak) */
2370 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2371 int pcibios_sriov_disable(struct pci_dev *pdev);
2372 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2373 #else
2374 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2375 {
2376 return -ENOSYS;
2377 }
2378 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2379 {
2380 return -ENOSYS;
2381 }
2382
2383 static inline int pci_iov_vf_id(struct pci_dev *dev)
2384 {
2385 return -ENOSYS;
2386 }
2387
2388 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2389 struct pci_driver *pf_driver)
2390 {
2391 return ERR_PTR(-EINVAL);
2392 }
2393
2394 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2395 { return -ENODEV; }
2396
2397 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2398 struct pci_dev *virtfn, int id)
2399 {
2400 return -ENODEV;
2401 }
2402 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2403 {
2404 return -ENOSYS;
2405 }
2406 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2407 int id) { }
2408 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2409 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2410 static inline int pci_vfs_assigned(struct pci_dev *dev)
2411 { return 0; }
2412 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2413 { return 0; }
2414 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2415 { return 0; }
2416 #define pci_sriov_configure_simple NULL
2417 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2418 { return 0; }
2419 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2420 #endif
2421
2422 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2423 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2424 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2425 #endif
2426
2427 /**
2428 * pci_pcie_cap - get the saved PCIe capability offset
2429 * @dev: PCI device
2430 *
2431 * PCIe capability offset is calculated at PCI device initialization
2432 * time and saved in the data structure. This function returns saved
2433 * PCIe capability offset. Using this instead of pci_find_capability()
2434 * reduces unnecessary search in the PCI configuration space. If you
2435 * need to calculate PCIe capability offset from raw device for some
2436 * reasons, please use pci_find_capability() instead.
2437 */
2438 static inline int pci_pcie_cap(struct pci_dev *dev)
2439 {
2440 return dev->pcie_cap;
2441 }
2442
2443 /**
2444 * pci_is_pcie - check if the PCI device is PCI Express capable
2445 * @dev: PCI device
2446 *
2447 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2448 */
2449 static inline bool pci_is_pcie(struct pci_dev *dev)
2450 {
2451 return pci_pcie_cap(dev);
2452 }
2453
2454 /**
2455 * pcie_caps_reg - get the PCIe Capabilities Register
2456 * @dev: PCI device
2457 */
2458 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2459 {
2460 return dev->pcie_flags_reg;
2461 }
2462
2463 /**
2464 * pci_pcie_type - get the PCIe device/port type
2465 * @dev: PCI device
2466 */
2467 static inline int pci_pcie_type(const struct pci_dev *dev)
2468 {
2469 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2470 }
2471
2472 /**
2473 * pcie_find_root_port - Get the PCIe root port device
2474 * @dev: PCI device
2475 *
2476 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2477 * for a given PCI/PCIe Device.
2478 */
2479 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2480 {
2481 while (dev) {
2482 if (pci_is_pcie(dev) &&
2483 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2484 return dev;
2485 dev = pci_upstream_bridge(dev);
2486 }
2487
2488 return NULL;
2489 }
2490
2491 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
2492 {
2493 /*
2494 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg()
2495 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache
2496 * the value (e.g. inside the loop in pci_dev_wait()).
2497 */
2498 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure;
2499 }
2500
2501 void pci_request_acs(void);
2502 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2503 bool pci_acs_path_enabled(struct pci_dev *start,
2504 struct pci_dev *end, u16 acs_flags);
2505 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2506
2507 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2508 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2509
2510 /* Large Resource Data Type Tag Item Names */
2511 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2512 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2513 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2514
2515 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2516 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2517 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2518
2519 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2520 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2521 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2522 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2523 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2524
2525 /**
2526 * pci_vpd_alloc - Allocate buffer and read VPD into it
2527 * @dev: PCI device
2528 * @size: pointer to field where VPD length is returned
2529 *
2530 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2531 */
2532 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2533
2534 /**
2535 * pci_vpd_find_id_string - Locate id string in VPD
2536 * @buf: Pointer to buffered VPD data
2537 * @len: The length of the buffer area in which to search
2538 * @size: Pointer to field where length of id string is returned
2539 *
2540 * Returns the index of the id string or -ENOENT if not found.
2541 */
2542 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2543
2544 /**
2545 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2546 * @buf: Pointer to buffered VPD data
2547 * @len: The length of the buffer area in which to search
2548 * @kw: The keyword to search for
2549 * @size: Pointer to field where length of found keyword data is returned
2550 *
2551 * Returns the index of the information field keyword data or -ENOENT if
2552 * not found.
2553 */
2554 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2555 const char *kw, unsigned int *size);
2556
2557 /**
2558 * pci_vpd_check_csum - Check VPD checksum
2559 * @buf: Pointer to buffered VPD data
2560 * @len: VPD size
2561 *
2562 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2563 */
2564 int pci_vpd_check_csum(const void *buf, unsigned int len);
2565
2566 /* PCI <-> OF binding helpers */
2567 #ifdef CONFIG_OF
2568 struct device_node;
2569 struct irq_domain;
2570 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2571 bool pci_host_of_has_msi_map(struct device *dev);
2572
2573 /* Arch may override this (weak) */
2574 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2575
2576 #else /* CONFIG_OF */
2577 static inline struct irq_domain *
2578 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2579 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2580 #endif /* CONFIG_OF */
2581
2582 static inline struct device_node *
2583 pci_device_to_OF_node(const struct pci_dev *pdev)
2584 {
2585 return pdev ? pdev->dev.of_node : NULL;
2586 }
2587
2588 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2589 {
2590 return bus ? bus->dev.of_node : NULL;
2591 }
2592
2593 #ifdef CONFIG_ACPI
2594 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2595
2596 void
2597 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2598 bool pci_pr3_present(struct pci_dev *pdev);
2599 #else
2600 static inline struct irq_domain *
2601 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2602 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2603 #endif
2604
2605 #ifdef CONFIG_EEH
2606 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2607 {
2608 return pdev->dev.archdata.edev;
2609 }
2610 #endif
2611
2612 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2613 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2614 int pci_for_each_dma_alias(struct pci_dev *pdev,
2615 int (*fn)(struct pci_dev *pdev,
2616 u16 alias, void *data), void *data);
2617
2618 /* Helper functions for operation of device flag */
2619 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2620 {
2621 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2622 }
2623 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2624 {
2625 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2626 }
2627 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2628 {
2629 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2630 }
2631
2632 /**
2633 * pci_ari_enabled - query ARI forwarding status
2634 * @bus: the PCI bus
2635 *
2636 * Returns true if ARI forwarding is enabled.
2637 */
2638 static inline bool pci_ari_enabled(struct pci_bus *bus)
2639 {
2640 return bus->self && bus->self->ari_enabled;
2641 }
2642
2643 /**
2644 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2645 * @pdev: PCI device to check
2646 *
2647 * Walk upwards from @pdev and check for each encountered bridge if it's part
2648 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2649 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2650 */
2651 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2652 {
2653 struct pci_dev *parent = pdev;
2654
2655 if (pdev->is_thunderbolt)
2656 return true;
2657
2658 while ((parent = pci_upstream_bridge(parent)))
2659 if (parent->is_thunderbolt)
2660 return true;
2661
2662 return false;
2663 }
2664
2665 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2666 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2667 #endif
2668
2669 #include <linux/dma-mapping.h>
2670
2671 #define pci_printk(level, pdev, fmt, arg...) \
2672 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2673
2674 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2675 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2676 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2677 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2678 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2679 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
2680 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2681 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2682 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2683
2684 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2685 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2686
2687 #define pci_info_ratelimited(pdev, fmt, arg...) \
2688 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2689
2690 #define pci_WARN(pdev, condition, fmt, arg...) \
2691 WARN(condition, "%s %s: " fmt, \
2692 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2693
2694 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2695 WARN_ONCE(condition, "%s %s: " fmt, \
2696 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2697
2698 #endif /* LINUX_PCI_H */
2699
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