1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_SMSCPHY_H__ 3 #define __LINUX_SMSCPHY_H__ 4 5 #define MII_LAN83C185_ISF 29 /* Interrupt Source Flags */ 6 #define MII_LAN83C185_IM 30 /* Interrupt Mask */ 7 #define MII_LAN83C185_CTRL_STATUS 17 /* Mode/Status Register */ 8 #define MII_LAN83C185_SPECIAL_MODES 18 /* Special Modes Register */ 9 10 #define MII_LAN83C185_ISF_INT1 (1<<1) /* Auto-Negotiation Page Received */ 11 #define MII_LAN83C185_ISF_INT2 (1<<2) /* Parallel Detection Fault */ 12 #define MII_LAN83C185_ISF_INT3 (1<<3) /* Auto-Negotiation LP Ack */ 13 #define MII_LAN83C185_ISF_INT4 (1<<4) /* Link Down */ 14 #define MII_LAN83C185_ISF_INT5 (1<<5) /* Remote Fault Detected */ 15 #define MII_LAN83C185_ISF_INT6 (1<<6) /* Auto-Negotiation complete */ 16 #define MII_LAN83C185_ISF_INT7 (1<<7) /* ENERGYON */ 17 18 #define MII_LAN83C185_ISF_INT_ALL (0x0e) 19 20 #define MII_LAN83C185_ISF_INT_PHYLIB_EVENTS \ 21 (MII_LAN83C185_ISF_INT6 | MII_LAN83C185_ISF_INT4 | \ 22 MII_LAN83C185_ISF_INT7) 23 24 #define MII_LAN83C185_EDPWRDOWN (1 << 13) /* EDPWRDOWN */ 25 #define MII_LAN83C185_ENERGYON (1 << 1) /* ENERGYON */ 26 27 #define MII_LAN83C185_MODE_MASK 0xE0 28 #define MII_LAN83C185_MODE_POWERDOWN 0xC0 /* Power Down mode */ 29 #define MII_LAN83C185_MODE_ALL 0xE0 /* All capable mode */ 30 31 int smsc_phy_config_intr(struct phy_device *phydev); 32 irqreturn_t smsc_phy_handle_interrupt(struct phy_device *phydev); 33 int smsc_phy_config_init(struct phy_device *phydev); 34 int lan87xx_read_status(struct phy_device *phydev); 35 int smsc_phy_get_tunable(struct phy_device *phydev, 36 struct ethtool_tunable *tuna, void *data); 37 int smsc_phy_set_tunable(struct phy_device *phydev, 38 struct ethtool_tunable *tuna, const void *data); 39 int smsc_phy_probe(struct phy_device *phydev); 40 41 #define MII_LAN874X_PHY_MMD_WOL_WUCSR 0x8010 42 #define MII_LAN874X_PHY_MMD_WOL_WUF_CFGA 0x8011 43 #define MII_LAN874X_PHY_MMD_WOL_WUF_CFGB 0x8012 44 #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK0 0x8021 45 #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK1 0x8022 46 #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK2 0x8023 47 #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK3 0x8024 48 #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK4 0x8025 49 #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK5 0x8026 50 #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK6 0x8027 51 #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK7 0x8028 52 #define MII_LAN874X_PHY_MMD_WOL_RX_ADDRA 0x8061 53 #define MII_LAN874X_PHY_MMD_WOL_RX_ADDRB 0x8062 54 #define MII_LAN874X_PHY_MMD_WOL_RX_ADDRC 0x8063 55 #define MII_LAN874X_PHY_MMD_MCFGR 0x8064 56 57 #define MII_LAN874X_PHY_PME1_SET (2 << 13) 58 #define MII_LAN874X_PHY_PME2_SET (2 << 11) 59 #define MII_LAN874X_PHY_PME_SELF_CLEAR BIT(9) 60 #define MII_LAN874X_PHY_WOL_PFDA_FR BIT(7) 61 #define MII_LAN874X_PHY_WOL_WUFR BIT(6) 62 #define MII_LAN874X_PHY_WOL_MPR BIT(5) 63 #define MII_LAN874X_PHY_WOL_BCAST_FR BIT(4) 64 #define MII_LAN874X_PHY_WOL_PFDAEN BIT(3) 65 #define MII_LAN874X_PHY_WOL_WUEN BIT(2) 66 #define MII_LAN874X_PHY_WOL_MPEN BIT(1) 67 #define MII_LAN874X_PHY_WOL_BCSTEN BIT(0) 68 69 #define MII_LAN874X_PHY_WOL_FILTER_EN BIT(15) 70 #define MII_LAN874X_PHY_WOL_FILTER_MCASTTEN BIT(9) 71 #define MII_LAN874X_PHY_WOL_FILTER_BCSTEN BIT(8) 72 73 #define MII_LAN874X_PHY_PME_SELF_CLEAR_DELAY 0x1000 /* 81 milliseconds */ 74 75 #endif /* __LINUX_SMSCPHY_H__ */ 76
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