1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * include/linux/spi/mxs-spi.h
4 *
5 * Freescale i.MX233/i.MX28 SPI controller register definition
6 *
7 * Copyright 2008 Embedded Alley Solutions, Inc.
8 * Copyright 2009-2011 Freescale Semiconductor, Inc.
9 */
10
11 #ifndef __LINUX_SPI_MXS_SPI_H__
12 #define __LINUX_SPI_MXS_SPI_H__
13
14 #include <linux/dmaengine.h>
15
16 #define ssp_is_old(host) ((host)->devid == IMX23_SSP)
17
18 /* SSP registers */
19 #define HW_SSP_CTRL0 0x000
20 #define BM_SSP_CTRL0_RUN (1 << 29)
21 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
22 #define BM_SSP_CTRL0_LOCK_CS (1 << 27)
23 #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
24 #define BM_SSP_CTRL0_READ (1 << 25)
25 #define BM_SSP_CTRL0_DATA_XFER (1 << 24)
26 #define BP_SSP_CTRL0_BUS_WIDTH 22
27 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
28 #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
29 #define BM_SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
30 #define BM_SSP_CTRL0_LONG_RESP (1 << 19)
31 #define BM_SSP_CTRL0_GET_RESP (1 << 17)
32 #define BM_SSP_CTRL0_ENABLE (1 << 16)
33 #define BP_SSP_CTRL0_XFER_COUNT 0
34 #define BM_SSP_CTRL0_XFER_COUNT 0xffff
35 #define HW_SSP_CMD0 0x010
36 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
37 #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
38 #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
39 #define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
40 #define BP_SSP_CMD0_BLOCK_SIZE 16
41 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
42 #define BP_SSP_CMD0_BLOCK_COUNT 8
43 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
44 #define BP_SSP_CMD0_CMD 0
45 #define BM_SSP_CMD0_CMD 0xff
46 #define HW_SSP_CMD1 0x020
47 #define HW_SSP_XFER_SIZE 0x030
48 #define HW_SSP_BLOCK_SIZE 0x040
49 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4
50 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
51 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0
52 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0xf
53 #define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
54 #define BP_SSP_TIMING_TIMEOUT 16
55 #define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
56 #define BP_SSP_TIMING_CLOCK_DIVIDE 8
57 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
60 #define BP_SSP_TIMING_CLOCK_RATE 0
61 #define BM_SSP_TIMING_CLOCK_RATE 0xff
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
64 #define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
65 #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
66 #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
67 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
68 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
69 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
70 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
71 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
72 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
73 #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
74 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
75 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
76 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
77 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
78 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
79 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
80 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
81 #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
82 #define BM_SSP_CTRL1_PHASE (1 << 10)
83 #define BM_SSP_CTRL1_POLARITY (1 << 9)
84 #define BP_SSP_CTRL1_WORD_LENGTH 4
85 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
88 #define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
89 #define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
90 #define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF
91 #define BP_SSP_CTRL1_SSP_MODE 0
92 #define BM_SSP_CTRL1_SSP_MODE 0xf
93 #define BF_SSP_CTRL1_SSP_MODE(v) \
94 (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
95 #define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
96 #define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
97 #define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
98 #define BV_SSP_CTRL1_SSP_MODE__MS 0x4
99
100 #define HW_SSP_DATA(h) (ssp_is_old(h) ? 0x070 : 0x090)
101
102 #define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
103 #define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
104 #define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
105 #define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
106 #define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
107 #define BM_SSP_STATUS_CARD_DETECT (1 << 28)
108 #define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
109 #define BM_SSP_STATUS_FIFO_EMPTY (1 << 5)
110
111 #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
112
113 #define SSP_PIO_NUM 3
114
115 enum mxs_ssp_id {
116 IMX23_SSP,
117 IMX28_SSP,
118 };
119
120 struct mxs_ssp {
121 struct device *dev;
122 void __iomem *base;
123 struct clk *clk;
124 unsigned int clk_rate;
125 enum mxs_ssp_id devid;
126
127 struct dma_chan *dmach;
128 unsigned int dma_dir;
129 enum dma_transfer_direction slave_dirn;
130 u32 ssp_pio_words[SSP_PIO_NUM];
131 };
132
133 void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);
134
135 #endif /* __LINUX_SPI_MXS_SPI_H__ */
136
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