1 /* SPDX-License-Identifier: GPL-2.0-or-later
2 *
3 * Copyright (C) 2005 David Brownell
4 */
5
6 #ifndef __LINUX_SPI_H
7 #define __LINUX_SPI_H
8
9 #include <linux/acpi.h>
10 #include <linux/bits.h>
11 #include <linux/completion.h>
12 #include <linux/device.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/kthread.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/overflow.h>
17 #include <linux/scatterlist.h>
18 #include <linux/slab.h>
19 #include <linux/u64_stats_sync.h>
20
21 #include <uapi/linux/spi/spi.h>
22
23 /* Max no. of CS supported per spi device */
24 #define SPI_CS_CNT_MAX 16
25
26 struct dma_chan;
27 struct software_node;
28 struct ptp_system_timestamp;
29 struct spi_controller;
30 struct spi_transfer;
31 struct spi_controller_mem_ops;
32 struct spi_controller_mem_caps;
33 struct spi_message;
34
35 /*
36 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
37 * and SPI infrastructure.
38 */
39 extern const struct bus_type spi_bus_type;
40
41 /**
42 * struct spi_statistics - statistics for spi transfers
43 * @syncp: seqcount to protect members in this struct for per-cpu update
44 * on 32-bit systems
45 *
46 * @messages: number of spi-messages handled
47 * @transfers: number of spi_transfers handled
48 * @errors: number of errors during spi_transfer
49 * @timedout: number of timeouts during spi_transfer
50 *
51 * @spi_sync: number of times spi_sync is used
52 * @spi_sync_immediate:
53 * number of times spi_sync is executed immediately
54 * in calling context without queuing and scheduling
55 * @spi_async: number of times spi_async is used
56 *
57 * @bytes: number of bytes transferred to/from device
58 * @bytes_tx: number of bytes sent to device
59 * @bytes_rx: number of bytes received from device
60 *
61 * @transfer_bytes_histo:
62 * transfer bytes histogram
63 *
64 * @transfers_split_maxsize:
65 * number of transfers that have been split because of
66 * maxsize limit
67 */
68 struct spi_statistics {
69 struct u64_stats_sync syncp;
70
71 u64_stats_t messages;
72 u64_stats_t transfers;
73 u64_stats_t errors;
74 u64_stats_t timedout;
75
76 u64_stats_t spi_sync;
77 u64_stats_t spi_sync_immediate;
78 u64_stats_t spi_async;
79
80 u64_stats_t bytes;
81 u64_stats_t bytes_rx;
82 u64_stats_t bytes_tx;
83
84 #define SPI_STATISTICS_HISTO_SIZE 17
85 u64_stats_t transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE];
86
87 u64_stats_t transfers_split_maxsize;
88 };
89
90 #define SPI_STATISTICS_ADD_TO_FIELD(pcpu_stats, field, count) \
91 do { \
92 struct spi_statistics *__lstats; \
93 get_cpu(); \
94 __lstats = this_cpu_ptr(pcpu_stats); \
95 u64_stats_update_begin(&__lstats->syncp); \
96 u64_stats_add(&__lstats->field, count); \
97 u64_stats_update_end(&__lstats->syncp); \
98 put_cpu(); \
99 } while (0)
100
101 #define SPI_STATISTICS_INCREMENT_FIELD(pcpu_stats, field) \
102 do { \
103 struct spi_statistics *__lstats; \
104 get_cpu(); \
105 __lstats = this_cpu_ptr(pcpu_stats); \
106 u64_stats_update_begin(&__lstats->syncp); \
107 u64_stats_inc(&__lstats->field); \
108 u64_stats_update_end(&__lstats->syncp); \
109 put_cpu(); \
110 } while (0)
111
112 /**
113 * struct spi_delay - SPI delay information
114 * @value: Value for the delay
115 * @unit: Unit for the delay
116 */
117 struct spi_delay {
118 #define SPI_DELAY_UNIT_USECS 0
119 #define SPI_DELAY_UNIT_NSECS 1
120 #define SPI_DELAY_UNIT_SCK 2
121 u16 value;
122 u8 unit;
123 };
124
125 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer);
126 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer);
127 extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
128 struct spi_transfer *xfer);
129
130 /**
131 * struct spi_device - Controller side proxy for an SPI slave device
132 * @dev: Driver model representation of the device.
133 * @controller: SPI controller used with the device.
134 * @max_speed_hz: Maximum clock rate to be used with this chip
135 * (on this board); may be changed by the device's driver.
136 * The spi_transfer.speed_hz can override this for each transfer.
137 * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
138 * the corresponding physical CS for logical CS i.
139 * @mode: The spi mode defines how data is clocked out and in.
140 * This may be changed by the device's driver.
141 * The "active low" default for chipselect mode can be overridden
142 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for
143 * each word in a transfer (by specifying SPI_LSB_FIRST).
144 * @bits_per_word: Data transfers involve one or more words; word sizes
145 * like eight or 12 bits are common. In-memory wordsizes are
146 * powers of two bytes (e.g. 20 bit samples use 32 bits).
147 * This may be changed by the device's driver, or left at the
148 * default (0) indicating protocol words are eight bit bytes.
149 * The spi_transfer.bits_per_word can override this for each transfer.
150 * @rt: Make the pump thread real time priority.
151 * @irq: Negative, or the number passed to request_irq() to receive
152 * interrupts from this device.
153 * @controller_state: Controller's runtime state
154 * @controller_data: Board-specific definitions for controller, such as
155 * FIFO initialization parameters; from board_info.controller_data
156 * @modalias: Name of the driver to use with this device, or an alias
157 * for that name. This appears in the sysfs "modalias" attribute
158 * for driver coldplugging, and in uevents used for hotplugging
159 * @driver_override: If the name of a driver is written to this attribute, then
160 * the device will bind to the named driver and only the named driver.
161 * Do not set directly, because core frees it; use driver_set_override() to
162 * set or clear it.
163 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines
164 * (optional, NULL when not using a GPIO line)
165 * @word_delay: delay to be inserted between consecutive
166 * words of a transfer
167 * @cs_setup: delay to be introduced by the controller after CS is asserted
168 * @cs_hold: delay to be introduced by the controller before CS is deasserted
169 * @cs_inactive: delay to be introduced by the controller after CS is
170 * deasserted. If @cs_change_delay is used from @spi_transfer, then the
171 * two delays will be added up.
172 * @pcpu_statistics: statistics for the spi_device
173 * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array
174 *
175 * A @spi_device is used to interchange data between an SPI slave
176 * (usually a discrete chip) and CPU memory.
177 *
178 * In @dev, the platform_data is used to hold information about this
179 * device that's meaningful to the device's protocol driver, but not
180 * to its controller. One example might be an identifier for a chip
181 * variant with slightly different functionality; another might be
182 * information about how this particular board wires the chip's pins.
183 */
184 struct spi_device {
185 struct device dev;
186 struct spi_controller *controller;
187 u32 max_speed_hz;
188 u8 chip_select[SPI_CS_CNT_MAX];
189 u8 bits_per_word;
190 bool rt;
191 #define SPI_NO_TX BIT(31) /* No transmit wire */
192 #define SPI_NO_RX BIT(30) /* No receive wire */
193 /*
194 * TPM specification defines flow control over SPI. Client device
195 * can insert a wait state on MISO when address is transmitted by
196 * controller on MOSI. Detecting the wait state in software is only
197 * possible for full duplex controllers. For controllers that support
198 * only half-duplex, the wait state detection needs to be implemented
199 * in hardware. TPM devices would set this flag when hardware flow
200 * control is expected from SPI controller.
201 */
202 #define SPI_TPM_HW_FLOW BIT(29) /* TPM HW flow control */
203 /*
204 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK.
205 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart,
206 * which is defined in 'include/uapi/linux/spi/spi.h'.
207 * The bits defined here are from bit 31 downwards, while in
208 * SPI_MODE_USER_MASK are from 0 upwards.
209 * These bits must not overlap. A static assert check should make sure of that.
210 * If adding extra bits, make sure to decrease the bit index below as well.
211 */
212 #define SPI_MODE_KERNEL_MASK (~(BIT(29) - 1))
213 u32 mode;
214 int irq;
215 void *controller_state;
216 void *controller_data;
217 char modalias[SPI_NAME_SIZE];
218 const char *driver_override;
219 struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */
220 struct spi_delay word_delay; /* Inter-word delay */
221 /* CS delays */
222 struct spi_delay cs_setup;
223 struct spi_delay cs_hold;
224 struct spi_delay cs_inactive;
225
226 /* The statistics */
227 struct spi_statistics __percpu *pcpu_statistics;
228
229 /* Bit mask of the chipselect(s) that the driver need to use from
230 * the chipselect array.When the controller is capable to handle
231 * multiple chip selects & memories are connected in parallel
232 * then more than one bit need to be set in cs_index_mask.
233 */
234 u32 cs_index_mask : SPI_CS_CNT_MAX;
235
236 /*
237 * Likely need more hooks for more protocol options affecting how
238 * the controller talks to each chip, like:
239 * - memory packing (12 bit samples into low bits, others zeroed)
240 * - priority
241 * - chipselect delays
242 * - ...
243 */
244 };
245
246 /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */
247 static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0,
248 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap");
249
250 static inline struct spi_device *to_spi_device(const struct device *dev)
251 {
252 return dev ? container_of(dev, struct spi_device, dev) : NULL;
253 }
254
255 /* Most drivers won't need to care about device refcounting */
256 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
257 {
258 return (spi && get_device(&spi->dev)) ? spi : NULL;
259 }
260
261 static inline void spi_dev_put(struct spi_device *spi)
262 {
263 if (spi)
264 put_device(&spi->dev);
265 }
266
267 /* ctldata is for the bus_controller driver's runtime state */
268 static inline void *spi_get_ctldata(const struct spi_device *spi)
269 {
270 return spi->controller_state;
271 }
272
273 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
274 {
275 spi->controller_state = state;
276 }
277
278 /* Device driver data */
279
280 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
281 {
282 dev_set_drvdata(&spi->dev, data);
283 }
284
285 static inline void *spi_get_drvdata(const struct spi_device *spi)
286 {
287 return dev_get_drvdata(&spi->dev);
288 }
289
290 static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
291 {
292 return spi->chip_select[idx];
293 }
294
295 static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect)
296 {
297 spi->chip_select[idx] = chipselect;
298 }
299
300 static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx)
301 {
302 return spi->cs_gpiod[idx];
303 }
304
305 static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod)
306 {
307 spi->cs_gpiod[idx] = csgpiod;
308 }
309
310 static inline bool spi_is_csgpiod(struct spi_device *spi)
311 {
312 u8 idx;
313
314 for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
315 if (spi_get_csgpiod(spi, idx))
316 return true;
317 }
318 return false;
319 }
320
321 /**
322 * struct spi_driver - Host side "protocol" driver
323 * @id_table: List of SPI devices supported by this driver
324 * @probe: Binds this driver to the SPI device. Drivers can verify
325 * that the device is actually present, and may need to configure
326 * characteristics (such as bits_per_word) which weren't needed for
327 * the initial configuration done during system setup.
328 * @remove: Unbinds this driver from the SPI device
329 * @shutdown: Standard shutdown callback used during system state
330 * transitions such as powerdown/halt and kexec
331 * @driver: SPI device drivers should initialize the name and owner
332 * field of this structure.
333 *
334 * This represents the kind of device driver that uses SPI messages to
335 * interact with the hardware at the other end of a SPI link. It's called
336 * a "protocol" driver because it works through messages rather than talking
337 * directly to SPI hardware (which is what the underlying SPI controller
338 * driver does to pass those messages). These protocols are defined in the
339 * specification for the device(s) supported by the driver.
340 *
341 * As a rule, those device protocols represent the lowest level interface
342 * supported by a driver, and it will support upper level interfaces too.
343 * Examples of such upper levels include frameworks like MTD, networking,
344 * MMC, RTC, filesystem character device nodes, and hardware monitoring.
345 */
346 struct spi_driver {
347 const struct spi_device_id *id_table;
348 int (*probe)(struct spi_device *spi);
349 void (*remove)(struct spi_device *spi);
350 void (*shutdown)(struct spi_device *spi);
351 struct device_driver driver;
352 };
353
354 #define to_spi_driver(__drv) \
355 ( __drv ? container_of_const(__drv, struct spi_driver, driver) : NULL )
356
357 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv);
358
359 /**
360 * spi_unregister_driver - reverse effect of spi_register_driver
361 * @sdrv: the driver to unregister
362 * Context: can sleep
363 */
364 static inline void spi_unregister_driver(struct spi_driver *sdrv)
365 {
366 if (sdrv)
367 driver_unregister(&sdrv->driver);
368 }
369
370 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select);
371
372 /* Use a define to avoid include chaining to get THIS_MODULE */
373 #define spi_register_driver(driver) \
374 __spi_register_driver(THIS_MODULE, driver)
375
376 /**
377 * module_spi_driver() - Helper macro for registering a SPI driver
378 * @__spi_driver: spi_driver struct
379 *
380 * Helper macro for SPI drivers which do not do anything special in module
381 * init/exit. This eliminates a lot of boilerplate. Each module may only
382 * use this macro once, and calling it replaces module_init() and module_exit()
383 */
384 #define module_spi_driver(__spi_driver) \
385 module_driver(__spi_driver, spi_register_driver, \
386 spi_unregister_driver)
387
388 /**
389 * struct spi_controller - interface to SPI master or slave controller
390 * @dev: device interface to this driver
391 * @list: link with the global spi_controller list
392 * @bus_num: board-specific (and often SOC-specific) identifier for a
393 * given SPI controller.
394 * @num_chipselect: chipselects are used to distinguish individual
395 * SPI slaves, and are numbered from zero to num_chipselects.
396 * each slave has a chipselect signal, but it's common that not
397 * every chipselect is connected to a slave.
398 * @dma_alignment: SPI controller constraint on DMA buffers alignment.
399 * @mode_bits: flags understood by this controller driver
400 * @buswidth_override_bits: flags to override for this controller driver
401 * @bits_per_word_mask: A mask indicating which values of bits_per_word are
402 * supported by the driver. Bit n indicates that a bits_per_word n+1 is
403 * supported. If set, the SPI core will reject any transfer with an
404 * unsupported bits_per_word. If not set, this value is simply ignored,
405 * and it's up to the individual driver to perform any validation.
406 * @min_speed_hz: Lowest supported transfer speed
407 * @max_speed_hz: Highest supported transfer speed
408 * @flags: other constraints relevant to this driver
409 * @slave: indicates that this is an SPI slave controller
410 * @target: indicates that this is an SPI target controller
411 * @devm_allocated: whether the allocation of this struct is devres-managed
412 * @max_transfer_size: function that returns the max transfer size for
413 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
414 * @max_message_size: function that returns the max message size for
415 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
416 * @io_mutex: mutex for physical bus access
417 * @add_lock: mutex to avoid adding devices to the same chipselect
418 * @bus_lock_spinlock: spinlock for SPI bus locking
419 * @bus_lock_mutex: mutex for exclusion of multiple callers
420 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
421 * @setup: updates the device mode and clocking records used by a
422 * device's SPI controller; protocol code may call this. This
423 * must fail if an unrecognized or unsupported mode is requested.
424 * It's always safe to call this unless transfers are pending on
425 * the device whose settings are being modified.
426 * @set_cs_timing: optional hook for SPI devices to request SPI master
427 * controller for configuring specific CS setup time, hold time and inactive
428 * delay interms of clock counts
429 * @transfer: adds a message to the controller's transfer queue.
430 * @cleanup: frees controller-specific state
431 * @can_dma: determine whether this controller supports DMA
432 * @dma_map_dev: device which can be used for DMA mapping
433 * @cur_rx_dma_dev: device which is currently used for RX DMA mapping
434 * @cur_tx_dma_dev: device which is currently used for TX DMA mapping
435 * @queued: whether this controller is providing an internal message queue
436 * @kworker: pointer to thread struct for message pump
437 * @pump_messages: work struct for scheduling work to the message pump
438 * @queue_lock: spinlock to synchronise access to message queue
439 * @queue: message queue
440 * @cur_msg: the currently in-flight message
441 * @cur_msg_completion: a completion for the current in-flight message
442 * @cur_msg_incomplete: Flag used internally to opportunistically skip
443 * the @cur_msg_completion. This flag is used to check if the driver has
444 * already called spi_finalize_current_message().
445 * @cur_msg_need_completion: Flag used internally to opportunistically skip
446 * the @cur_msg_completion. This flag is used to signal the context that
447 * is running spi_finalize_current_message() that it needs to complete()
448 * @fallback: fallback to PIO if DMA transfer return failure with
449 * SPI_TRANS_FAIL_NO_START.
450 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs.
451 * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip
452 * selected
453 * @last_cs_index_mask: bit mask the last chip selects that were used
454 * @xfer_completion: used by core transfer_one_message()
455 * @busy: message pump is busy
456 * @running: message pump is running
457 * @rt: whether this queue is set to run as a realtime task
458 * @auto_runtime_pm: the core should ensure a runtime PM reference is held
459 * while the hardware is prepared, using the parent
460 * device for the spidev
461 * @max_dma_len: Maximum length of a DMA transfer for the device.
462 * @prepare_transfer_hardware: a message will soon arrive from the queue
463 * so the subsystem requests the driver to prepare the transfer hardware
464 * by issuing this call
465 * @transfer_one_message: the subsystem calls the driver to transfer a single
466 * message while queuing transfers that arrive in the meantime. When the
467 * driver is finished with this message, it must call
468 * spi_finalize_current_message() so the subsystem can issue the next
469 * message
470 * @unprepare_transfer_hardware: there are currently no more messages on the
471 * queue so the subsystem notifies the driver that it may relax the
472 * hardware by issuing this call
473 *
474 * @set_cs: set the logic level of the chip select line. May be called
475 * from interrupt context.
476 * @optimize_message: optimize the message for reuse
477 * @unoptimize_message: release resources allocated by optimize_message
478 * @prepare_message: set up the controller to transfer a single message,
479 * for example doing DMA mapping. Called from threaded
480 * context.
481 * @transfer_one: transfer a single spi_transfer.
482 *
483 * - return 0 if the transfer is finished,
484 * - return 1 if the transfer is still in progress. When
485 * the driver is finished with this transfer it must
486 * call spi_finalize_current_transfer() so the subsystem
487 * can issue the next transfer. If the transfer fails, the
488 * driver must set the flag SPI_TRANS_FAIL_IO to
489 * spi_transfer->error first, before calling
490 * spi_finalize_current_transfer().
491 * Note: transfer_one and transfer_one_message are mutually
492 * exclusive; when both are set, the generic subsystem does
493 * not call your transfer_one callback.
494 * @handle_err: the subsystem calls the driver to handle an error that occurs
495 * in the generic implementation of transfer_one_message().
496 * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
497 * This field is optional and should only be implemented if the
498 * controller has native support for memory like operations.
499 * @mem_caps: controller capabilities for the handling of memory operations.
500 * @unprepare_message: undo any work done by prepare_message().
501 * @slave_abort: abort the ongoing transfer request on an SPI slave controller
502 * @target_abort: abort the ongoing transfer request on an SPI target controller
503 * @cs_gpiods: Array of GPIO descriptors to use as chip select lines; one per CS
504 * number. Any individual value may be NULL for CS lines that
505 * are not GPIOs (driven by the SPI controller itself).
506 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab
507 * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have
508 * the cs_gpiod assigned if a GPIO line is found for the chipselect.
509 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will
510 * fill in this field with the first unused native CS, to be used by SPI
511 * controller drivers that need to drive a native CS when using GPIO CS.
512 * @max_native_cs: When cs_gpiods is used, and this field is filled in,
513 * spi_register_controller() will validate all native CS (including the
514 * unused native CS) against this value.
515 * @pcpu_statistics: statistics for the spi_controller
516 * @dma_tx: DMA transmit channel
517 * @dma_rx: DMA receive channel
518 * @dummy_rx: dummy receive buffer for full-duplex devices
519 * @dummy_tx: dummy transmit buffer for full-duplex devices
520 * @fw_translate_cs: If the boot firmware uses different numbering scheme
521 * what Linux expects, this optional hook can be used to translate
522 * between the two.
523 * @ptp_sts_supported: If the driver sets this to true, it must provide a
524 * time snapshot in @spi_transfer->ptp_sts as close as possible to the
525 * moment in time when @spi_transfer->ptp_sts_word_pre and
526 * @spi_transfer->ptp_sts_word_post were transmitted.
527 * If the driver does not set this, the SPI core takes the snapshot as
528 * close to the driver hand-over as possible.
529 * @irq_flags: Interrupt enable state during PTP system timestamping
530 * @queue_empty: signal green light for opportunistically skipping the queue
531 * for spi_sync transfers.
532 * @must_async: disable all fast paths in the core
533 * @defer_optimize_message: set to true if controller cannot pre-optimize messages
534 * and needs to defer the optimization step until the message is actually
535 * being transferred
536 *
537 * Each SPI controller can communicate with one or more @spi_device
538 * children. These make a small bus, sharing MOSI, MISO and SCK signals
539 * but not chip select signals. Each device may be configured to use a
540 * different clock rate, since those shared signals are ignored unless
541 * the chip is selected.
542 *
543 * The driver for an SPI controller manages access to those devices through
544 * a queue of spi_message transactions, copying data between CPU memory and
545 * an SPI slave device. For each such message it queues, it calls the
546 * message's completion function when the transaction completes.
547 */
548 struct spi_controller {
549 struct device dev;
550
551 struct list_head list;
552
553 /*
554 * Other than negative (== assign one dynamically), bus_num is fully
555 * board-specific. Usually that simplifies to being SoC-specific.
556 * example: one SoC has three SPI controllers, numbered 0..2,
557 * and one board's schematics might show it using SPI-2. Software
558 * would normally use bus_num=2 for that controller.
559 */
560 s16 bus_num;
561
562 /*
563 * Chipselects will be integral to many controllers; some others
564 * might use board-specific GPIOs.
565 */
566 u16 num_chipselect;
567
568 /* Some SPI controllers pose alignment requirements on DMAable
569 * buffers; let protocol drivers know about these requirements.
570 */
571 u16 dma_alignment;
572
573 /* spi_device.mode flags understood by this controller driver */
574 u32 mode_bits;
575
576 /* spi_device.mode flags override flags for this controller */
577 u32 buswidth_override_bits;
578
579 /* Bitmask of supported bits_per_word for transfers */
580 u32 bits_per_word_mask;
581 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
582 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
583
584 /* Limits on transfer speed */
585 u32 min_speed_hz;
586 u32 max_speed_hz;
587
588 /* Other constraints relevant to this driver */
589 u16 flags;
590 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* Can't do full duplex */
591 #define SPI_CONTROLLER_NO_RX BIT(1) /* Can't do buffer read */
592 #define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */
593 #define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */
594 #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */
595 #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select slave */
596 #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently suspended */
597 /*
598 * The spi-controller has multi chip select capability and can
599 * assert/de-assert more than one chip select at once.
600 */
601 #define SPI_CONTROLLER_MULTI_CS BIT(7)
602
603 /* Flag indicating if the allocation of this struct is devres-managed */
604 bool devm_allocated;
605
606 union {
607 /* Flag indicating this is an SPI slave controller */
608 bool slave;
609 /* Flag indicating this is an SPI target controller */
610 bool target;
611 };
612
613 /*
614 * On some hardware transfer / message size may be constrained
615 * the limit may depend on device transfer settings.
616 */
617 size_t (*max_transfer_size)(struct spi_device *spi);
618 size_t (*max_message_size)(struct spi_device *spi);
619
620 /* I/O mutex */
621 struct mutex io_mutex;
622
623 /* Used to avoid adding the same CS twice */
624 struct mutex add_lock;
625
626 /* Lock and mutex for SPI bus locking */
627 spinlock_t bus_lock_spinlock;
628 struct mutex bus_lock_mutex;
629
630 /* Flag indicating that the SPI bus is locked for exclusive use */
631 bool bus_lock_flag;
632
633 /*
634 * Setup mode and clock, etc (SPI driver may call many times).
635 *
636 * IMPORTANT: this may be called when transfers to another
637 * device are active. DO NOT UPDATE SHARED REGISTERS in ways
638 * which could break those transfers.
639 */
640 int (*setup)(struct spi_device *spi);
641
642 /*
643 * set_cs_timing() method is for SPI controllers that supports
644 * configuring CS timing.
645 *
646 * This hook allows SPI client drivers to request SPI controllers
647 * to configure specific CS timing through spi_set_cs_timing() after
648 * spi_setup().
649 */
650 int (*set_cs_timing)(struct spi_device *spi);
651
652 /*
653 * Bidirectional bulk transfers
654 *
655 * + The transfer() method may not sleep; its main role is
656 * just to add the message to the queue.
657 * + For now there's no remove-from-queue operation, or
658 * any other request management
659 * + To a given spi_device, message queueing is pure FIFO
660 *
661 * + The controller's main job is to process its message queue,
662 * selecting a chip (for masters), then transferring data
663 * + If there are multiple spi_device children, the i/o queue
664 * arbitration algorithm is unspecified (round robin, FIFO,
665 * priority, reservations, preemption, etc)
666 *
667 * + Chipselect stays active during the entire message
668 * (unless modified by spi_transfer.cs_change != 0).
669 * + The message transfers use clock and SPI mode parameters
670 * previously established by setup() for this device
671 */
672 int (*transfer)(struct spi_device *spi,
673 struct spi_message *mesg);
674
675 /* Called on release() to free memory provided by spi_controller */
676 void (*cleanup)(struct spi_device *spi);
677
678 /*
679 * Used to enable core support for DMA handling, if can_dma()
680 * exists and returns true then the transfer will be mapped
681 * prior to transfer_one() being called. The driver should
682 * not modify or store xfer and dma_tx and dma_rx must be set
683 * while the device is prepared.
684 */
685 bool (*can_dma)(struct spi_controller *ctlr,
686 struct spi_device *spi,
687 struct spi_transfer *xfer);
688 struct device *dma_map_dev;
689 struct device *cur_rx_dma_dev;
690 struct device *cur_tx_dma_dev;
691
692 /*
693 * These hooks are for drivers that want to use the generic
694 * controller transfer queueing mechanism. If these are used, the
695 * transfer() function above must NOT be specified by the driver.
696 * Over time we expect SPI drivers to be phased over to this API.
697 */
698 bool queued;
699 struct kthread_worker *kworker;
700 struct kthread_work pump_messages;
701 spinlock_t queue_lock;
702 struct list_head queue;
703 struct spi_message *cur_msg;
704 struct completion cur_msg_completion;
705 bool cur_msg_incomplete;
706 bool cur_msg_need_completion;
707 bool busy;
708 bool running;
709 bool rt;
710 bool auto_runtime_pm;
711 bool fallback;
712 bool last_cs_mode_high;
713 s8 last_cs[SPI_CS_CNT_MAX];
714 u32 last_cs_index_mask : SPI_CS_CNT_MAX;
715 struct completion xfer_completion;
716 size_t max_dma_len;
717
718 int (*optimize_message)(struct spi_message *msg);
719 int (*unoptimize_message)(struct spi_message *msg);
720 int (*prepare_transfer_hardware)(struct spi_controller *ctlr);
721 int (*transfer_one_message)(struct spi_controller *ctlr,
722 struct spi_message *mesg);
723 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr);
724 int (*prepare_message)(struct spi_controller *ctlr,
725 struct spi_message *message);
726 int (*unprepare_message)(struct spi_controller *ctlr,
727 struct spi_message *message);
728 union {
729 int (*slave_abort)(struct spi_controller *ctlr);
730 int (*target_abort)(struct spi_controller *ctlr);
731 };
732
733 /*
734 * These hooks are for drivers that use a generic implementation
735 * of transfer_one_message() provided by the core.
736 */
737 void (*set_cs)(struct spi_device *spi, bool enable);
738 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi,
739 struct spi_transfer *transfer);
740 void (*handle_err)(struct spi_controller *ctlr,
741 struct spi_message *message);
742
743 /* Optimized handlers for SPI memory-like operations. */
744 const struct spi_controller_mem_ops *mem_ops;
745 const struct spi_controller_mem_caps *mem_caps;
746
747 /* GPIO chip select */
748 struct gpio_desc **cs_gpiods;
749 bool use_gpio_descriptors;
750 s8 unused_native_cs;
751 s8 max_native_cs;
752
753 /* Statistics */
754 struct spi_statistics __percpu *pcpu_statistics;
755
756 /* DMA channels for use with core dmaengine helpers */
757 struct dma_chan *dma_tx;
758 struct dma_chan *dma_rx;
759
760 /* Dummy data for full duplex devices */
761 void *dummy_rx;
762 void *dummy_tx;
763
764 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
765
766 /*
767 * Driver sets this field to indicate it is able to snapshot SPI
768 * transfers (needed e.g. for reading the time of POSIX clocks)
769 */
770 bool ptp_sts_supported;
771
772 /* Interrupt enable state during PTP system timestamping */
773 unsigned long irq_flags;
774
775 /* Flag for enabling opportunistic skipping of the queue in spi_sync */
776 bool queue_empty;
777 bool must_async;
778 bool defer_optimize_message;
779 };
780
781 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr)
782 {
783 return dev_get_drvdata(&ctlr->dev);
784 }
785
786 static inline void spi_controller_set_devdata(struct spi_controller *ctlr,
787 void *data)
788 {
789 dev_set_drvdata(&ctlr->dev, data);
790 }
791
792 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr)
793 {
794 if (!ctlr || !get_device(&ctlr->dev))
795 return NULL;
796 return ctlr;
797 }
798
799 static inline void spi_controller_put(struct spi_controller *ctlr)
800 {
801 if (ctlr)
802 put_device(&ctlr->dev);
803 }
804
805 static inline bool spi_controller_is_slave(struct spi_controller *ctlr)
806 {
807 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;
808 }
809
810 static inline bool spi_controller_is_target(struct spi_controller *ctlr)
811 {
812 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target;
813 }
814
815 /* PM calls that need to be issued by the driver */
816 extern int spi_controller_suspend(struct spi_controller *ctlr);
817 extern int spi_controller_resume(struct spi_controller *ctlr);
818
819 /* Calls the driver make to interact with the message queue */
820 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr);
821 extern void spi_finalize_current_message(struct spi_controller *ctlr);
822 extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
823
824 /* Helper calls for driver to timestamp transfer */
825 void spi_take_timestamp_pre(struct spi_controller *ctlr,
826 struct spi_transfer *xfer,
827 size_t progress, bool irqs_off);
828 void spi_take_timestamp_post(struct spi_controller *ctlr,
829 struct spi_transfer *xfer,
830 size_t progress, bool irqs_off);
831
832 /* The SPI driver core manages memory for the spi_controller classdev */
833 extern struct spi_controller *__spi_alloc_controller(struct device *host,
834 unsigned int size, bool slave);
835
836 static inline struct spi_controller *spi_alloc_master(struct device *host,
837 unsigned int size)
838 {
839 return __spi_alloc_controller(host, size, false);
840 }
841
842 static inline struct spi_controller *spi_alloc_slave(struct device *host,
843 unsigned int size)
844 {
845 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
846 return NULL;
847
848 return __spi_alloc_controller(host, size, true);
849 }
850
851 static inline struct spi_controller *spi_alloc_host(struct device *dev,
852 unsigned int size)
853 {
854 return __spi_alloc_controller(dev, size, false);
855 }
856
857 static inline struct spi_controller *spi_alloc_target(struct device *dev,
858 unsigned int size)
859 {
860 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
861 return NULL;
862
863 return __spi_alloc_controller(dev, size, true);
864 }
865
866 struct spi_controller *__devm_spi_alloc_controller(struct device *dev,
867 unsigned int size,
868 bool slave);
869
870 static inline struct spi_controller *devm_spi_alloc_master(struct device *dev,
871 unsigned int size)
872 {
873 return __devm_spi_alloc_controller(dev, size, false);
874 }
875
876 static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev,
877 unsigned int size)
878 {
879 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
880 return NULL;
881
882 return __devm_spi_alloc_controller(dev, size, true);
883 }
884
885 static inline struct spi_controller *devm_spi_alloc_host(struct device *dev,
886 unsigned int size)
887 {
888 return __devm_spi_alloc_controller(dev, size, false);
889 }
890
891 static inline struct spi_controller *devm_spi_alloc_target(struct device *dev,
892 unsigned int size)
893 {
894 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
895 return NULL;
896
897 return __devm_spi_alloc_controller(dev, size, true);
898 }
899
900 extern int spi_register_controller(struct spi_controller *ctlr);
901 extern int devm_spi_register_controller(struct device *dev,
902 struct spi_controller *ctlr);
903 extern void spi_unregister_controller(struct spi_controller *ctlr);
904
905 #if IS_ENABLED(CONFIG_ACPI)
906 extern struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev);
907 extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
908 struct acpi_device *adev,
909 int index);
910 int acpi_spi_count_resources(struct acpi_device *adev);
911 #endif
912
913 /*
914 * SPI resource management while processing a SPI message
915 */
916
917 typedef void (*spi_res_release_t)(struct spi_controller *ctlr,
918 struct spi_message *msg,
919 void *res);
920
921 /**
922 * struct spi_res - SPI resource management structure
923 * @entry: list entry
924 * @release: release code called prior to freeing this resource
925 * @data: extra data allocated for the specific use-case
926 *
927 * This is based on ideas from devres, but focused on life-cycle
928 * management during spi_message processing.
929 */
930 struct spi_res {
931 struct list_head entry;
932 spi_res_release_t release;
933 unsigned long long data[]; /* Guarantee ull alignment */
934 };
935
936 /*---------------------------------------------------------------------------*/
937
938 /*
939 * I/O INTERFACE between SPI controller and protocol drivers
940 *
941 * Protocol drivers use a queue of spi_messages, each transferring data
942 * between the controller and memory buffers.
943 *
944 * The spi_messages themselves consist of a series of read+write transfer
945 * segments. Those segments always read the same number of bits as they
946 * write; but one or the other is easily ignored by passing a NULL buffer
947 * pointer. (This is unlike most types of I/O API, because SPI hardware
948 * is full duplex.)
949 *
950 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
951 * up to the protocol driver, which guarantees the integrity of both (as
952 * well as the data buffers) for as long as the message is queued.
953 */
954
955 /**
956 * struct spi_transfer - a read/write buffer pair
957 * @tx_buf: data to be written (DMA-safe memory), or NULL
958 * @rx_buf: data to be read (DMA-safe memory), or NULL
959 * @tx_dma: DMA address of tx_buf, currently not for client use
960 * @rx_dma: DMA address of rx_buf, currently not for client use
961 * @tx_nbits: number of bits used for writing. If 0 the default
962 * (SPI_NBITS_SINGLE) is used.
963 * @rx_nbits: number of bits used for reading. If 0 the default
964 * (SPI_NBITS_SINGLE) is used.
965 * @len: size of rx and tx buffers (in bytes)
966 * @speed_hz: Select a speed other than the device default for this
967 * transfer. If 0 the default (from @spi_device) is used.
968 * @bits_per_word: select a bits_per_word other than the device default
969 * for this transfer. If 0 the default (from @spi_device) is used.
970 * @dummy_data: indicates transfer is dummy bytes transfer.
971 * @cs_off: performs the transfer with chipselect off.
972 * @cs_change: affects chipselect after this transfer completes
973 * @cs_change_delay: delay between cs deassert and assert when
974 * @cs_change is set and @spi_transfer is not the last in @spi_message
975 * @delay: delay to be introduced after this transfer before
976 * (optionally) changing the chipselect status, then starting
977 * the next transfer or completing this @spi_message.
978 * @word_delay: inter word delay to be introduced after each word size
979 * (set by bits_per_word) transmission.
980 * @effective_speed_hz: the effective SCK-speed that was used to
981 * transfer this transfer. Set to 0 if the SPI bus driver does
982 * not support it.
983 * @transfer_list: transfers are sequenced through @spi_message.transfers
984 * @tx_sg_mapped: If true, the @tx_sg is mapped for DMA
985 * @rx_sg_mapped: If true, the @rx_sg is mapped for DMA
986 * @tx_sg: Scatterlist for transmit, currently not for client use
987 * @rx_sg: Scatterlist for receive, currently not for client use
988 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset
989 * within @tx_buf for which the SPI device is requesting that the time
990 * snapshot for this transfer begins. Upon completing the SPI transfer,
991 * this value may have changed compared to what was requested, depending
992 * on the available snapshotting resolution (DMA transfer,
993 * @ptp_sts_supported is false, etc).
994 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning
995 * that a single byte should be snapshotted).
996 * If the core takes care of the timestamp (if @ptp_sts_supported is false
997 * for this controller), it will set @ptp_sts_word_pre to 0, and
998 * @ptp_sts_word_post to the length of the transfer. This is done
999 * purposefully (instead of setting to spi_transfer->len - 1) to denote
1000 * that a transfer-level snapshot taken from within the driver may still
1001 * be of higher quality.
1002 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a
1003 * PTP system timestamp structure may lie. If drivers use PIO or their
1004 * hardware has some sort of assist for retrieving exact transfer timing,
1005 * they can (and should) assert @ptp_sts_supported and populate this
1006 * structure using the ptp_read_system_*ts helper functions.
1007 * The timestamp must represent the time at which the SPI slave device has
1008 * processed the word, i.e. the "pre" timestamp should be taken before
1009 * transmitting the "pre" word, and the "post" timestamp after receiving
1010 * transmit confirmation from the controller for the "post" word.
1011 * @timestamped: true if the transfer has been timestamped
1012 * @error: Error status logged by SPI controller driver.
1013 *
1014 * SPI transfers always write the same number of bytes as they read.
1015 * Protocol drivers should always provide @rx_buf and/or @tx_buf.
1016 * In some cases, they may also want to provide DMA addresses for
1017 * the data being transferred; that may reduce overhead, when the
1018 * underlying driver uses DMA.
1019 *
1020 * If the transmit buffer is NULL, zeroes will be shifted out
1021 * while filling @rx_buf. If the receive buffer is NULL, the data
1022 * shifted in will be discarded. Only "len" bytes shift out (or in).
1023 * It's an error to try to shift out a partial word. (For example, by
1024 * shifting out three bytes with word size of sixteen or twenty bits;
1025 * the former uses two bytes per word, the latter uses four bytes.)
1026 *
1027 * In-memory data values are always in native CPU byte order, translated
1028 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
1029 * for example when bits_per_word is sixteen, buffers are 2N bytes long
1030 * (@len = 2N) and hold N sixteen bit words in CPU byte order.
1031 *
1032 * When the word size of the SPI transfer is not a power-of-two multiple
1033 * of eight bits, those in-memory words include extra bits. In-memory
1034 * words are always seen by protocol drivers as right-justified, so the
1035 * undefined (rx) or unused (tx) bits are always the most significant bits.
1036 *
1037 * All SPI transfers start with the relevant chipselect active. Normally
1038 * it stays selected until after the last transfer in a message. Drivers
1039 * can affect the chipselect signal using cs_change.
1040 *
1041 * (i) If the transfer isn't the last one in the message, this flag is
1042 * used to make the chipselect briefly go inactive in the middle of the
1043 * message. Toggling chipselect in this way may be needed to terminate
1044 * a chip command, letting a single spi_message perform all of group of
1045 * chip transactions together.
1046 *
1047 * (ii) When the transfer is the last one in the message, the chip may
1048 * stay selected until the next transfer. On multi-device SPI busses
1049 * with nothing blocking messages going to other devices, this is just
1050 * a performance hint; starting a message to another device deselects
1051 * this one. But in other cases, this can be used to ensure correctness.
1052 * Some devices need protocol transactions to be built from a series of
1053 * spi_message submissions, where the content of one message is determined
1054 * by the results of previous messages and where the whole transaction
1055 * ends when the chipselect goes inactive.
1056 *
1057 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
1058 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
1059 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
1060 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
1061 *
1062 * The code that submits an spi_message (and its spi_transfers)
1063 * to the lower layers is responsible for managing its memory.
1064 * Zero-initialize every field you don't set up explicitly, to
1065 * insulate against future API updates. After you submit a message
1066 * and its transfers, ignore them until its completion callback.
1067 */
1068 struct spi_transfer {
1069 /*
1070 * It's okay if tx_buf == rx_buf (right?).
1071 * For MicroWire, one buffer must be NULL.
1072 * Buffers must work with dma_*map_single() calls.
1073 */
1074 const void *tx_buf;
1075 void *rx_buf;
1076 unsigned len;
1077
1078 #define SPI_TRANS_FAIL_NO_START BIT(0)
1079 #define SPI_TRANS_FAIL_IO BIT(1)
1080 u16 error;
1081
1082 bool tx_sg_mapped;
1083 bool rx_sg_mapped;
1084
1085 struct sg_table tx_sg;
1086 struct sg_table rx_sg;
1087 dma_addr_t tx_dma;
1088 dma_addr_t rx_dma;
1089
1090 unsigned dummy_data:1;
1091 unsigned cs_off:1;
1092 unsigned cs_change:1;
1093 unsigned tx_nbits:4;
1094 unsigned rx_nbits:4;
1095 unsigned timestamped:1;
1096 #define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */
1097 #define SPI_NBITS_DUAL 0x02 /* 2-bit transfer */
1098 #define SPI_NBITS_QUAD 0x04 /* 4-bit transfer */
1099 #define SPI_NBITS_OCTAL 0x08 /* 8-bit transfer */
1100 u8 bits_per_word;
1101 struct spi_delay delay;
1102 struct spi_delay cs_change_delay;
1103 struct spi_delay word_delay;
1104 u32 speed_hz;
1105
1106 u32 effective_speed_hz;
1107
1108 unsigned int ptp_sts_word_pre;
1109 unsigned int ptp_sts_word_post;
1110
1111 struct ptp_system_timestamp *ptp_sts;
1112
1113 struct list_head transfer_list;
1114 };
1115
1116 /**
1117 * struct spi_message - one multi-segment SPI transaction
1118 * @transfers: list of transfer segments in this transaction
1119 * @spi: SPI device to which the transaction is queued
1120 * @pre_optimized: peripheral driver pre-optimized the message
1121 * @optimized: the message is in the optimized state
1122 * @prepared: spi_prepare_message was called for the this message
1123 * @status: zero for success, else negative errno
1124 * @complete: called to report transaction completions
1125 * @context: the argument to complete() when it's called
1126 * @frame_length: the total number of bytes in the message
1127 * @actual_length: the total number of bytes that were transferred in all
1128 * successful segments
1129 * @queue: for use by whichever driver currently owns the message
1130 * @state: for use by whichever driver currently owns the message
1131 * @opt_state: for use by whichever driver currently owns the message
1132 * @resources: for resource management when the SPI message is processed
1133 *
1134 * A @spi_message is used to execute an atomic sequence of data transfers,
1135 * each represented by a struct spi_transfer. The sequence is "atomic"
1136 * in the sense that no other spi_message may use that SPI bus until that
1137 * sequence completes. On some systems, many such sequences can execute as
1138 * a single programmed DMA transfer. On all systems, these messages are
1139 * queued, and might complete after transactions to other devices. Messages
1140 * sent to a given spi_device are always executed in FIFO order.
1141 *
1142 * The code that submits an spi_message (and its spi_transfers)
1143 * to the lower layers is responsible for managing its memory.
1144 * Zero-initialize every field you don't set up explicitly, to
1145 * insulate against future API updates. After you submit a message
1146 * and its transfers, ignore them until its completion callback.
1147 */
1148 struct spi_message {
1149 struct list_head transfers;
1150
1151 struct spi_device *spi;
1152
1153 /* spi_optimize_message() was called for this message */
1154 bool pre_optimized;
1155 /* __spi_optimize_message() was called for this message */
1156 bool optimized;
1157
1158 /* spi_prepare_message() was called for this message */
1159 bool prepared;
1160
1161 /*
1162 * REVISIT: we might want a flag affecting the behavior of the
1163 * last transfer ... allowing things like "read 16 bit length L"
1164 * immediately followed by "read L bytes". Basically imposing
1165 * a specific message scheduling algorithm.
1166 *
1167 * Some controller drivers (message-at-a-time queue processing)
1168 * could provide that as their default scheduling algorithm. But
1169 * others (with multi-message pipelines) could need a flag to
1170 * tell them about such special cases.
1171 */
1172
1173 /* Completion is reported through a callback */
1174 int status;
1175 void (*complete)(void *context);
1176 void *context;
1177 unsigned frame_length;
1178 unsigned actual_length;
1179
1180 /*
1181 * For optional use by whatever driver currently owns the
1182 * spi_message ... between calls to spi_async and then later
1183 * complete(), that's the spi_controller controller driver.
1184 */
1185 struct list_head queue;
1186 void *state;
1187 /*
1188 * Optional state for use by controller driver between calls to
1189 * __spi_optimize_message() and __spi_unoptimize_message().
1190 */
1191 void *opt_state;
1192
1193 /* List of spi_res resources when the SPI message is processed */
1194 struct list_head resources;
1195 };
1196
1197 static inline void spi_message_init_no_memset(struct spi_message *m)
1198 {
1199 INIT_LIST_HEAD(&m->transfers);
1200 INIT_LIST_HEAD(&m->resources);
1201 }
1202
1203 static inline void spi_message_init(struct spi_message *m)
1204 {
1205 memset(m, 0, sizeof *m);
1206 spi_message_init_no_memset(m);
1207 }
1208
1209 static inline void
1210 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
1211 {
1212 list_add_tail(&t->transfer_list, &m->transfers);
1213 }
1214
1215 static inline void
1216 spi_transfer_del(struct spi_transfer *t)
1217 {
1218 list_del(&t->transfer_list);
1219 }
1220
1221 static inline int
1222 spi_transfer_delay_exec(struct spi_transfer *t)
1223 {
1224 return spi_delay_exec(&t->delay, t);
1225 }
1226
1227 /**
1228 * spi_message_init_with_transfers - Initialize spi_message and append transfers
1229 * @m: spi_message to be initialized
1230 * @xfers: An array of SPI transfers
1231 * @num_xfers: Number of items in the xfer array
1232 *
1233 * This function initializes the given spi_message and adds each spi_transfer in
1234 * the given array to the message.
1235 */
1236 static inline void
1237 spi_message_init_with_transfers(struct spi_message *m,
1238 struct spi_transfer *xfers, unsigned int num_xfers)
1239 {
1240 unsigned int i;
1241
1242 spi_message_init(m);
1243 for (i = 0; i < num_xfers; ++i)
1244 spi_message_add_tail(&xfers[i], m);
1245 }
1246
1247 /*
1248 * It's fine to embed message and transaction structures in other data
1249 * structures so long as you don't free them while they're in use.
1250 */
1251 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
1252 {
1253 struct spi_message_with_transfers {
1254 struct spi_message m;
1255 struct spi_transfer t[];
1256 } *mwt;
1257 unsigned i;
1258
1259 mwt = kzalloc(struct_size(mwt, t, ntrans), flags);
1260 if (!mwt)
1261 return NULL;
1262
1263 spi_message_init_no_memset(&mwt->m);
1264 for (i = 0; i < ntrans; i++)
1265 spi_message_add_tail(&mwt->t[i], &mwt->m);
1266
1267 return &mwt->m;
1268 }
1269
1270 static inline void spi_message_free(struct spi_message *m)
1271 {
1272 kfree(m);
1273 }
1274
1275 extern int spi_optimize_message(struct spi_device *spi, struct spi_message *msg);
1276 extern void spi_unoptimize_message(struct spi_message *msg);
1277 extern int devm_spi_optimize_message(struct device *dev, struct spi_device *spi,
1278 struct spi_message *msg);
1279
1280 extern int spi_setup(struct spi_device *spi);
1281 extern int spi_async(struct spi_device *spi, struct spi_message *message);
1282 extern int spi_slave_abort(struct spi_device *spi);
1283 extern int spi_target_abort(struct spi_device *spi);
1284
1285 static inline size_t
1286 spi_max_message_size(struct spi_device *spi)
1287 {
1288 struct spi_controller *ctlr = spi->controller;
1289
1290 if (!ctlr->max_message_size)
1291 return SIZE_MAX;
1292 return ctlr->max_message_size(spi);
1293 }
1294
1295 static inline size_t
1296 spi_max_transfer_size(struct spi_device *spi)
1297 {
1298 struct spi_controller *ctlr = spi->controller;
1299 size_t tr_max = SIZE_MAX;
1300 size_t msg_max = spi_max_message_size(spi);
1301
1302 if (ctlr->max_transfer_size)
1303 tr_max = ctlr->max_transfer_size(spi);
1304
1305 /* Transfer size limit must not be greater than message size limit */
1306 return min(tr_max, msg_max);
1307 }
1308
1309 /**
1310 * spi_is_bpw_supported - Check if bits per word is supported
1311 * @spi: SPI device
1312 * @bpw: Bits per word
1313 *
1314 * This function checks to see if the SPI controller supports @bpw.
1315 *
1316 * Returns:
1317 * True if @bpw is supported, false otherwise.
1318 */
1319 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
1320 {
1321 u32 bpw_mask = spi->controller->bits_per_word_mask;
1322
1323 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
1324 return true;
1325
1326 return false;
1327 }
1328
1329 /**
1330 * spi_controller_xfer_timeout - Compute a suitable timeout value
1331 * @ctlr: SPI device
1332 * @xfer: Transfer descriptor
1333 *
1334 * Compute a relevant timeout value for the given transfer. We derive the time
1335 * that it would take on a single data line and take twice this amount of time
1336 * with a minimum of 500ms to avoid false positives on loaded systems.
1337 *
1338 * Returns: Transfer timeout value in milliseconds.
1339 */
1340 static inline unsigned int spi_controller_xfer_timeout(struct spi_controller *ctlr,
1341 struct spi_transfer *xfer)
1342 {
1343 return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U);
1344 }
1345
1346 /*---------------------------------------------------------------------------*/
1347
1348 /* SPI transfer replacement methods which make use of spi_res */
1349
1350 struct spi_replaced_transfers;
1351 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr,
1352 struct spi_message *msg,
1353 struct spi_replaced_transfers *res);
1354 /**
1355 * struct spi_replaced_transfers - structure describing the spi_transfer
1356 * replacements that have occurred
1357 * so that they can get reverted
1358 * @release: some extra release code to get executed prior to
1359 * releasing this structure
1360 * @extradata: pointer to some extra data if requested or NULL
1361 * @replaced_transfers: transfers that have been replaced and which need
1362 * to get restored
1363 * @replaced_after: the transfer after which the @replaced_transfers
1364 * are to get re-inserted
1365 * @inserted: number of transfers inserted
1366 * @inserted_transfers: array of spi_transfers of array-size @inserted,
1367 * that have been replacing replaced_transfers
1368 *
1369 * Note: that @extradata will point to @inserted_transfers[@inserted]
1370 * if some extra allocation is requested, so alignment will be the same
1371 * as for spi_transfers.
1372 */
1373 struct spi_replaced_transfers {
1374 spi_replaced_release_t release;
1375 void *extradata;
1376 struct list_head replaced_transfers;
1377 struct list_head *replaced_after;
1378 size_t inserted;
1379 struct spi_transfer inserted_transfers[];
1380 };
1381
1382 /*---------------------------------------------------------------------------*/
1383
1384 /* SPI transfer transformation methods */
1385
1386 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr,
1387 struct spi_message *msg,
1388 size_t maxsize);
1389 extern int spi_split_transfers_maxwords(struct spi_controller *ctlr,
1390 struct spi_message *msg,
1391 size_t maxwords);
1392
1393 /*---------------------------------------------------------------------------*/
1394
1395 /*
1396 * All these synchronous SPI transfer routines are utilities layered
1397 * over the core async transfer primitive. Here, "synchronous" means
1398 * they will sleep uninterruptibly until the async transfer completes.
1399 */
1400
1401 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
1402 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message);
1403 extern int spi_bus_lock(struct spi_controller *ctlr);
1404 extern int spi_bus_unlock(struct spi_controller *ctlr);
1405
1406 /**
1407 * spi_sync_transfer - synchronous SPI data transfer
1408 * @spi: device with which data will be exchanged
1409 * @xfers: An array of spi_transfers
1410 * @num_xfers: Number of items in the xfer array
1411 * Context: can sleep
1412 *
1413 * Does a synchronous SPI data transfer of the given spi_transfer array.
1414 *
1415 * For more specific semantics see spi_sync().
1416 *
1417 * Return: zero on success, else a negative error code.
1418 */
1419 static inline int
1420 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers,
1421 unsigned int num_xfers)
1422 {
1423 struct spi_message msg;
1424
1425 spi_message_init_with_transfers(&msg, xfers, num_xfers);
1426
1427 return spi_sync(spi, &msg);
1428 }
1429
1430 /**
1431 * spi_write - SPI synchronous write
1432 * @spi: device to which data will be written
1433 * @buf: data buffer
1434 * @len: data buffer size
1435 * Context: can sleep
1436 *
1437 * This function writes the buffer @buf.
1438 * Callable only from contexts that can sleep.
1439 *
1440 * Return: zero on success, else a negative error code.
1441 */
1442 static inline int
1443 spi_write(struct spi_device *spi, const void *buf, size_t len)
1444 {
1445 struct spi_transfer t = {
1446 .tx_buf = buf,
1447 .len = len,
1448 };
1449
1450 return spi_sync_transfer(spi, &t, 1);
1451 }
1452
1453 /**
1454 * spi_read - SPI synchronous read
1455 * @spi: device from which data will be read
1456 * @buf: data buffer
1457 * @len: data buffer size
1458 * Context: can sleep
1459 *
1460 * This function reads the buffer @buf.
1461 * Callable only from contexts that can sleep.
1462 *
1463 * Return: zero on success, else a negative error code.
1464 */
1465 static inline int
1466 spi_read(struct spi_device *spi, void *buf, size_t len)
1467 {
1468 struct spi_transfer t = {
1469 .rx_buf = buf,
1470 .len = len,
1471 };
1472
1473 return spi_sync_transfer(spi, &t, 1);
1474 }
1475
1476 /* This copies txbuf and rxbuf data; for small transfers only! */
1477 extern int spi_write_then_read(struct spi_device *spi,
1478 const void *txbuf, unsigned n_tx,
1479 void *rxbuf, unsigned n_rx);
1480
1481 /**
1482 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1483 * @spi: device with which data will be exchanged
1484 * @cmd: command to be written before data is read back
1485 * Context: can sleep
1486 *
1487 * Callable only from contexts that can sleep.
1488 *
1489 * Return: the (unsigned) eight bit number returned by the
1490 * device, or else a negative error code.
1491 */
1492 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
1493 {
1494 ssize_t status;
1495 u8 result;
1496
1497 status = spi_write_then_read(spi, &cmd, 1, &result, 1);
1498
1499 /* Return negative errno or unsigned value */
1500 return (status < 0) ? status : result;
1501 }
1502
1503 /**
1504 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1505 * @spi: device with which data will be exchanged
1506 * @cmd: command to be written before data is read back
1507 * Context: can sleep
1508 *
1509 * The number is returned in wire-order, which is at least sometimes
1510 * big-endian.
1511 *
1512 * Callable only from contexts that can sleep.
1513 *
1514 * Return: the (unsigned) sixteen bit number returned by the
1515 * device, or else a negative error code.
1516 */
1517 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
1518 {
1519 ssize_t status;
1520 u16 result;
1521
1522 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1523
1524 /* Return negative errno or unsigned value */
1525 return (status < 0) ? status : result;
1526 }
1527
1528 /**
1529 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1530 * @spi: device with which data will be exchanged
1531 * @cmd: command to be written before data is read back
1532 * Context: can sleep
1533 *
1534 * This function is similar to spi_w8r16, with the exception that it will
1535 * convert the read 16 bit data word from big-endian to native endianness.
1536 *
1537 * Callable only from contexts that can sleep.
1538 *
1539 * Return: the (unsigned) sixteen bit number returned by the device in CPU
1540 * endianness, or else a negative error code.
1541 */
1542 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd)
1543
1544 {
1545 ssize_t status;
1546 __be16 result;
1547
1548 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1549 if (status < 0)
1550 return status;
1551
1552 return be16_to_cpu(result);
1553 }
1554
1555 /*---------------------------------------------------------------------------*/
1556
1557 /*
1558 * INTERFACE between board init code and SPI infrastructure.
1559 *
1560 * No SPI driver ever sees these SPI device table segments, but
1561 * it's how the SPI core (or adapters that get hotplugged) grows
1562 * the driver model tree.
1563 *
1564 * As a rule, SPI devices can't be probed. Instead, board init code
1565 * provides a table listing the devices which are present, with enough
1566 * information to bind and set up the device's driver. There's basic
1567 * support for non-static configurations too; enough to handle adding
1568 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1569 */
1570
1571 /**
1572 * struct spi_board_info - board-specific template for a SPI device
1573 * @modalias: Initializes spi_device.modalias; identifies the driver.
1574 * @platform_data: Initializes spi_device.platform_data; the particular
1575 * data stored there is driver-specific.
1576 * @swnode: Software node for the device.
1577 * @controller_data: Initializes spi_device.controller_data; some
1578 * controllers need hints about hardware setup, e.g. for DMA.
1579 * @irq: Initializes spi_device.irq; depends on how the board is wired.
1580 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
1581 * from the chip datasheet and board-specific signal quality issues.
1582 * @bus_num: Identifies which spi_controller parents the spi_device; unused
1583 * by spi_new_device(), and otherwise depends on board wiring.
1584 * @chip_select: Initializes spi_device.chip_select; depends on how
1585 * the board is wired.
1586 * @mode: Initializes spi_device.mode; based on the chip datasheet, board
1587 * wiring (some devices support both 3WIRE and standard modes), and
1588 * possibly presence of an inverter in the chipselect path.
1589 *
1590 * When adding new SPI devices to the device tree, these structures serve
1591 * as a partial device template. They hold information which can't always
1592 * be determined by drivers. Information that probe() can establish (such
1593 * as the default transfer wordsize) is not included here.
1594 *
1595 * These structures are used in two places. Their primary role is to
1596 * be stored in tables of board-specific device descriptors, which are
1597 * declared early in board initialization and then used (much later) to
1598 * populate a controller's device tree after the that controller's driver
1599 * initializes. A secondary (and atypical) role is as a parameter to
1600 * spi_new_device() call, which happens after those controller drivers
1601 * are active in some dynamic board configuration models.
1602 */
1603 struct spi_board_info {
1604 /*
1605 * The device name and module name are coupled, like platform_bus;
1606 * "modalias" is normally the driver name.
1607 *
1608 * platform_data goes to spi_device.dev.platform_data,
1609 * controller_data goes to spi_device.controller_data,
1610 * IRQ is copied too.
1611 */
1612 char modalias[SPI_NAME_SIZE];
1613 const void *platform_data;
1614 const struct software_node *swnode;
1615 void *controller_data;
1616 int irq;
1617
1618 /* Slower signaling on noisy or low voltage boards */
1619 u32 max_speed_hz;
1620
1621
1622 /*
1623 * bus_num is board specific and matches the bus_num of some
1624 * spi_controller that will probably be registered later.
1625 *
1626 * chip_select reflects how this chip is wired to that master;
1627 * it's less than num_chipselect.
1628 */
1629 u16 bus_num;
1630 u16 chip_select;
1631
1632 /*
1633 * mode becomes spi_device.mode, and is essential for chips
1634 * where the default of SPI_CS_HIGH = 0 is wrong.
1635 */
1636 u32 mode;
1637
1638 /*
1639 * ... may need additional spi_device chip config data here.
1640 * avoid stuff protocol drivers can set; but include stuff
1641 * needed to behave without being bound to a driver:
1642 * - quirks like clock rate mattering when not selected
1643 */
1644 };
1645
1646 #ifdef CONFIG_SPI
1647 extern int
1648 spi_register_board_info(struct spi_board_info const *info, unsigned n);
1649 #else
1650 /* Board init code may ignore whether SPI is configured or not */
1651 static inline int
1652 spi_register_board_info(struct spi_board_info const *info, unsigned n)
1653 { return 0; }
1654 #endif
1655
1656 /*
1657 * If you're hotplugging an adapter with devices (parport, USB, etc)
1658 * use spi_new_device() to describe each device. You can also call
1659 * spi_unregister_device() to start making that device vanish, but
1660 * normally that would be handled by spi_unregister_controller().
1661 *
1662 * You can also use spi_alloc_device() and spi_add_device() to use a two
1663 * stage registration sequence for each spi_device. This gives the caller
1664 * some more control over the spi_device structure before it is registered,
1665 * but requires that caller to initialize fields that would otherwise
1666 * be defined using the board info.
1667 */
1668 extern struct spi_device *
1669 spi_alloc_device(struct spi_controller *ctlr);
1670
1671 extern int
1672 spi_add_device(struct spi_device *spi);
1673
1674 extern struct spi_device *
1675 spi_new_device(struct spi_controller *, struct spi_board_info *);
1676
1677 extern void spi_unregister_device(struct spi_device *spi);
1678
1679 extern const struct spi_device_id *
1680 spi_get_device_id(const struct spi_device *sdev);
1681
1682 extern const void *
1683 spi_get_device_match_data(const struct spi_device *sdev);
1684
1685 static inline bool
1686 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer)
1687 {
1688 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);
1689 }
1690
1691 #endif /* __LINUX_SPI_H */
1692
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