1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * 10G controller driver for Samsung Exynos SoCs
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
9 */
10 #ifndef __SXGBE_PLATFORM_H__
11 #define __SXGBE_PLATFORM_H__
12
13 #include <linux/phy.h>
14
15 /* MDC Clock Selection define*/
16 #define SXGBE_CSR_100_150M 0x0 /* MDC = clk_scr_i/62 */
17 #define SXGBE_CSR_150_250M 0x1 /* MDC = clk_scr_i/102 */
18 #define SXGBE_CSR_250_300M 0x2 /* MDC = clk_scr_i/122 */
19 #define SXGBE_CSR_300_350M 0x3 /* MDC = clk_scr_i/142 */
20 #define SXGBE_CSR_350_400M 0x4 /* MDC = clk_scr_i/162 */
21 #define SXGBE_CSR_400_500M 0x5 /* MDC = clk_scr_i/202 */
22
23 /* Platfrom data for platform device structure's
24 * platform_data field
25 */
26 struct sxgbe_mdio_bus_data {
27 unsigned int phy_mask;
28 int *irqs;
29 int probed_phy_irq;
30 };
31
32 struct sxgbe_dma_cfg {
33 int pbl;
34 int fixed_burst;
35 int burst_map;
36 int adv_addr_mode;
37 };
38
39 struct sxgbe_plat_data {
40 char *phy_bus_name;
41 int bus_id;
42 int phy_addr;
43 phy_interface_t interface;
44 struct sxgbe_mdio_bus_data *mdio_bus_data;
45 struct sxgbe_dma_cfg *dma_cfg;
46 int clk_csr;
47 int pmt;
48 int force_sf_dma_mode;
49 int force_thresh_dma_mode;
50 int riwt_off;
51 };
52
53 #endif /* __SXGBE_PLATFORM_H__ */
54
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