1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2022-2023 NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #ifndef LINUX_TEGRA_ICC_H
7 #define LINUX_TEGRA_ICC_H
8
9 enum tegra_icc_client_type {
10 TEGRA_ICC_NONE,
11 TEGRA_ICC_NISO,
12 TEGRA_ICC_ISO_DISPLAY,
13 TEGRA_ICC_ISO_VI,
14 TEGRA_ICC_ISO_AUDIO,
15 TEGRA_ICC_ISO_VIFAL,
16 };
17
18 /* ICC ID's for MC client's used in BPMP */
19 #define TEGRA_ICC_BPMP_DEBUG 1
20 #define TEGRA_ICC_BPMP_CPU_CLUSTER0 2
21 #define TEGRA_ICC_BPMP_CPU_CLUSTER1 3
22 #define TEGRA_ICC_BPMP_CPU_CLUSTER2 4
23 #define TEGRA_ICC_BPMP_GPU 5
24 #define TEGRA_ICC_BPMP_CACTMON 6
25 #define TEGRA_ICC_BPMP_DISPLAY 7
26 #define TEGRA_ICC_BPMP_VI 8
27 #define TEGRA_ICC_BPMP_EQOS 9
28 #define TEGRA_ICC_BPMP_PCIE_0 10
29 #define TEGRA_ICC_BPMP_PCIE_1 11
30 #define TEGRA_ICC_BPMP_PCIE_2 12
31 #define TEGRA_ICC_BPMP_PCIE_3 13
32 #define TEGRA_ICC_BPMP_PCIE_4 14
33 #define TEGRA_ICC_BPMP_PCIE_5 15
34 #define TEGRA_ICC_BPMP_PCIE_6 16
35 #define TEGRA_ICC_BPMP_PCIE_7 17
36 #define TEGRA_ICC_BPMP_PCIE_8 18
37 #define TEGRA_ICC_BPMP_PCIE_9 19
38 #define TEGRA_ICC_BPMP_PCIE_10 20
39 #define TEGRA_ICC_BPMP_DLA_0 21
40 #define TEGRA_ICC_BPMP_DLA_1 22
41 #define TEGRA_ICC_BPMP_SDMMC_1 23
42 #define TEGRA_ICC_BPMP_SDMMC_2 24
43 #define TEGRA_ICC_BPMP_SDMMC_3 25
44 #define TEGRA_ICC_BPMP_SDMMC_4 26
45 #define TEGRA_ICC_BPMP_NVDEC 27
46 #define TEGRA_ICC_BPMP_NVENC 28
47 #define TEGRA_ICC_BPMP_NVJPG_0 29
48 #define TEGRA_ICC_BPMP_NVJPG_1 30
49 #define TEGRA_ICC_BPMP_OFAA 31
50 #define TEGRA_ICC_BPMP_XUSB_HOST 32
51 #define TEGRA_ICC_BPMP_XUSB_DEV 33
52 #define TEGRA_ICC_BPMP_TSEC 34
53 #define TEGRA_ICC_BPMP_VIC 35
54 #define TEGRA_ICC_BPMP_APE 36
55 #define TEGRA_ICC_BPMP_APEDMA 37
56 #define TEGRA_ICC_BPMP_SE 38
57 #define TEGRA_ICC_BPMP_ISP 39
58 #define TEGRA_ICC_BPMP_HDA 40
59 #define TEGRA_ICC_BPMP_VIFAL 41
60 #define TEGRA_ICC_BPMP_VI2FAL 42
61 #define TEGRA_ICC_BPMP_VI2 43
62 #define TEGRA_ICC_BPMP_RCE 44
63 #define TEGRA_ICC_BPMP_PVA 45
64
65 #endif /* LINUX_TEGRA_ICC_H */
66
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