1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A66597 driver platform data
4 *
5 * Copyright (C) 2009 Renesas Solutions Corp.
6 *
7 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
8 */
9
10 #ifndef __LINUX_USB_R8A66597_H
11 #define __LINUX_USB_R8A66597_H
12
13 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
14 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
15 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
16
17 struct r8a66597_platdata {
18 /* This callback can control port power instead of DVSTCTR register. */
19 void (*port_power)(int port, int power);
20
21 /* This parameter is for BUSWAIT */
22 u16 buswait;
23
24 /* set one = on chip controller, set zero = external controller */
25 unsigned on_chip:1;
26
27 /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
28 unsigned xtal:2;
29
30 /* set one = 3.3V, set zero = 1.5V */
31 unsigned vif:1;
32
33 /* set one = big endian, set zero = little endian */
34 unsigned endian:1;
35
36 /* (external controller only) set one = WR0_N shorted to WR1_N */
37 unsigned wr0_shorted_to_wr1:1;
38
39 /* set one = using SUDMAC */
40 unsigned sudmac:1;
41 };
42
43 /* Register definitions */
44 #define SYSCFG0 0x00
45 #define SYSCFG1 0x02
46 #define SYSSTS0 0x04
47 #define SYSSTS1 0x06
48 #define DVSTCTR0 0x08
49 #define DVSTCTR1 0x0A
50 #define TESTMODE 0x0C
51 #define PINCFG 0x0E
52 #define DMA0CFG 0x10
53 #define DMA1CFG 0x12
54 #define CFIFO 0x14
55 #define D0FIFO 0x18
56 #define D1FIFO 0x1C
57 #define CFIFOSEL 0x20
58 #define CFIFOCTR 0x22
59 #define CFIFOSIE 0x24
60 #define D0FIFOSEL 0x28
61 #define D0FIFOCTR 0x2A
62 #define D1FIFOSEL 0x2C
63 #define D1FIFOCTR 0x2E
64 #define INTENB0 0x30
65 #define INTENB1 0x32
66 #define INTENB2 0x34
67 #define BRDYENB 0x36
68 #define NRDYENB 0x38
69 #define BEMPENB 0x3A
70 #define SOFCFG 0x3C
71 #define INTSTS0 0x40
72 #define INTSTS1 0x42
73 #define INTSTS2 0x44
74 #define BRDYSTS 0x46
75 #define NRDYSTS 0x48
76 #define BEMPSTS 0x4A
77 #define FRMNUM 0x4C
78 #define UFRMNUM 0x4E
79 #define USBADDR 0x50
80 #define USBREQ 0x54
81 #define USBVAL 0x56
82 #define USBINDX 0x58
83 #define USBLENG 0x5A
84 #define DCPCFG 0x5C
85 #define DCPMAXP 0x5E
86 #define DCPCTR 0x60
87 #define PIPESEL 0x64
88 #define PIPECFG 0x68
89 #define PIPEBUF 0x6A
90 #define PIPEMAXP 0x6C
91 #define PIPEPERI 0x6E
92 #define PIPE1CTR 0x70
93 #define PIPE2CTR 0x72
94 #define PIPE3CTR 0x74
95 #define PIPE4CTR 0x76
96 #define PIPE5CTR 0x78
97 #define PIPE6CTR 0x7A
98 #define PIPE7CTR 0x7C
99 #define PIPE8CTR 0x7E
100 #define PIPE9CTR 0x80
101 #define PIPE1TRE 0x90
102 #define PIPE1TRN 0x92
103 #define PIPE2TRE 0x94
104 #define PIPE2TRN 0x96
105 #define PIPE3TRE 0x98
106 #define PIPE3TRN 0x9A
107 #define PIPE4TRE 0x9C
108 #define PIPE4TRN 0x9E
109 #define PIPE5TRE 0xA0
110 #define PIPE5TRN 0xA2
111 #define DEVADD0 0xD0
112 #define DEVADD1 0xD2
113 #define DEVADD2 0xD4
114 #define DEVADD3 0xD6
115 #define DEVADD4 0xD8
116 #define DEVADD5 0xDA
117 #define DEVADD6 0xDC
118 #define DEVADD7 0xDE
119 #define DEVADD8 0xE0
120 #define DEVADD9 0xE2
121 #define DEVADDA 0xE4
122
123 /* System Configuration Control Register */
124 #define XTAL 0xC000 /* b15-14: Crystal selection */
125 #define XTAL48 0x8000 /* 48MHz */
126 #define XTAL24 0x4000 /* 24MHz */
127 #define XTAL12 0x0000 /* 12MHz */
128 #define XCKE 0x2000 /* b13: External clock enable */
129 #define PLLC 0x0800 /* b11: PLL control */
130 #define SCKE 0x0400 /* b10: USB clock enable */
131 #define PCSDIS 0x0200 /* b9: not CS wakeup */
132 #define LPSME 0x0100 /* b8: Low power sleep mode */
133 #define HSE 0x0080 /* b7: Hi-speed enable */
134 #define DCFM 0x0040 /* b6: Controller function select */
135 #define DRPD 0x0020 /* b5: D+/- pull down control */
136 #define DPRPU 0x0010 /* b4: D+ pull up control */
137 #define USBE 0x0001 /* b0: USB module operation enable */
138
139 /* System Configuration Status Register */
140 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
141 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
142 #define SOFEA 0x0020 /* b5: SOF monitor */
143 #define IDMON 0x0004 /* b3: ID-pin monitor */
144 #define LNST 0x0003 /* b1-0: D+, D- line status */
145 #define SE1 0x0003 /* SE1 */
146 #define FS_KSTS 0x0002 /* Full-Speed K State */
147 #define FS_JSTS 0x0001 /* Full-Speed J State */
148 #define LS_JSTS 0x0002 /* Low-Speed J State */
149 #define LS_KSTS 0x0001 /* Low-Speed K State */
150 #define SE0 0x0000 /* SE0 */
151
152 /* Device State Control Register */
153 #define EXTLP0 0x0400 /* b10: External port */
154 #define VBOUT 0x0200 /* b9: VBUS output */
155 #define WKUP 0x0100 /* b8: Remote wakeup */
156 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
157 #define USBRST 0x0040 /* b6: USB reset enable */
158 #define RESUME 0x0020 /* b5: Resume enable */
159 #define UACT 0x0010 /* b4: USB bus enable */
160 #define RHST 0x0007 /* b1-0: Reset handshake status */
161 #define HSPROC 0x0004 /* HS handshake is processing */
162 #define HSMODE 0x0003 /* Hi-Speed mode */
163 #define FSMODE 0x0002 /* Full-Speed mode */
164 #define LSMODE 0x0001 /* Low-Speed mode */
165 #define UNDECID 0x0000 /* Undecided */
166
167 /* Test Mode Register */
168 #define UTST 0x000F /* b3-0: Test select */
169 #define H_TST_PACKET 0x000C /* HOST TEST Packet */
170 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
171 #define H_TST_K 0x000A /* HOST TEST K */
172 #define H_TST_J 0x0009 /* HOST TEST J */
173 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
174 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
175 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
176 #define P_TST_K 0x0002 /* PERI TEST K */
177 #define P_TST_J 0x0001 /* PERI TEST J */
178 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
179
180 /* Data Pin Configuration Register */
181 #define LDRV 0x8000 /* b15: Drive Current Adjust */
182 #define VIF1 0x0000 /* VIF = 1.8V */
183 #define VIF3 0x8000 /* VIF = 3.3V */
184 #define INTA 0x0001 /* b1: USB INT-pin active */
185
186 /* DMAx Pin Configuration Register */
187 #define DREQA 0x4000 /* b14: Dreq active select */
188 #define BURST 0x2000 /* b13: Burst mode */
189 #define DACKA 0x0400 /* b10: Dack active select */
190 #define DFORM 0x0380 /* b9-7: DMA mode select */
191 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
192 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
193 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
194 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
195 #define DENDA 0x0040 /* b6: Dend active select */
196 #define PKTM 0x0020 /* b5: Packet mode */
197 #define DENDE 0x0010 /* b4: Dend enable */
198 #define OBUS 0x0004 /* b2: OUTbus mode */
199
200 /* CFIFO/DxFIFO Port Select Register */
201 #define RCNT 0x8000 /* b15: Read count mode */
202 #define REW 0x4000 /* b14: Buffer rewind */
203 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
204 #define DREQE 0x1000 /* b12: DREQ output enable */
205 #define MBW_8 0x0000 /* 8bit */
206 #define MBW_16 0x0400 /* 16bit */
207 #define MBW_32 0x0800 /* 32bit */
208 #define BIGEND 0x0100 /* b8: Big endian mode */
209 #define BYTE_LITTLE 0x0000 /* little dendian */
210 #define BYTE_BIG 0x0100 /* big endifan */
211 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
212 #define CURPIPE 0x000F /* b2-0: PIPE select */
213
214 /* CFIFO/DxFIFO Port Control Register */
215 #define BVAL 0x8000 /* b15: Buffer valid flag */
216 #define BCLR 0x4000 /* b14: Buffer clear */
217 #define FRDY 0x2000 /* b13: FIFO ready */
218 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
219
220 /* Interrupt Enable Register 0 */
221 #define VBSE 0x8000 /* b15: VBUS interrupt */
222 #define RSME 0x4000 /* b14: Resume interrupt */
223 #define SOFE 0x2000 /* b13: Frame update interrupt */
224 #define DVSE 0x1000 /* b12: Device state transition interrupt */
225 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
226 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
227 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
228 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
229
230 /* Interrupt Enable Register 1 */
231 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
232 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
233 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
234 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
235 #define EOFERRE 0x0040 /* b6: EOF error interrupt */
236 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
237 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
238
239 /* BRDY Interrupt Enable/Status Register */
240 #define BRDY9 0x0200 /* b9: PIPE9 */
241 #define BRDY8 0x0100 /* b8: PIPE8 */
242 #define BRDY7 0x0080 /* b7: PIPE7 */
243 #define BRDY6 0x0040 /* b6: PIPE6 */
244 #define BRDY5 0x0020 /* b5: PIPE5 */
245 #define BRDY4 0x0010 /* b4: PIPE4 */
246 #define BRDY3 0x0008 /* b3: PIPE3 */
247 #define BRDY2 0x0004 /* b2: PIPE2 */
248 #define BRDY1 0x0002 /* b1: PIPE1 */
249 #define BRDY0 0x0001 /* b1: PIPE0 */
250
251 /* NRDY Interrupt Enable/Status Register */
252 #define NRDY9 0x0200 /* b9: PIPE9 */
253 #define NRDY8 0x0100 /* b8: PIPE8 */
254 #define NRDY7 0x0080 /* b7: PIPE7 */
255 #define NRDY6 0x0040 /* b6: PIPE6 */
256 #define NRDY5 0x0020 /* b5: PIPE5 */
257 #define NRDY4 0x0010 /* b4: PIPE4 */
258 #define NRDY3 0x0008 /* b3: PIPE3 */
259 #define NRDY2 0x0004 /* b2: PIPE2 */
260 #define NRDY1 0x0002 /* b1: PIPE1 */
261 #define NRDY0 0x0001 /* b1: PIPE0 */
262
263 /* BEMP Interrupt Enable/Status Register */
264 #define BEMP9 0x0200 /* b9: PIPE9 */
265 #define BEMP8 0x0100 /* b8: PIPE8 */
266 #define BEMP7 0x0080 /* b7: PIPE7 */
267 #define BEMP6 0x0040 /* b6: PIPE6 */
268 #define BEMP5 0x0020 /* b5: PIPE5 */
269 #define BEMP4 0x0010 /* b4: PIPE4 */
270 #define BEMP3 0x0008 /* b3: PIPE3 */
271 #define BEMP2 0x0004 /* b2: PIPE2 */
272 #define BEMP1 0x0002 /* b1: PIPE1 */
273 #define BEMP0 0x0001 /* b0: PIPE0 */
274
275 /* SOF Pin Configuration Register */
276 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
277 #define BRDYM 0x0040 /* b6: BRDY clear timing */
278 #define INTL 0x0020 /* b5: Interrupt sense select */
279 #define EDGESTS 0x0010 /* b4: */
280 #define SOFMODE 0x000C /* b3-2: SOF pin select */
281 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
282 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
283 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
284
285 /* Interrupt Status Register 0 */
286 #define VBINT 0x8000 /* b15: VBUS interrupt */
287 #define RESM 0x4000 /* b14: Resume interrupt */
288 #define SOFR 0x2000 /* b13: SOF frame update interrupt */
289 #define DVST 0x1000 /* b12: Device state transition interrupt */
290 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
291 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
292 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
293 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
294 #define VBSTS 0x0080 /* b7: VBUS input port */
295 #define DVSQ 0x0070 /* b6-4: Device state */
296 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
297 #define DS_SPD_ADDR 0x0060 /* Suspend Address */
298 #define DS_SPD_DFLT 0x0050 /* Suspend Default */
299 #define DS_SPD_POWR 0x0040 /* Suspend Powered */
300 #define DS_SUSP 0x0040 /* Suspend */
301 #define DS_CNFG 0x0030 /* Configured */
302 #define DS_ADDS 0x0020 /* Address */
303 #define DS_DFLT 0x0010 /* Default */
304 #define DS_POWR 0x0000 /* Powered */
305 #define DVSQS 0x0030 /* b5-4: Device state */
306 #define VALID 0x0008 /* b3: Setup packet detected flag */
307 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
308 #define CS_SQER 0x0006 /* Sequence error */
309 #define CS_WRND 0x0005 /* Control write nodata status stage */
310 #define CS_WRSS 0x0004 /* Control write status stage */
311 #define CS_WRDS 0x0003 /* Control write data stage */
312 #define CS_RDSS 0x0002 /* Control read status stage */
313 #define CS_RDDS 0x0001 /* Control read data stage */
314 #define CS_IDST 0x0000 /* Idle or setup stage */
315
316 /* Interrupt Status Register 1 */
317 #define OVRCR 0x8000 /* b15: Over-current interrupt */
318 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
319 #define DTCH 0x1000 /* b12: Detach sense interrupt */
320 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
321 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
322 #define SIGN 0x0020 /* b5: Setup ignore interrupt */
323 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
324
325 /* Frame Number Register */
326 #define OVRN 0x8000 /* b15: Overrun error */
327 #define CRCE 0x4000 /* b14: Received data error */
328 #define FRNM 0x07FF /* b10-0: Frame number */
329
330 /* Micro Frame Number Register */
331 #define UFRNM 0x0007 /* b2-0: Micro frame number */
332
333 /* Default Control Pipe Maxpacket Size Register */
334 /* Pipe Maxpacket Size Register */
335 #define DEVSEL 0xF000 /* b15-14: Device address select */
336 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
337
338 /* Default Control Pipe Control Register */
339 #define BSTS 0x8000 /* b15: Buffer status */
340 #define SUREQ 0x4000 /* b14: Send USB request */
341 #define CSCLR 0x2000 /* b13: complete-split status clear */
342 #define CSSTS 0x1000 /* b12: complete-split status */
343 #define SUREQCLR 0x0800 /* b11: stop setup request */
344 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
345 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
346 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
347 #define PBUSY 0x0020 /* b5: pipe busy */
348 #define PINGE 0x0010 /* b4: ping enable */
349 #define CCPL 0x0004 /* b2: Enable control transfer complete */
350 #define PID 0x0003 /* b1-0: Response PID */
351 #define PID_STALL11 0x0003 /* STALL */
352 #define PID_STALL 0x0002 /* STALL */
353 #define PID_BUF 0x0001 /* BUF */
354 #define PID_NAK 0x0000 /* NAK */
355
356 /* Pipe Window Select Register */
357 #define PIPENM 0x0007 /* b2-0: Pipe select */
358
359 /* Pipe Configuration Register */
360 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
361 #define R8A66597_ISO 0xC000 /* Isochronous */
362 #define R8A66597_INT 0x8000 /* Interrupt */
363 #define R8A66597_BULK 0x4000 /* Bulk */
364 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
365 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
366 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
367 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
368 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
369 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
370
371 /* Pipe Buffer Configuration Register */
372 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
373 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
374 #define PIPE0BUF 256
375 #define PIPExBUF 64
376
377 /* Pipe Maxpacket Size Register */
378 #define MXPS 0x07FF /* b10-0: Maxpacket size */
379
380 /* Pipe Cycle Configuration Register */
381 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
382 #define IITV 0x0007 /* b2-0: Isochronous interval */
383
384 /* Pipex Control Register */
385 #define BSTS 0x8000 /* b15: Buffer status */
386 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
387 #define CSCLR 0x2000 /* b13: complete-split status clear */
388 #define CSSTS 0x1000 /* b12: complete-split status */
389 #define ATREPM 0x0400 /* b10: Auto repeat mode */
390 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
391 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
392 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
393 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
394 #define PBUSY 0x0020 /* b5: pipe busy */
395 #define PID 0x0003 /* b1-0: Response PID */
396
397 /* PIPExTRE */
398 #define TRENB 0x0200 /* b9: Transaction counter enable */
399 #define TRCLR 0x0100 /* b8: Transaction counter clear */
400
401 /* PIPExTRN */
402 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
403
404 /* DEVADDx */
405 #define UPPHUB 0x7800
406 #define HUBPORT 0x0700
407 #define USBSPD 0x00C0
408 #define RTPORT 0x0001
409
410 /* SUDMAC registers */
411 #define CH0CFG 0x00
412 #define CH1CFG 0x04
413 #define CH0BA 0x10
414 #define CH1BA 0x14
415 #define CH0BBC 0x18
416 #define CH1BBC 0x1C
417 #define CH0CA 0x20
418 #define CH1CA 0x24
419 #define CH0CBC 0x28
420 #define CH1CBC 0x2C
421 #define CH0DEN 0x30
422 #define CH1DEN 0x34
423 #define DSTSCLR 0x38
424 #define DBUFCTRL 0x3C
425 #define DINTCTRL 0x40
426 #define DINTSTS 0x44
427 #define DINTSTSCLR 0x48
428 #define CH0SHCTRL 0x50
429 #define CH1SHCTRL 0x54
430
431 /* SUDMAC Configuration Registers */
432 #define SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
433 #define RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */
434 #define LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
435
436 /* DMA Enable Registers */
437 #define DEN 0x0001 /* b1: DMA Transfer Enable */
438
439 /* DMA Status Clear Register */
440 #define CH1STCLR 0x0002 /* b2: Ch1 DMA Status Clear */
441 #define CH0STCLR 0x0001 /* b1: Ch0 DMA Status Clear */
442
443 /* DMA Buffer Control Register */
444 #define CH1BUFW 0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */
445 #define CH0BUFW 0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */
446 #define CH1BUFS 0x0002 /* b2: Ch1 DMA Buffer Data Status */
447 #define CH0BUFS 0x0001 /* b1: Ch0 DMA Buffer Data Status */
448
449 /* DMA Interrupt Control Register */
450 #define CH1ERRE 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */
451 #define CH0ERRE 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */
452 #define CH1ENDE 0x0002 /* b2: Ch1 DMA Transfer End Int Enable */
453 #define CH0ENDE 0x0001 /* b1: Ch0 DMA Transfer End Int Enable */
454
455 /* DMA Interrupt Status Register */
456 #define CH1ERRS 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Status */
457 #define CH0ERRS 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Status */
458 #define CH1ENDS 0x0002 /* b2: Ch1 DMA Transfer End Int Status */
459 #define CH0ENDS 0x0001 /* b1: Ch0 DMA Transfer End Int Status */
460
461 /* DMA Interrupt Status Clear Register */
462 #define CH1ERRC 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Stat Clear */
463 #define CH0ERRC 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Stat Clear */
464 #define CH1ENDC 0x0002 /* b2: Ch1 DMA Transfer End Int Stat Clear */
465 #define CH0ENDC 0x0001 /* b1: Ch0 DMA Transfer End Int Stat Clear */
466
467 #endif /* __LINUX_USB_R8A66597_H */
468
469
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