1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * adv7604 - Analog Devices ADV7604 video decoder driver
4 *
5 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 */
7
8 #ifndef _ADV7604_
9 #define _ADV7604_
10
11 #include <linux/types.h>
12
13 /* Analog input muxing modes (AFE register 0x02, [2:0]) */
14 enum adv7604_ain_sel {
15 ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
16 ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
17 ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
18 ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
19 ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
20 };
21
22 /*
23 * Bus rotation and reordering. This is used to specify component reordering on
24 * the board and describes the components order on the bus when the ADV7604
25 * outputs RGB.
26 */
27 enum adv7604_bus_order {
28 ADV7604_BUS_ORDER_RGB, /* No operation */
29 ADV7604_BUS_ORDER_GRB, /* Swap 1-2 */
30 ADV7604_BUS_ORDER_RBG, /* Swap 2-3 */
31 ADV7604_BUS_ORDER_BGR, /* Swap 1-3 */
32 ADV7604_BUS_ORDER_BRG, /* Rotate right */
33 ADV7604_BUS_ORDER_GBR, /* Rotate left */
34 };
35
36 /* Input Color Space (IO register 0x02, [7:4]) */
37 enum adv76xx_inp_color_space {
38 ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0,
39 ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1,
40 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
41 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
42 ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4,
43 ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5,
44 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
45 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
46 ADV76XX_INP_COLOR_SPACE_AUTO = 0xf,
47 };
48
49 /* Select output format (IO register 0x03, [4:2]) */
50 enum adv7604_op_format_mode_sel {
51 ADV7604_OP_FORMAT_MODE0 = 0x00,
52 ADV7604_OP_FORMAT_MODE1 = 0x04,
53 ADV7604_OP_FORMAT_MODE2 = 0x08,
54 };
55
56 enum adv76xx_drive_strength {
57 ADV76XX_DR_STR_MEDIUM_LOW = 1,
58 ADV76XX_DR_STR_MEDIUM_HIGH = 2,
59 ADV76XX_DR_STR_HIGH = 3,
60 };
61
62 /* INT1 Configuration (IO register 0x40, [1:0]) */
63 enum adv76xx_int1_config {
64 ADV76XX_INT1_CONFIG_OPEN_DRAIN,
65 ADV76XX_INT1_CONFIG_ACTIVE_LOW,
66 ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
67 ADV76XX_INT1_CONFIG_DISABLED,
68 };
69
70 enum adv76xx_page {
71 ADV76XX_PAGE_IO,
72 ADV7604_PAGE_AVLINK,
73 ADV76XX_PAGE_CEC,
74 ADV76XX_PAGE_INFOFRAME,
75 ADV7604_PAGE_ESDP,
76 ADV7604_PAGE_DPP,
77 ADV76XX_PAGE_AFE,
78 ADV76XX_PAGE_REP,
79 ADV76XX_PAGE_EDID,
80 ADV76XX_PAGE_HDMI,
81 ADV76XX_PAGE_TEST,
82 ADV76XX_PAGE_CP,
83 ADV7604_PAGE_VDP,
84 ADV76XX_PAGE_MAX,
85 };
86
87 /* Platform dependent definition */
88 struct adv76xx_platform_data {
89 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
90 unsigned disable_pwrdnb:1;
91
92 /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
93 unsigned disable_cable_det_rst:1;
94
95 int default_input;
96
97 /* Analog input muxing mode */
98 enum adv7604_ain_sel ain_sel;
99
100 /* Bus rotation and reordering */
101 enum adv7604_bus_order bus_order;
102
103 /* Select output format mode */
104 enum adv7604_op_format_mode_sel op_format_mode_sel;
105
106 /* Configuration of the INT1 pin */
107 enum adv76xx_int1_config int1_config;
108
109 /* IO register 0x02 */
110 unsigned alt_gamma:1;
111
112 /* IO register 0x05 */
113 unsigned blank_data:1;
114 unsigned insert_av_codes:1;
115 unsigned replicate_av_codes:1;
116
117 /* IO register 0x06 */
118 unsigned inv_vs_pol:1;
119 unsigned inv_hs_pol:1;
120 unsigned inv_llc_pol:1;
121
122 /* IO register 0x14 */
123 enum adv76xx_drive_strength dr_str_data;
124 enum adv76xx_drive_strength dr_str_clk;
125 enum adv76xx_drive_strength dr_str_sync;
126
127 /* IO register 0x30 */
128 unsigned output_bus_lsb_to_msb:1;
129
130 /* Free run */
131 unsigned hdmi_free_run_mode;
132
133 /* i2c addresses: 0 == use default */
134 u8 i2c_addresses[ADV76XX_PAGE_MAX];
135 };
136
137 enum adv76xx_pad {
138 ADV76XX_PAD_HDMI_PORT_A = 0,
139 ADV7604_PAD_HDMI_PORT_B = 1,
140 ADV7604_PAD_HDMI_PORT_C = 2,
141 ADV7604_PAD_HDMI_PORT_D = 3,
142 ADV7604_PAD_VGA_RGB = 4,
143 ADV7604_PAD_VGA_COMP = 5,
144 /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
145 ADV7604_PAD_SOURCE = 6,
146 ADV7611_PAD_SOURCE = 1,
147 ADV76XX_PAD_MAX = 7,
148 };
149
150 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
151 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
152 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
153
154 /* notify events */
155 #define ADV76XX_HOTPLUG 1
156
157 #endif
158
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