1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /*
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
4 */
5
6 #ifndef OPA_PORT_INFO_H
7 #define OPA_PORT_INFO_H
8
9 #include <rdma/opa_smi.h>
10
11 #define OPA_PORT_LINK_MODE_NOP 0 /* No change */
12 #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
13
14 #define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */
15 #define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */
16 #define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
18 #define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */
19
20 #define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
25
26 /* Link Down / Neighbor Link Down Reason; indicated as follows: */
27 #define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */
28 #define OPA_LINKDOWN_REASON_RCV_ERROR_0 1
29 #define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2
30 #define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3
31 #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
32 #define OPA_LINKDOWN_REASON_BAD_SLID 5
33 #define OPA_LINKDOWN_REASON_BAD_DLID 6
34 #define OPA_LINKDOWN_REASON_BAD_L2 7
35 #define OPA_LINKDOWN_REASON_BAD_SC 8
36 #define OPA_LINKDOWN_REASON_RCV_ERROR_8 9
37 #define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10
38 #define OPA_LINKDOWN_REASON_RCV_ERROR_10 11
39 #define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12
40 #define OPA_LINKDOWN_REASON_PREEMPT_VL15 13
41 #define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14
42 #define OPA_LINKDOWN_REASON_RCV_ERROR_14 15
43 #define OPA_LINKDOWN_REASON_RCV_ERROR_15 16
44 #define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17
45 #define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18
46 #define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19
47 #define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20
48 #define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21
49 #define OPA_LINKDOWN_REASON_BAD_PREEMPT 22
50 #define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23
51 #define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24
52 #define OPA_LINKDOWN_REASON_RCV_ERROR_24 25
53 #define OPA_LINKDOWN_REASON_RCV_ERROR_25 26
54 #define OPA_LINKDOWN_REASON_RCV_ERROR_26 27
55 #define OPA_LINKDOWN_REASON_RCV_ERROR_27 28
56 #define OPA_LINKDOWN_REASON_RCV_ERROR_28 29
57 #define OPA_LINKDOWN_REASON_RCV_ERROR_29 30
58 #define OPA_LINKDOWN_REASON_RCV_ERROR_30 31
59 #define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32
60 #define OPA_LINKDOWN_REASON_UNKNOWN 33
61 /* 34 -reserved */
62 #define OPA_LINKDOWN_REASON_REBOOT 35
63 #define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36
64 /* 37-38 reserved */
65 #define OPA_LINKDOWN_REASON_FM_BOUNCE 39
66 #define OPA_LINKDOWN_REASON_SPEED_POLICY 40
67 #define OPA_LINKDOWN_REASON_WIDTH_POLICY 41
68 /* 42-48 reserved */
69 #define OPA_LINKDOWN_REASON_DISCONNECTED 49
70 #define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED 50
71 #define OPA_LINKDOWN_REASON_NOT_INSTALLED 51
72 #define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52
73 /* 53 reserved */
74 #define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54
75 /* 55 reserved */
76 #define OPA_LINKDOWN_REASON_POWER_POLICY 56
77 #define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57
78 #define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58
79 /* 59 reserved */
80 #define OPA_LINKDOWN_REASON_SWITCH_MGMT 60
81 #define OPA_LINKDOWN_REASON_SMA_DISABLED 61
82 /* 62 reserved */
83 #define OPA_LINKDOWN_REASON_TRANSIENT 63
84 /* 64-255 reserved */
85
86 /* OPA Link Init reason; indicated as follows: */
87 /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
88 #define OPA_LINKINIT_REASON_NOP 0
89 #define OPA_LINKINIT_REASON_LINKUP (1 << 4)
90 #define OPA_LINKINIT_REASON_FLAPPING (2 << 4)
91 #define OPA_LINKINIT_REASON_CLEAR (8 << 4)
92 #define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4)
93 #define OPA_LINKINIT_QUARANTINED (9 << 4)
94 #define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4)
95
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
99
100 #define OPA_LINK_WIDTH_1X 0x0001
101 #define OPA_LINK_WIDTH_2X 0x0002
102 #define OPA_LINK_WIDTH_3X 0x0004
103 #define OPA_LINK_WIDTH_4X 0x0008
104
105 #define OPA_CAP_MASK3_IsEthOnFabricSupported (1 << 13)
106 #define OPA_CAP_MASK3_IsSnoopSupported (1 << 7)
107 #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6)
108 #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
109 #define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4)
110 #define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3)
111 /* reserved (1 << 2) */
112 #define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1)
113 #define OPA_CAP_MASK3_IsVLrSupported (1 << 0)
114
115 enum {
116 OPA_PORT_PHYS_CONF_DISCONNECTED = 0,
117 OPA_PORT_PHYS_CONF_STANDARD = 1,
118 OPA_PORT_PHYS_CONF_FIXED = 2,
119 OPA_PORT_PHYS_CONF_VARIABLE = 3,
120 OPA_PORT_PHYS_CONF_SI_PHOTO = 4
121 };
122
123 enum port_info_field_masks {
124 /* vl.cap */
125 OPA_PI_MASK_VL_CAP = 0x1F,
126 /* port_states.ledenable_offlinereason */
127 OPA_PI_MASK_OFFLINE_REASON = 0x0F,
128 OPA_PI_MASK_LED_ENABLE = 0x40,
129 /* port_states.unsleepstate_downdefstate */
130 OPA_PI_MASK_UNSLEEP_STATE = 0xF0,
131 OPA_PI_MASK_DOWNDEF_STATE = 0x0F,
132 /* port_states.portphysstate_portstate */
133 OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0,
134 OPA_PI_MASK_PORT_STATE = 0x0F,
135 /* port_phys_conf */
136 OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F,
137 /* collectivemask_multicastmask */
138 OPA_PI_MASK_COLLECT_MASK = 0x38,
139 OPA_PI_MASK_MULTICAST_MASK = 0x07,
140 /* mkeyprotect_lmc */
141 OPA_PI_MASK_MKEY_PROT_BIT = 0xC0,
142 OPA_PI_MASK_LMC = 0x0F,
143 /* smsl */
144 OPA_PI_MASK_SMSL = 0x1F,
145 /* partenforce_filterraw */
146 /* Filter Raw In/Out bits 1 and 2 were removed */
147 OPA_PI_MASK_LINKINIT_REASON = 0xF0,
148 OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08,
149 OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04,
150 /* operational_vls */
151 OPA_PI_MASK_OPERATIONAL_VL = 0x1F,
152 /* sa_qp */
153 OPA_PI_MASK_SA_QP = 0x00FFFFFF,
154 /* sm_trap_qp */
155 OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF,
156 /* localphy_overrun_errors */
157 OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0,
158 OPA_PI_MASK_OVERRUN_ERRORS = 0x0F,
159 /* clientrereg_subnettimeout */
160 OPA_PI_MASK_CLIENT_REREGISTER = 0x80,
161 OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F,
162 /* port_link_mode */
163 OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10),
164 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
165 OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0),
166 /* port_link_crc_mode */
167 OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00,
168 OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0,
169 OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F,
170 /* port_mode */
171 OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001,
172 OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002,
173 OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004,
174 OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008,
175 OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010,
176 OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020,
177 OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040,
178 /* flit_control.interleave */
179 OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12),
180 OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10),
181 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
182 OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0),
183
184 /* port_error_action */
185 OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000,
186 /* 7 bits reserved */
187 OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000,
188 OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000,
189 OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000,
190 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000,
191 OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000,
192 OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000,
193 OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000,
194 OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000,
195 /* 2 bits reserved */
196 OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000,
197 OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000,
198 OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800,
199 /* 1 bit reserved */
200 OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200,
201 /* 1 bit reserved */
202 OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080,
203 OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040,
204 OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020,
205 OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010,
206 OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008,
207 OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004,
208 OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002,
209 OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001,
210
211 /* pass_through.res_drctl */
212 OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01,
213
214 /* buffer_units */
215 OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11),
216 OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6),
217 OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3),
218 OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0),
219
220 /* neigh_mtu.pvlx_to_mtu */
221 OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0,
222 OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F,
223
224 /* neigh_mtu.vlstall_hoq_life */
225 OPA_PI_MASK_VL_STALL = (0x03 << 5),
226 OPA_PI_MASK_HOQ_LIFE = (0x1F << 0),
227
228 /* port_neigh_mode */
229 OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3),
230 OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2),
231 OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0),
232
233 /* resptime_value */
234 OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F,
235
236 /* mtucap */
237 OPA_PI_MASK_MTU_CAP = 0x0F,
238 };
239
240 struct opa_port_states {
241 u8 reserved;
242 u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */
243 u8 reserved2;
244 u8 portphysstate_portstate; /* 4 bits, 4 bits */
245 };
246
247 struct opa_port_state_info {
248 struct opa_port_states port_states;
249 __be16 link_width_downgrade_tx_active;
250 __be16 link_width_downgrade_rx_active;
251 };
252
253 struct opa_port_info {
254 __be32 lid;
255 __be32 flow_control_mask;
256
257 struct {
258 u8 res; /* was inittype */
259 u8 cap; /* 3 res, 5 bits */
260 __be16 high_limit;
261 __be16 preempt_limit;
262 u8 arb_high_cap;
263 u8 arb_low_cap;
264 } vl;
265
266 struct opa_port_states port_states;
267 u8 port_phys_conf; /* 4 res, 4 bits */
268 u8 collectivemask_multicastmask; /* 2 res, 3, 3 */
269 u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */
270 u8 smsl; /* 3 res, 5 bits */
271
272 u8 partenforce_filterraw; /* bit fields */
273 u8 operational_vls; /* 3 res, 5 bits */
274 __be16 pkey_8b;
275 __be16 pkey_10b;
276 __be16 mkey_violations;
277
278 __be16 pkey_violations;
279 __be16 qkey_violations;
280 __be32 sm_trap_qp; /* 8 bits, 24 bits */
281
282 __be32 sa_qp; /* 8 bits, 24 bits */
283 u8 neigh_port_num;
284 u8 link_down_reason;
285 u8 neigh_link_down_reason;
286 u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */
287
288 struct {
289 __be16 supported;
290 __be16 enabled;
291 __be16 active;
292 } link_speed;
293 struct {
294 __be16 supported;
295 __be16 enabled;
296 __be16 active;
297 } link_width;
298 struct {
299 __be16 supported;
300 __be16 enabled;
301 __be16 tx_active;
302 __be16 rx_active;
303 } link_width_downgrade;
304 __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */
305 __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */
306
307 __be16 port_mode; /* 9 res, bit fields */
308 struct {
309 __be16 supported;
310 __be16 enabled;
311 } port_packet_format;
312 struct {
313 __be16 interleave; /* 2 res, 2,2,5,5 */
314 struct {
315 __be16 min_initial;
316 __be16 min_tail;
317 u8 large_pkt_limit;
318 u8 small_pkt_limit;
319 u8 max_small_pkt_limit;
320 u8 preemption_limit;
321 } preemption;
322 } flit_control;
323
324 __be32 reserved4;
325 __be32 port_error_action; /* bit field */
326
327 struct {
328 u8 egress_port;
329 u8 res_drctl; /* 7 res, 1 */
330 } pass_through;
331 __be16 mkey_lease_period;
332 __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */
333
334 __be32 reserved5;
335 __be32 sm_lid;
336
337 __be64 mkey;
338
339 __be64 subnet_prefix;
340
341 struct {
342 u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */
343 } neigh_mtu;
344
345 struct {
346 u8 vlstall_hoqlife; /* 3 bits, 5 bits */
347 } xmit_q[OPA_MAX_VLS];
348
349 struct {
350 u8 addr[16];
351 } ipaddr_ipv6;
352
353 struct {
354 u8 addr[4];
355 } ipaddr_ipv4;
356
357 u32 reserved6;
358 u32 reserved7;
359 u32 reserved8;
360
361 __be64 neigh_node_guid;
362
363 __be32 ib_cap_mask;
364 __be16 reserved9; /* was ib_cap_mask2 */
365 __be16 opa_cap_mask;
366
367 __be32 reserved10; /* was link_roundtrip_latency */
368 __be16 overall_buffer_space;
369 __be16 reserved11; /* was max_credit_hint */
370
371 __be16 diag_code;
372 struct {
373 u8 buffer;
374 u8 wire;
375 } replay_depth;
376 u8 port_neigh_mode;
377 u8 mtucap; /* 4 res, 4 bits */
378
379 u8 resptimevalue; /* 3 res, 5 bits */
380 u8 local_port_num;
381 u8 reserved12;
382 u8 reserved13; /* was guid_cap */
383 } __packed;
384
385 #endif /* OPA_PORT_INFO_H */
386
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