1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Microchip SAMA7 SFRBU registers offsets and bit definitions. 4 * 5 * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Claudu Beznea <claudiu.beznea@microchip.com> 8 */ 9 10 #ifndef __SAMA7_SFRBU_H__ 11 #define __SAMA7_SFRBU_H__ 12 13 #ifdef CONFIG_SOC_SAMA7 14 15 #define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */ 16 #define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */ 17 #define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */ 18 #define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ 19 #define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ 20 21 #define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ 22 #define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ 23 #define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ 24 #define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ 25 #define AT91_SFRBU_PD_VALUE_MSK (0x3) 26 #define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ 27 28 #define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ 29 #define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ 30 31 #endif /* CONFIG_SOC_SAMA7 */ 32 33 #endif /* __SAMA7_SFRBU_H__ */ 34 35
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