1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4 * Creative Labs, Inc.
5 * Definitions for EMU10K1 (SB Live!) chips
6 */
7 #ifndef __SOUND_EMU10K1_H
8 #define __SOUND_EMU10K1_H
9
10
11 #include <sound/pcm.h>
12 #include <sound/rawmidi.h>
13 #include <sound/hwdep.h>
14 #include <sound/ac97_codec.h>
15 #include <sound/util_mem.h>
16 #include <sound/pcm-indirect.h>
17 #include <sound/timer.h>
18 #include <linux/interrupt.h>
19 #include <linux/mutex.h>
20 #include <linux/firmware.h>
21 #include <linux/io.h>
22
23 #include <uapi/sound/emu10k1.h>
24
25 /* ------------------- DEFINES -------------------- */
26
27 #define EMUPAGESIZE 4096
28 #define MAXPAGES0 4096 /* 32 bit mode */
29 #define MAXPAGES1 8192 /* 31 bit mode */
30 #define NUM_G 64 /* use all channels */
31 #define NUM_EFX_PLAYBACK 16
32
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
34 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
36
37 #define TMEMSIZE 256*1024
38
39 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
40
41 // This is used to define hardware bit-fields (sub-registers) by combining
42 // the bit shift and count with the actual register address. The passed
43 // mask must represent a single run of adjacent bits.
44 // The non-concatenating (_NC) variant should be used directly only for
45 // sub-registers that do not follow the <register>_<field> naming pattern.
46 #define SUB_REG_NC(reg, field, mask) \
47 enum { \
48 field ## _MASK = mask, \
49 field = reg | \
50 (__builtin_ctz(mask) << 16) | \
51 (__builtin_popcount(mask) << 24), \
52 };
53 #define SUB_REG(reg, field, mask) SUB_REG_NC(reg, reg ## _ ## field, mask)
54
55 // Macros for manipulating values of bit-fields declared using the above macros.
56 // Best used with constant register addresses, as otherwise quite some code is
57 // generated. The actual register read/write functions handle combined addresses
58 // automatically, so use of these macros conveys no advantage when accessing a
59 // single sub-register at a time.
60 #define REG_SHIFT(r) (((r) >> 16) & 0x1f)
61 #define REG_SIZE(r) (((r) >> 24) & 0x1f)
62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
63 #define REG_MASK(r) (REG_MASK0(r) << REG_SHIFT(r))
64 #define REG_VAL_GET(r, v) ((v & REG_MASK(r)) >> REG_SHIFT(r))
65 #define REG_VAL_PUT(r, v) ((v) << REG_SHIFT(r))
66
67 // List terminator for snd_emu10k1_ptr_write_multiple()
68 #define REGLIST_END ~0
69
70 // Audigy specify registers are prefixed with 'A_'
71
72 /************************************************************************************************/
73 /* PCI function 0 registers, address = <val> + PCIBASE0 */
74 /************************************************************************************************/
75
76 #define PTR 0x00 /* Indexed register set pointer register */
77 /* NOTE: The CHANNELNUM and ADDRESS words can */
78 /* be modified independently of each other. */
79 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
80 /* channel number of the register to be */
81 /* accessed. For non per-channel registers the */
82 /* value should be set to zero. */
83 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
84 #define A_PTR_ADDRESS_MASK 0x0fff0000
85
86 #define DATA 0x04 /* Indexed register set data register */
87
88 #define IPR 0x08 /* Global interrupt pending register */
89 /* Clear pending interrupts by writing a 1 to */
90 /* the relevant bits and zero to the other bits */
91 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
92 to interrupt */
93 #define IPR_WATERMARK_REACHED 0x40000000
94 #define IPR_A_GPIO 0x20000000 /* GPIO input pin change */
95
96 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
97 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
98 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
99
100 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
101 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
102
103 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
104 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
105 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
106 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
107 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
108 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
109 #define IPR_MUTE 0x00040000 /* Mute button pressed */
110 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
111 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
112 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
113 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
114 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
115 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
116 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
117 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
118 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
119 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
120 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
121 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
122 /* The interrupt is triggered shortly after */
123 /* CCR_READADDRESS has crossed the boundary; */
124 /* due to the cache, this runs ahead of the */
125 /* actual playback position. */
126 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
127 /* highest set channel in CLIPL, CLIPH, HLIPL, */
128 /* or HLIPH. When IPR is written with CL set, */
129 /* the bit in H/CLIPL or H/CLIPH corresponding */
130 /* to the CN value written will be cleared. */
131
132 #define INTE 0x0c /* Interrupt enable register */
133 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
134 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
135 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
136 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
137 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
138 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
139 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
140 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
141 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
142 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
143 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
144 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
145 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
146 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
147 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
148 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
149 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
150 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
151
152 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
153 /* NOTE: There is no reason to use this under */
154 /* Linux, and it will cause odd hardware */
155 /* behavior and possibly random segfaults and */
156 /* lockups if enabled. */
157
158 #define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */
159
160 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
161 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
162 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
163
164 #define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000
165 #define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000
166
167 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
168 /* NOTE: This bit must always be enabled */
169 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
170 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
171 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
172 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
173 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
174 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
175 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
176 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
177 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
178 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
179 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
180 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
181 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
182
183 #define WC 0x10 /* Wall Clock register */
184 SUB_REG(WC, SAMPLECOUNTER, 0x03FFFFC0) /* Sample periods elapsed since reset */
185 SUB_REG(WC, CURRENTCHANNEL, 0x0000003F) /* Channel [0..63] currently being serviced */
186 /* NOTE: Each channel takes 1/64th of a sample */
187 /* period to be serviced. */
188
189 #define HCFG 0x14 /* Hardware config register */
190 /* NOTE: There is no reason to use the legacy */
191 /* SoundBlaster emulation stuff described below */
192 /* under Linux, and all kinds of weird hardware */
193 /* behavior can result if you try. Don't. */
194 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
195 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
196 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
197 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
198 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
199 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
200 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
201 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
202 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
203 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
204 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
205 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
206 /* NOTE: The rest of the bits in this register */
207 /* _are_ relevant under Linux. */
208 #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
210 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
211 #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
212
213 /* Specific to Alice2, CA0102 */
214
215 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
216 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
217 #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
218 /* will automatically mute their output when */
219 /* they are not rate-locked to the external */
220 /* async audio source */
221 #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
222 /* will automatically mute their output when */
223 /* the SPDIF V-bit indicates invalid audio */
224 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
225 #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
226 /* 0x00000800 not used on Alice2 */
227 #define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
228 /* phase track the previous input. */
229 /* I2S0 can phase track the last S/PDIF input */
230 #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
231 /* conversion for the corresponding */
232 /* I2S format input */
233 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
234
235 /* Older chips */
236
237 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
238 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
239 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
240 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
241 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
242 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
243 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
244 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
245 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
246 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
247 /* 1 = Force all 3 async digital inputs to use */
248 /* the same async sample rate tracker (ZVIDEO) */
249 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
250 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
251 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
252 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
253 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
254 /* will automatically mute their output when */
255 /* they are not rate-locked to the external */
256 /* async audio source */
257 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
258 /* NOTE: This should generally never be used. */
259 SUB_REG(HCFG, LOCKTANKCACHE, 0x00000004) /* 1 = Cancel bustmaster accesses to tankcache */
260 /* NOTE: This should generally never be used. */
261 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
262 /* NOTE: This is a 'cheap' way to implement a */
263 /* master mute function on the mute button, and */
264 /* in general should not be used unless a more */
265 /* sophisticated master mute function has not */
266 /* been written. */
267 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
268 /* Should be set to 1 when the EMU10K1 is */
269 /* completely initialized. */
270
271 // On Audigy, the MPU port moved to the 0x70-0x74 ptr registers
272
273 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
274
275 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
276 #define MUCMD_RESET 0xff /* RESET command */
277 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
278 /* NOTE: All other commands are ignored */
279
280 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
281 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
282 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
283
284 #define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */
285 #define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */
286 #define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */
287 #define A_GPOUTPUT_MASK 0x00ff
288
289 // The GPIO port is used for I/O config on Sound Blasters;
290 // card-specific info can be found in the emu_chip_details table.
291 // On E-MU cards the port is used as the interface to the FPGA.
292
293 // Audigy output/GPIO stuff taken from the kX drivers
294 #define A_IOCFG A_GPIO
295 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
296 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
297 #define A_IOCFG_ENABLE_DIGITAL 0x0004
298 #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
299 #define A_IOCFG_UNKNOWN_20 0x0020
300 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
301 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
302 #define A_IOCFG_GPOUT2 0x0001 /* IR */
303 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
304 /* + digital for generic 10k2 */
305 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
306 #define A_IOCFG_FRONT_JACK 0x4000
307 #define A_IOCFG_REAR_JACK 0x8000
308 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
309
310 #define TIMER 0x1a /* Timer terminal count register */
311 /* NOTE: After the rate is changed, a maximum */
312 /* of 1024 sample periods should be allowed */
313 /* before the new rate is guaranteed accurate. */
314 #define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */
315 /* 0 == 1024 periods, [1..4] are not useful */
316
317 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
318
319 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
320 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
321 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
322
323 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
324 #define PTR2 0x20 /* Indexed register set pointer register */
325 #define DATA2 0x24 /* Indexed register set data register */
326 #define IPR2 0x28 /* P16V interrupt pending register */
327 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
328 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
329 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
330 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
331 /* 0x00000100 Playback. Only in once per period.
332 * 0x00110000 Capture. Int on half buffer.
333 */
334 #define INTE2 0x2c /* P16V Interrupt enable register. */
335 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
336 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
337 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
338 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
339 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
340 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
341 #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
342 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
343 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
344 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
345 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
346 /* 0x00000000 2-channel output. */
347 /* 0x00000200 8-channel output. */
348 /* 0x00000004 pauses stream/irq fail. */
349 /* Rest of bits do nothing to sound output */
350 /* bit 0: Enable P16V audio.
351 * bit 1: Lock P16V record memory cache.
352 * bit 2: Lock P16V playback memory cache.
353 * bit 3: Dummy record insert zero samples.
354 * bit 8: Record 8-channel in phase.
355 * bit 9: Playback 8-channel in phase.
356 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
357 * bit 13: Playback mixer enable.
358 * bit 14: Route SRC48 mixer output to fx engine.
359 * bit 15: Enable IEEE 1394 chip.
360 */
361 #define IPR3 0x38 /* Cdif interrupt pending register */
362 #define INTE3 0x3c /* Cdif interrupt enable register. */
363
364 /************************************************************************************************/
365 /* PCI function 1 registers, address = <val> + PCIBASE1 */
366 /************************************************************************************************/
367
368 #define JOYSTICK1 0x00 /* Analog joystick port register */
369 #define JOYSTICK2 0x01 /* Analog joystick port register */
370 #define JOYSTICK3 0x02 /* Analog joystick port register */
371 #define JOYSTICK4 0x03 /* Analog joystick port register */
372 #define JOYSTICK5 0x04 /* Analog joystick port register */
373 #define JOYSTICK6 0x05 /* Analog joystick port register */
374 #define JOYSTICK7 0x06 /* Analog joystick port register */
375 #define JOYSTICK8 0x07 /* Analog joystick port register */
376
377 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
378 /* When reading, use these bitfields: */
379 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
380 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
381
382 /********************************************************************************************************/
383 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
384 /********************************************************************************************************/
385
386 // No official documentation was released for EMU10K1, but some info
387 // about playback can be extrapolated from the EMU8K documents:
388 // "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers
389 // "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view
390
391 // The short version:
392 // - The engine has 64 playback channels, also called voices. The channels
393 // operate independently, except when paired for stereo (see below).
394 // - PCM samples are fetched into the cache; see description of CD0 below.
395 // - Samples are consumed at the rate CPF_CURRENTPITCH.
396 // - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8
397 // - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated
398 // according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero
399 // CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim.
400 // - The value is multiplied by CVCF_CURRENTVOL.
401 // - The value goes through a filter with cutoff CVCF_CURRENTFILTER;
402 // delay stages Z1 and Z2.
403 // - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2)
404 // of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*,
405 // multiplied by a per-send amount (*_FXSENDAMOUNT_*).
406 // The scaling of the send amounts is exponential-ish.
407 // - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*.
408 // - The pitch, volume, and filter cutoff can be modulated by two envelope
409 // engines and two low frequency oscillators.
410 // - To avoid abrupt changes to the parameters (which may cause audible
411 // distortion), the modulation engine sets the target registers, towards
412 // which the current registers "swerve" gradually.
413
414 // For the odd channel in a stereo pair, these registers are meaningless:
415 // CPF_STEREO, CPF_CURRENTPITCH, PTRX_PITCHTARGET, CCR_CACHEINVALIDSIZE,
416 // PSST_LOOPSTARTADDR, DSL_LOOPENDADDR, CCCA_CURRADDR
417 // The somewhat non-obviously still meaningful ones are:
418 // CPF_STOP, CPF_FRACADDRESS, CCR_READADDRESS (!),
419 // CCCA_INTERPROM, CCCA_8BITSELECT (!)
420 // (The envelope engine is ignored here, as stereo matters only for verbatim playback.)
421
422 #define CPF 0x00 /* Current pitch and fraction register */
423 SUB_REG(CPF, CURRENTPITCH, 0xffff0000) /* Current pitch (linear, 0x4000 == unity pitch shift) */
424 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
425 SUB_REG(CPF, STOP, 0x00004000) /* 1 = Current pitch forced to 0 */
426 /* Can be set only while matching bit in SOLEx is 1 */
427 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
428
429 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
430 SUB_REG(PTRX, PITCHTARGET, 0xffff0000) /* Pitch target of specified channel */
431 SUB_REG(PTRX, FXSENDAMOUNT_A, 0x0000ff00) /* Linear level of channel output sent to FX send bus A */
432 SUB_REG(PTRX, FXSENDAMOUNT_B, 0x000000ff) /* Linear level of channel output sent to FX send bus B */
433
434 // Note: the volumes are raw multpliers, so real 100% is impossible.
435 #define CVCF 0x02 /* Current volume and filter cutoff register */
436 SUB_REG(CVCF, CURRENTVOL, 0xffff0000) /* Current linear volume of specified channel */
437 SUB_REG(CVCF, CURRENTFILTER, 0x0000ffff) /* Current filter cutoff frequency of specified channel */
438
439 #define VTFT 0x03 /* Volume target and filter cutoff target register */
440 SUB_REG(VTFT, VOLUMETARGET, 0xffff0000) /* Volume target of specified channel */
441 SUB_REG(VTFT, FILTERTARGET, 0x0000ffff) /* Filter cutoff target of specified channel */
442
443 #define Z1 0x05 /* Filter delay memory 1 register */
444
445 #define Z2 0x04 /* Filter delay memory 2 register */
446
447 #define PSST 0x06 /* Send C amount and loop start address register */
448 SUB_REG(PSST, FXSENDAMOUNT_C, 0xff000000) /* Linear level of channel output sent to FX send bus C */
449 SUB_REG(PSST, LOOPSTARTADDR, 0x00ffffff) /* Loop start address of the specified channel */
450
451 #define DSL 0x07 /* Send D amount and loop end address register */
452 SUB_REG(DSL, FXSENDAMOUNT_D, 0xff000000) /* Linear level of channel output sent to FX send bus D */
453 SUB_REG(DSL, LOOPENDADDR, 0x00ffffff) /* Loop end address of the specified channel */
454
455 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
456 SUB_REG(CCCA, RESONANCE, 0xf0000000) /* Lowpass filter resonance (Q) height */
457 #define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */
458 /* 1 == full band, 7 == lowpass */
459 /* ROM 0 is used when pitch shifting downward or less */
460 /* then 3 semitones upward. Increasingly higher ROM */
461 /* numbers are used, typically in steps of 3 semitones, */
462 /* as upward pitch shifting is performed. */
463 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
464 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
465 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
466 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
467 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
468 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
469 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
470 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
471 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
472 /* 8-bit samples are unsigned, 16-bit ones signed */
473 SUB_REG(CCCA, CURRADDR, 0x00ffffff) /* Current address of the selected channel */
474
475 #define CCR 0x09 /* Cache control register */
476 SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */
477 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
478 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
479 /* Auto-set from CPF_STEREO_MASK */
480 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
481 /* Auto-set from CCCA_8BITSELECT */
482 SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */
483 SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */
484 /* NOTE: This is valid only if CACHELOOPFLAG is set */
485 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
486 SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
487
488 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
489 /* NOTE: This register is normally not used */
490 SUB_REG(CLP, CACHELOOPADDR, 0x0000ffff) /* Cache loop address low word */
491
492 #define FXRT 0x0b /* Effects send routing register */
493 /* NOTE: It is illegal to assign the same routing to */
494 /* two effects sends. */
495 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
496 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
497 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
498 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
499
500 #define MAPA 0x0c /* Cache map A */
501 #define MAPB 0x0d /* Cache map B */
502
503 #define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */
504 #define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */
505
506 #define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
507 #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
508
509 /* 0x0e, 0x0f: Internal state, at least on Audigy */
510
511 #define ENVVOL 0x10 /* Volume envelope register */
512 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
513 /* 0x8000-n == 666*n usec delay */
514
515 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
516 #define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */
517 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
518 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
519 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
520
521 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
522 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */
523 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
524 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */
525 /* this channel and from writing to pitch, filter and */
526 /* volume targets. */
527 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
528 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
529
530 #define LFOVAL1 0x13 /* Modulation LFO value */
531 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
532 /* 0x8000-n == 666*n usec delay */
533
534 #define ENVVAL 0x14 /* Modulation envelope register */
535 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
536 /* 0x8000-n == 666*n usec delay */
537
538 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
539 #define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */
540 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
541 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
542 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
543
544 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
545 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */
546 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
547 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
548 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
549
550 #define LFOVAL2 0x17 /* Vibrato LFO register */
551 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
552 /* 0x8000-n == 666*n usec delay */
553
554 #define IP 0x18 /* Initial pitch register */
555 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
556 /* 4 bits of octave, 12 bits of fractional octave */
557 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
558
559 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
560 SUB_REG(IFATN, FILTERCUTOFF, 0x0000ff00) /* Initial filter cutoff frequency in exponential units */
561 /* 6 most significant bits are semitones */
562 /* 2 least significant bits are fractions */
563 SUB_REG(IFATN, ATTENUATION, 0x000000ff) /* Initial attenuation in 0.375dB steps */
564
565 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
566 SUB_REG(PEFE, PITCHAMOUNT, 0x0000ff00) /* Pitch envlope amount */
567 /* Signed 2's complement, +/- one octave peak extremes */
568 SUB_REG(PEFE, FILTERAMOUNT, 0x000000ff) /* Filter envlope amount */
569 /* Signed 2's complement, +/- six octaves peak extremes */
570
571
572 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
573 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
574 /* Signed 2's complement, +/- one octave extremes */
575 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
576 /* Signed 2's complement, +/- three octave extremes */
577
578 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
579 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
580 /* Signed 2's complement, with +/- 12dB extremes */
581 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
582 /* ??Hz steps, maximum of ?? Hz. */
583
584 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
585 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
586 /* Signed 2's complement, +/- one octave extremes */
587 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
588 /* 0.039Hz steps, maximum of 9.85 Hz. */
589
590 #define TEMPENV 0x1e /* Tempory envelope register */
591 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
592 /* NOTE: All channels contain internal variables; do */
593 /* not write to these locations. */
594
595 /* 0x1f: not used */
596
597 // 32 cache registers (== 128 bytes) per channel follow.
598 // In stereo mode, the two channels' caches are concatenated into one,
599 // and hold the interleaved frames.
600 // The cache holds 64 frames, so the upper half is not used in 8-bit mode.
601 // All registers mentioned below count in frames. Shortcuts:
602 // CA = CCCA_CURRADDR, CRA = CCR_READADDRESS,
603 // CLA = CCR_CACHELOOPADDRHI:CLP_CACHELOOPADDR,
604 // CIS = CCR_CACHEINVALIDSIZE, LIS = CCR_LOOPINVALSIZE,
605 // CLF = CCR_CACHELOOPFLAG, LF = CCR_LOOPFLAG
606 // The cache is a ring buffer; CRA operates modulo 64.
607 // The cache is filled from (CA - CIS) into (CRA - CIS).
608 // The engine has a fetch threshold of 32 bytes, so it tries to keep
609 // CIS below 8 (16-bit stereo), 16 (16-bit mono, 8-bit stereo), or
610 // 32 (8-bit mono). The actual transfers are pretty unpredictable,
611 // especially if several voices are running.
612 // Frames are consumed at CRA, which is incremented afterwards,
613 // along with CA and CIS. This implies that the actual playback
614 // position always lags CA by exactly 64 frames.
615 // When CA reaches DSL_LOOPENDADDR, LF is set for one frame's time.
616 // LF's rising edge causes the current values of CA and CIS to be
617 // copied into CLA and LIS, resp., and CLF to be set.
618 // If CLF is set, the first LIS of the CIS frames are instead
619 // filled from (CLA - LIS), and CLF is subsequently reset.
620 #define CD0 0x20 /* Cache data registers 0 .. 0x1f */
621
622 #define PTB 0x40 /* Page table base register */
623 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
624
625 #define TCB 0x41 /* Tank cache base register */
626 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
627
628 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
629 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
630 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
631 /* NOTE: To guarantee phase coherency, both channels */
632 /* must be disabled prior to enabling both channels. */
633 #define A_ADCCR_RCHANENABLE 0x00000020
634 #define A_ADCCR_LCHANENABLE 0x00000010
635
636 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
637 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
638 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
639 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
640 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
641 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
642 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
643 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
644 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
645 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
646 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
647 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
648 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
649
650 #define FXWC 0x43 /* FX output write channels register */
651 /* When set, each bit enables the writing of the */
652 /* corresponding FX output channel (internal registers */
653 /* 0x20-0x3f) to host memory. This mode of recording */
654 /* is 16bit, 48KHz only. All 32 channels can be enabled */
655 /* simultaneously. */
656
657 #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
658
659 #define TCBS 0x44 /* Tank cache buffer size register */
660 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
661 #define TCBS_BUFFSIZE_16K 0x00000000
662 #define TCBS_BUFFSIZE_32K 0x00000001
663 #define TCBS_BUFFSIZE_64K 0x00000002
664 #define TCBS_BUFFSIZE_128K 0x00000003
665 #define TCBS_BUFFSIZE_256K 0x00000004
666 #define TCBS_BUFFSIZE_512K 0x00000005
667 #define TCBS_BUFFSIZE_1024K 0x00000006
668 #define TCBS_BUFFSIZE_2048K 0x00000007
669
670 #define MICBA 0x45 /* AC97 microphone buffer address register */
671 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
672
673 #define ADCBA 0x46 /* ADC buffer address register */
674 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
675
676 #define FXBA 0x47 /* FX Buffer Address */
677 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
678
679 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
680
681 #define MICBS 0x49 /* Microphone buffer size register */
682
683 #define ADCBS 0x4a /* ADC buffer size register */
684
685 #define FXBS 0x4b /* FX buffer size register */
686
687 /* The following mask values define the size of the ADC, MIC and FX buffers in bytes */
688 #define ADCBS_BUFSIZE_NONE 0x00000000
689 #define ADCBS_BUFSIZE_384 0x00000001
690 #define ADCBS_BUFSIZE_448 0x00000002
691 #define ADCBS_BUFSIZE_512 0x00000003
692 #define ADCBS_BUFSIZE_640 0x00000004
693 #define ADCBS_BUFSIZE_768 0x00000005
694 #define ADCBS_BUFSIZE_896 0x00000006
695 #define ADCBS_BUFSIZE_1024 0x00000007
696 #define ADCBS_BUFSIZE_1280 0x00000008
697 #define ADCBS_BUFSIZE_1536 0x00000009
698 #define ADCBS_BUFSIZE_1792 0x0000000a
699 #define ADCBS_BUFSIZE_2048 0x0000000b
700 #define ADCBS_BUFSIZE_2560 0x0000000c
701 #define ADCBS_BUFSIZE_3072 0x0000000d
702 #define ADCBS_BUFSIZE_3584 0x0000000e
703 #define ADCBS_BUFSIZE_4096 0x0000000f
704 #define ADCBS_BUFSIZE_5120 0x00000010
705 #define ADCBS_BUFSIZE_6144 0x00000011
706 #define ADCBS_BUFSIZE_7168 0x00000012
707 #define ADCBS_BUFSIZE_8192 0x00000013
708 #define ADCBS_BUFSIZE_10240 0x00000014
709 #define ADCBS_BUFSIZE_12288 0x00000015
710 #define ADCBS_BUFSIZE_14366 0x00000016
711 #define ADCBS_BUFSIZE_16384 0x00000017
712 #define ADCBS_BUFSIZE_20480 0x00000018
713 #define ADCBS_BUFSIZE_24576 0x00000019
714 #define ADCBS_BUFSIZE_28672 0x0000001a
715 #define ADCBS_BUFSIZE_32768 0x0000001b
716 #define ADCBS_BUFSIZE_40960 0x0000001c
717 #define ADCBS_BUFSIZE_49152 0x0000001d
718 #define ADCBS_BUFSIZE_57344 0x0000001e
719 #define ADCBS_BUFSIZE_65536 0x0000001f
720
721 // On Audigy, the FX send amounts are not applied instantly, but determine
722 // targets towards which the following registers swerve gradually.
723 #define A_CSBA 0x4c /* FX send B & A current amounts */
724 #define A_CSDC 0x4d /* FX send D & C current amounts */
725 #define A_CSFE 0x4e /* FX send F & E current amounts */
726 #define A_CSHG 0x4f /* FX send H & G current amounts */
727
728 // NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1)
729 #define CDCS 0x50 /* CD-ROM digital channel status register */
730
731 #define GPSCS 0x51 /* General Purpose SPDIF channel status register */
732
733 // Corresponding EMU10K1_DBG_* constants are in the public header
734 #define DBG 0x52
735
736 #define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
737
738 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
739
740 // Corresponding A_DBG_* constants are in the public header
741 #define A_DBG 0x53
742
743 // NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
744 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
745
746 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
747
748 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
749
750 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
751 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
752 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
753 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
754 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
755 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
756 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
757 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
758 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
759 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
760 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
761 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
762 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
763 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
764 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
765 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
766 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
767 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
768 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
769 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
770 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
771 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
772 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
773
774 /* 0x57: Not used */
775
776 /* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */
777 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
778 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
779
780 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
781 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
782
783 // These cause CPF_STOP_MASK to be set shortly after CCCA_CURRADDR passes DSL_LOOPENDADDR.
784 // Subsequent changes to the address registers don't resume; clearing the bit here or in CPF does.
785 // The registers are NOT synchronized; the next serviced channel picks up immediately.
786 #define SOLEL 0x5c /* Stop on loop enable low register */
787 #define SOLEH 0x5d /* Stop on loop enable high register */
788
789 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
790 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
791 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
792 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
793 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
794
795 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
796 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
797 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
798 #define AC97SLOT_CNTR 0x10 /* Center enable */
799 #define AC97SLOT_LFE 0x20 /* LFE enable */
800
801 #define A_PCB 0x5f /* PCB Revision */
802
803 // NOTE: 0x60,61,62: 64-bit
804 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
805
806 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
807
808 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
809 /* NOTE: This one has no SPDIFLOCKED field */
810 /* Assumes sample lock */
811
812 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
813 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
814 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
815 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
816 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
817
818 /* Note that these values can vary +/- by a small amount */
819 #define SRCS_SPDIFRATE_44 0x0003acd9
820 #define SRCS_SPDIFRATE_48 0x00040000
821 #define SRCS_SPDIFRATE_96 0x00080000
822
823 #define MICIDX 0x63 /* Microphone recording buffer index register */
824 SUB_REG(MICIDX, IDX, 0x0000ffff)
825
826 #define ADCIDX 0x64 /* ADC recording buffer index register */
827 SUB_REG(ADCIDX, IDX, 0x0000ffff)
828
829 #define A_ADCIDX 0x63
830 SUB_REG(A_ADCIDX, IDX, 0x0000ffff)
831
832 #define A_MICIDX 0x64
833 SUB_REG(A_MICIDX, IDX, 0x0000ffff)
834
835 #define FXIDX 0x65 /* FX recording buffer index register */
836 SUB_REG(FXIDX, IDX, 0x0000ffff)
837
838 /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */
839 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */
840 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */
841
842 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */
843 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */
844
845 #define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */
846 #define A_SPRA 0x6b /* S/PDIF Host Record Address */
847 #define A_SPRC 0x6c /* S/PDIF Host Record Control */
848
849 #define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */
850
851 #define A_TTB 0x6e /* Tank Table Base */
852 #define A_TDOF 0x6f /* Tank Delay Offset */
853
854 /* This is the MPU port on the card (via the game port) */
855 #define A_MUDATA1 0x70
856 #define A_MUCMD1 0x71
857 #define A_MUSTAT1 A_MUCMD1
858
859 /* This is the MPU port on the Audigy Drive */
860 #define A_MUDATA2 0x72
861 #define A_MUCMD2 0x73
862 #define A_MUSTAT2 A_MUCMD2
863
864 /* The next two are the Audigy equivalent of FXWC */
865 /* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */
866 /* Each bit selects a channel for recording */
867 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
868 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
869
870 #define A_EHC 0x76 /* Extended Hardware Control */
871
872 #define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */
873 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
874 #define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */
875 #define A_SPDIF_192000 0x00000020
876 #define A_SPDIF_96000 0x00000040
877 #define A_SPDIF_44100 0x00000080
878 #define A_SPDIF_MUTED 0x000000c0
879
880 SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00) /* This sets the capture PCM rate, but it is */
881 /* unclear if this sets the ADC rate as well. */
882 #define A_I2S_CAPTURE_48000 0x0
883 #define A_I2S_CAPTURE_192000 0x1
884 #define A_I2S_CAPTURE_96000 0x2
885 #define A_I2S_CAPTURE_44100 0x4
886
887 #define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
888 #define A_EHC_SRC48_BYPASS 0x00000000
889 #define A_EHC_SRC48_192 0x00002000
890 #define A_EHC_SRC48_96 0x00004000
891 #define A_EHC_SRC48_44 0x00008000
892 #define A_EHC_SRC48_MUTED 0x0000c000
893
894 #define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */
895 #define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */
896 #define A_EHC_P17V_SEL1_MASK 0x000c0000
897 #define A_EHC_P17V_SEL2_MASK 0x00300000
898 #define A_EHC_P17V_SEL3_MASK 0x00c00000
899
900 #define A_EHC_ASYNC_BYPASS 0x80000000
901
902 #define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */
903 #define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */
904 #define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */
905 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
906
907 #define A_SRT_ESTSAMPLERATE 0x001fffff
908 #define A_SRT_RATELOCKED 0x01000000
909
910 #define A_TTDA 0x7a /* Tank Table DMA Address */
911 #define A_TTDD 0x7b /* Tank Table DMA Data */
912
913 // In A_FXRT1 & A_FXRT2, the 0x80 bit of each byte completely disables the
914 // filter (CVCF_CURRENTFILTER) for the corresponding channel. There is no
915 // effect on the volume (CVCF_CURRENTVOLUME) or the interpolator's filter
916 // (CCCA_INTERPROM_MASK).
917
918 #define A_FXRT2 0x7c
919 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
920 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
921 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
922 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
923
924 #define A_SENDAMOUNTS 0x7d
925 #define A_FXSENDAMOUNT_E_MASK 0xFF000000
926 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
927 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
928 #define A_FXSENDAMOUNT_H_MASK 0x000000FF
929
930 /* The send amounts for this one are the same as used with the emu10k1 */
931 #define A_FXRT1 0x7e
932 #define A_FXRT_CHANNELA 0x0000003f
933 #define A_FXRT_CHANNELB 0x00003f00
934 #define A_FXRT_CHANNELC 0x003f0000
935 #define A_FXRT_CHANNELD 0x3f000000
936
937 /* 0x7f: Not used */
938
939 /* The public header defines the GPR and TRAM base addresses that
940 * are valid for _both_ CPU and DSP addressing. */
941
942 /* Each DSP microcode instruction is mapped into 2 doublewords */
943 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
944 #define MICROCODEBASE 0x400 /* Microcode data base address */
945 #define A_MICROCODEBASE 0x600
946
947
948 /************************************************************************************************/
949 /* E-MU Digital Audio System overview */
950 /************************************************************************************************/
951
952 // - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2);
953 // the PCIe variants simply put the Audigy chip behind a PCI bridge.
954 // - All physical PCM I/O is routed through an additional FPGA; the regular
955 // EXTIN/EXTOUT ports are unconnected.
956 // - The FPGA has a signal routing matrix, to connect each destination (output
957 // socket or capture channel) to a source (input socket or playback channel).
958 // - The FPGA is controlled via Audigy's GPIO port, while sample data is
959 // transmitted via proprietary EMU32 serial links. On first-generation
960 // E-MU 1010 cards, Audigy's I2S inputs are also used for sample data.
961 // - The Audio/Micro Dock is attached to Hana via EDI, a "network" link.
962 // - The Audigy chip operates in slave mode; the clock is supplied by the FPGA.
963 // Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples),
964 // while the later cards use a single crystal and a PLL chip.
965 // - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz
966 // sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels
967 // are bundled.
968 // - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total
969 // number of usable inputs/outputs is limited, esp. with ADAT in use.
970 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
971 // to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels
972 // can overlap with the Dock's ADC/DAC's high channels.
973 // - The code names are mentioned below and in the emu_chip_details table.
974
975 /************************************************************************************************/
976 /* EMU1010 FPGA registers */
977 /************************************************************************************************/
978
979 #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
980 #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
981
982 #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
983 #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
984
985 #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
986 #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
987
988 #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
989 /* Must be written after power on to reset DLL */
990 /* One is unable to detect the Audio dock without this */
991 #define EMU_HANA_WCLOCK_SRC_MASK 0x07
992 #define EMU_HANA_WCLOCK_INT_48K 0x00
993 #define EMU_HANA_WCLOCK_INT_44_1K 0x01
994 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
995 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
996 #define EMU_HANA_WCLOCK_SYNC_BNC 0x04
997 #define EMU_HANA_WCLOCK_2ND_HANA 0x05
998 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
999 #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
1000 #define EMU_HANA_WCLOCK_MULT_MASK 0x18
1001 #define EMU_HANA_WCLOCK_1X 0x00
1002 #define EMU_HANA_WCLOCK_2X 0x08
1003 #define EMU_HANA_WCLOCK_4X 0x10
1004 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
1005
1006 // If the selected external clock source is/becomes invalid or incompatible
1007 // with the clock multiplier, the clock source is reset to this value, and
1008 // a WCLK_CHANGED interrupt is raised.
1009 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
1010 #define EMU_HANA_DEFCLOCK_48K 0x00
1011 #define EMU_HANA_DEFCLOCK_44_1K 0x01
1012
1013 #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
1014 #define EMU_MUTE 0x00
1015 #define EMU_UNMUTE 0x01
1016
1017 #define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
1018 #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
1019 #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
1020
1021 #define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
1022 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1023 #define EMU_HANA_IRQ_ADAT 0x02
1024 #define EMU_HANA_IRQ_DOCK 0x04
1025 #define EMU_HANA_IRQ_DOCK_LOST 0x08
1026
1027 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
1028 #define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00
1029 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
1030 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1031 #define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00
1032 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1033 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1034 #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1035
1036 #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
1037 #define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1038 #define EMU_HANA_OPTICAL_IN_ADAT 0x01
1039 #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1040 #define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1041
1042 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1043 #define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */
1044 #define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */
1045 #define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */
1046 #define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */
1047 #define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */
1048 #define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */
1049
1050 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
1051 #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
1052 #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
1053 #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
1054 #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
1055
1056 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
1057 #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
1058 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1059 #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
1060 #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
1061 #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
1062 #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
1063
1064 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
1065 #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
1066 #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
1067 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
1068 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
1069 #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
1070 #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
1071
1072 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1073 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1074 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
1075 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
1076 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1077
1078 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1079 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1080 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
1081 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
1082 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
1083 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1084 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1085 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1086 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1087
1088 #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
1089 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
1090 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
1091 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
1092 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
1093 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
1094
1095 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1096 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
1097 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
1098 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
1099 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
1100 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
1101
1102 /* 0x14 - 0x1f Unused R/W registers */
1103
1104 #define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */
1105 /* Same bits as for EMU_HANA_IRQ_ENABLE */
1106 /* Reading the register resets it. */
1107
1108 #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
1109 #define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */
1110 #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
1111 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */
1112 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */
1113
1114 #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */
1115 /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */
1116
1117 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1118 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1119
1120 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1121 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1122
1123 #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
1124 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1125 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1126
1127 // The actual code disagrees about the bit width of the registers -
1128 // the formula used is freq = 0x1770000 / (((X_HI << 5) | X_LO) + 1)
1129
1130 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1131 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1132
1133 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1134 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1135
1136 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1137 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1138
1139 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1140 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1141
1142 /* 0x30 - 0x3f Unused Read only registers */
1143
1144 // The meaning of this is not clear; kX-project just calls it "lock" in some info-only code.
1145 #define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */
1146 #define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */
1147
1148 /************************************************************************************************/
1149 /* EMU1010 Audio Destinations */
1150 /************************************************************************************************/
1151 /* Hana, original 1010,1212m,1820[m] using Alice2
1152 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1153 * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock
1154 * 0x00: Dock DAC 1 Left
1155 * 0x04: Dock DAC 1 Right
1156 * 0x08: Dock DAC 2 Left
1157 * 0x0c: Dock DAC 2 Right
1158 * 0x10: Dock DAC 3 Left
1159 * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left)
1160 * 0x14: Dock DAC 3 Right
1161 * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right)
1162 * 0x18: Dock DAC 4 Left
1163 * 0x1a: S/PDIF Left
1164 * 0x1c: Dock DAC 4 Right
1165 * 0x1e: S/PDIF Right
1166 * 0x02, 0x00: Hana S/PDIF Left
1167 * 0x02, 0x01: Hana S/PDIF Right
1168 * 0x03, 0x00: Hamoa DAC Left
1169 * 0x03, 0x01: Hamoa DAC Right
1170 * 0x04, 0x00-0x07: Hana ADAT
1171 * 0x05, 0x00: I2S0 Left to Alice2
1172 * 0x05, 0x01: I2S0 Right to Alice2
1173 * 0x06, 0x00: I2S0 Left to Alice2
1174 * 0x06, 0x01: I2S0 Right to Alice2
1175 * 0x07, 0x00: I2S0 Left to Alice2
1176 * 0x07, 0x01: I2S0 Right to Alice2
1177 *
1178 * Hana2 never released, but used Tina
1179 * Not needed.
1180 *
1181 * Hana3, rev2 1010,1212m,1616[m] using Tina
1182 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1183 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1184 * 0x00: Dock DAC 1 Left
1185 * 0x04: Dock DAC 1 Right
1186 * 0x08: Dock DAC 2 Left
1187 * 0x0c: Dock DAC 2 Right
1188 * 0x10: Dock DAC 3 Left
1189 * 0x12: Dock S/PDIF Left
1190 * 0x14: Dock DAC 3 Right
1191 * 0x16: Dock S/PDIF Right
1192 * 0x18-0x1f: Dock ADAT 0-7
1193 * 0x02, 0x00: Hana3 S/PDIF Left
1194 * 0x02, 0x01: Hana3 S/PDIF Right
1195 * 0x03, 0x00: Hamoa DAC Left
1196 * 0x03, 0x01: Hamoa DAC Right
1197 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1198 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1199 * 0x06-0x07: Not used
1200 *
1201 * HanaLite, rev1 0404 using Alice2
1202 * HanaLiteLite, rev2 0404 using Tina
1203 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina
1204 * 0x01: Not used
1205 * 0x02, 0x00: S/PDIF Left
1206 * 0x02, 0x01: S/PDIF Right
1207 * 0x03, 0x00: DAC Left
1208 * 0x03, 0x01: DAC Right
1209 * 0x04-0x07: Not used
1210 *
1211 * Mana, Cardbus 1616 using Tina2
1212 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1213 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1214 * (same as rev2 1010)
1215 * 0x02: Not used
1216 * 0x03, 0x00: Mana DAC Left
1217 * 0x03, 0x01: Mana DAC Right
1218 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1219 * 0x05-0x07: Not used
1220 */
1221
1222 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1223 * physical outputs of Hana, or outputs going to Alice2/Tina for capture -
1224 * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into
1225 * a channel depends on the mixer control setting for each destination - see
1226 * the register arrays in emumixer.c.
1227 */
1228 #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
1229 /* This channel is delayed by one sample. */
1230 #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1231 #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1232 #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1233 #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1234 #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1235 #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1236 #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1237 #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1238 #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1239 #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1240 #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
1241 #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
1242 #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
1243 #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
1244 #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
1245 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1246 #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1247 #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1248 #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
1249 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1250 #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1251 #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1252 #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
1253 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1254 #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1255 #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1256 #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
1257 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1258 #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1259 #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1260 #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
1261 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1262 #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1263 #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1264 #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
1265 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1266 #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
1267 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1268 #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1269 #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1270 #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
1271 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1272 #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
1273 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1274 #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1275 #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1276 #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
1277 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1278 #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
1279 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1280 #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1281 #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1282 #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
1283 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1284 #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
1285 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1286 #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
1287 #define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */
1288 #define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */
1289 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1290 #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
1291 #define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */
1292 #define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */
1293 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1294 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1295 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1296 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1297 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1298 #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1299 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1300 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1301 // In S/MUX mode, the samples of one channel are adjacent.
1302 #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
1303 #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
1304 #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
1305 #define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
1306 #define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
1307 #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
1308 #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
1309
1310 /* Additional destinations for 1616(M)/Microdock */
1311
1312 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1313 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1314 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1315 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1316 #define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */
1317
1318 #define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1319 #define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1320
1321 /************************************************************************************************/
1322 /* EMU1010 Audio Sources */
1323 /************************************************************************************************/
1324 /* Hana, original 1010,1212m,1820[m] using Alice2
1325 * 0x00, 0x00-0x1f: Silence
1326 * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock
1327 * 0x00: Dock Mic A
1328 * 0x04: Dock Mic B
1329 * 0x08: Dock ADC 1 Left
1330 * 0x0c: Dock ADC 1 Right
1331 * 0x10: Dock ADC 2 Left
1332 * 0x14: Dock ADC 2 Right
1333 * 0x18: Dock ADC 3 Left
1334 * 0x1c: Dock ADC 3 Right
1335 * 0x02, 0x00: Hamoa ADC Left
1336 * 0x02, 0x01: Hamoa ADC Right
1337 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1338 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1339 * 0x04, 0x00-0x07: Hana ADAT
1340 * 0x05, 0x00: Hana S/PDIF Left
1341 * 0x05, 0x01: Hana S/PDIF Right
1342 * 0x06-0x07: Not used
1343 *
1344 * Hana2 never released, but used Tina
1345 * Not needed.
1346 *
1347 * Hana3, rev2 1010,1212m,1616[m] using Tina
1348 * 0x00, 0x00-0x1f: Silence
1349 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1350 * 0x00: Dock Mic A
1351 * 0x04: Dock Mic B
1352 * 0x08: Dock ADC 1 Left
1353 * 0x0c: Dock ADC 1 Right
1354 * 0x10: Dock ADC 2 Left
1355 * 0x12: Dock S/PDIF Left
1356 * 0x14: Dock ADC 2 Right
1357 * 0x16: Dock S/PDIF Right
1358 * 0x18-0x1f: Dock ADAT 0-7
1359 * 0x02, 0x00: Hamoa ADC Left
1360 * 0x02, 0x01: Hamoa ADC Right
1361 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1362 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1363 * 0x04, 0x00-0x07: Hana3 ADAT
1364 * 0x05, 0x00: Hana3 S/PDIF Left
1365 * 0x05, 0x01: Hana3 S/PDIF Right
1366 * 0x06-0x07: Not used
1367 *
1368 * HanaLite, rev1 0404 using Alice2
1369 * HanaLiteLite, rev2 0404 using Tina
1370 * 0x00, 0x00-0x1f: Silence
1371 * 0x01: Not used
1372 * 0x02, 0x00: ADC Left
1373 * 0x02, 0x01: ADC Right
1374 * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output
1375 * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output
1376 * 0x04: Not used
1377 * 0x05, 0x00: S/PDIF Left
1378 * 0x05, 0x01: S/PDIF Right
1379 * 0x06-0x07: Not used
1380 *
1381 * Mana, Cardbus 1616 using Tina2
1382 * 0x00, 0x00-0x1f: Silence
1383 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1384 * (same as rev2 1010)
1385 * 0x02: Not used
1386 * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output
1387 * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output
1388 * 0x04-0x07: Not used
1389 */
1390
1391 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1392 * destinations using a mixer control for each destination - see emumixer.c.
1393 * Sources are either physical inputs of Hana, or inputs from Alice2/Tina -
1394 * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B.
1395 */
1396 #define EMU_SRC_SILENCE 0x0000 /* Silence */
1397 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1398 #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
1399 #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
1400 #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
1401 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1402 #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
1403 #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
1404 #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
1405 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1406 #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
1407 #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
1408 #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
1409 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1410 #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
1411 #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
1412 #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
1413 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1414 #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
1415 #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
1416 #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
1417 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1418 #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
1419 #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
1420 #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
1421 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1422 #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
1423 #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
1424 #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
1425 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1426 #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
1427 #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
1428 #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
1429 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1430 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1431 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1432 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1433 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1434 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1435 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1436 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1437 #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
1438 #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
1439 // In S/MUX mode, the samples of one channel are adjacent.
1440 #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
1441 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1442 #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
1443 #define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */
1444 #define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */
1445 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1446 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
1447 #define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */
1448 #define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */
1449
1450 /* Additional inputs for 1616(M)/Microdock */
1451
1452 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */
1453 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */
1454 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */
1455 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */
1456 #define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */
1457
1458 /* 0x600 and 0x700 no used */
1459
1460
1461 /* ------------------- CONSTANTS -------------------- */
1462
1463 extern const char * const snd_emu10k1_fxbus[32];
1464 extern const char * const snd_emu10k1_sblive_ins[16];
1465 extern const char * const snd_emu10k1_audigy_ins[16];
1466 extern const char * const snd_emu10k1_sblive_outs[32];
1467 extern const char * const snd_emu10k1_audigy_outs[32];
1468 extern const s8 snd_emu10k1_sblive51_fxbus2_map[16];
1469
1470 /* ------------------- STRUCTURES -------------------- */
1471
1472 enum {
1473 EMU10K1_UNUSED, // This must be zero
1474 EMU10K1_EFX,
1475 EMU10K1_EFX_IRQ,
1476 EMU10K1_PCM,
1477 EMU10K1_PCM_IRQ,
1478 EMU10K1_SYNTH,
1479 EMU10K1_NUM_TYPES
1480 };
1481
1482 struct snd_emu10k1;
1483
1484 struct snd_emu10k1_voice {
1485 unsigned char number;
1486 unsigned char use;
1487 unsigned char dirty;
1488 unsigned char last;
1489 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1490
1491 struct snd_emu10k1_pcm *epcm;
1492 };
1493
1494 enum {
1495 PLAYBACK_EMUVOICE,
1496 PLAYBACK_EFX,
1497 CAPTURE_AC97ADC,
1498 CAPTURE_AC97MIC,
1499 CAPTURE_EFX
1500 };
1501
1502 struct snd_emu10k1_pcm {
1503 struct snd_emu10k1 *emu;
1504 int type;
1505 struct snd_pcm_substream *substream;
1506 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1507 struct snd_emu10k1_voice *extra;
1508 unsigned short running;
1509 unsigned short first_ptr;
1510 snd_pcm_uframes_t resume_pos;
1511 struct snd_util_memblk *memblk;
1512 unsigned int pitch_target;
1513 unsigned int start_addr;
1514 unsigned int ccca_start_addr;
1515 unsigned int capture_ipr; /* interrupt acknowledge mask */
1516 unsigned int capture_inte; /* interrupt enable mask */
1517 unsigned int capture_ba_reg; /* buffer address register */
1518 unsigned int capture_bs_reg; /* buffer size register */
1519 unsigned int capture_idx_reg; /* buffer index register */
1520 unsigned int capture_cr_val; /* control value */
1521 unsigned int capture_cr_val2; /* control value2 (for audigy) */
1522 unsigned int capture_bs_val; /* buffer size value */
1523 unsigned int capture_bufsize; /* buffer size in bytes */
1524 };
1525
1526 struct snd_emu10k1_pcm_mixer {
1527 /* mono, left, right x 8 sends (4 on emu10k1) */
1528 unsigned char send_routing[3][8];
1529 unsigned char send_volume[3][8];
1530 // 0x8000 is neutral. The mixer code rescales it to 0xffff to maintain
1531 // backwards compatibility with user space.
1532 unsigned short attn[3];
1533 struct snd_emu10k1_pcm *epcm;
1534 };
1535
1536 #define snd_emu10k1_compose_send_routing(route) \
1537 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1538
1539 #define snd_emu10k1_compose_audigy_fxrt1(route) \
1540 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24) | 0x80808080)
1541
1542 #define snd_emu10k1_compose_audigy_fxrt2(route) \
1543 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24) | 0x80808080)
1544
1545 #define snd_emu10k1_compose_audigy_sendamounts(vol) \
1546 (((unsigned int)vol[4] << 24) | ((unsigned int)vol[5] << 16) | ((unsigned int)vol[6] << 8) | (unsigned int)vol[7])
1547
1548 struct snd_emu10k1_memblk {
1549 struct snd_util_memblk mem;
1550 /* private part */
1551 int first_page, last_page, pages, mapped_page;
1552 unsigned int map_locked;
1553 struct list_head mapped_link;
1554 struct list_head mapped_order_link;
1555 };
1556
1557 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1558
1559 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1560
1561 struct snd_emu10k1_fx8010_ctl {
1562 struct list_head list; /* list link container */
1563 unsigned int vcount;
1564 unsigned int count; /* count of GPR (1..16) */
1565 unsigned short gpr[32]; /* GPR number(s) */
1566 int value[32];
1567 int min; /* minimum range */
1568 int max; /* maximum range */
1569 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1570 struct snd_kcontrol *kcontrol;
1571 };
1572
1573 typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1574
1575 struct snd_emu10k1_fx8010_irq {
1576 struct snd_emu10k1_fx8010_irq *next;
1577 snd_fx8010_irq_handler_t *handler;
1578 unsigned short gpr_running;
1579 void *private_data;
1580 };
1581
1582 struct snd_emu10k1_fx8010_pcm {
1583 unsigned int valid: 1,
1584 opened: 1,
1585 active: 1;
1586 unsigned int channels; /* 16-bit channels count */
1587 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1588 unsigned int buffer_size; /* count of buffered samples */
1589 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1590 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1591 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1592 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1593 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1594 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1595 unsigned char etram[32]; /* external TRAM address & data */
1596 struct snd_pcm_indirect pcm_rec;
1597 unsigned int tram_pos;
1598 unsigned int tram_shift;
1599 struct snd_emu10k1_fx8010_irq irq;
1600 };
1601
1602 struct snd_emu10k1_fx8010 {
1603 unsigned short extin_mask; /* used external inputs (bitmask); not used for Audigy */
1604 unsigned short extout_mask; /* used external outputs (bitmask); not used for Audigy */
1605 unsigned int itram_size; /* internal TRAM size in samples */
1606 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1607 unsigned int dbg; /* FX debugger register */
1608 unsigned char name[128];
1609 int gpr_size; /* size of allocated GPR controls */
1610 int gpr_count; /* count of used kcontrols */
1611 struct list_head gpr_ctl; /* GPR controls */
1612 struct mutex lock;
1613 struct snd_emu10k1_fx8010_pcm pcm[8];
1614 spinlock_t irq_lock;
1615 struct snd_emu10k1_fx8010_irq *irq_handlers;
1616 };
1617
1618 struct snd_emu10k1_midi {
1619 struct snd_emu10k1 *emu;
1620 struct snd_rawmidi *rmidi;
1621 struct snd_rawmidi_substream *substream_input;
1622 struct snd_rawmidi_substream *substream_output;
1623 unsigned int midi_mode;
1624 spinlock_t input_lock;
1625 spinlock_t output_lock;
1626 spinlock_t open_lock;
1627 int tx_enable, rx_enable;
1628 int port;
1629 int ipr_tx, ipr_rx;
1630 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1631 };
1632
1633 enum {
1634 EMU_MODEL_SB,
1635 EMU_MODEL_EMU1010,
1636 EMU_MODEL_EMU1010B,
1637 EMU_MODEL_EMU1616,
1638 EMU_MODEL_EMU0404,
1639 };
1640
1641 // Chip-o-logy:
1642 // - All SB Live! cards use EMU10K1 chips
1643 // - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver
1644 // - Original Audigy uses CA0100 "Alice"
1645 // - Audigy 2 uses CA0102/CA10200 "Alice2"
1646 // - Has an interface for CA0151 (P16V) "Alice3"
1647 // - Audigy 2 Value uses CA0108/CA10300 "Tina"
1648 // - Approximately a CA0102 with an on-chip CA0151 (P17V)
1649 // - Audigy 2 ZS NB uses CA0109 "Tina2"
1650 // - Cardbus version of CA0108
1651 struct snd_emu_chip_details {
1652 u32 vendor;
1653 u32 device;
1654 u32 subsystem;
1655 unsigned char revision;
1656 unsigned char emu_model; /* EMU model type */
1657 unsigned int emu10k1_chip:1; /* Original SB Live. Not SB Live 24bit. */
1658 /* Redundant with emu10k2_chip being unset. */
1659 unsigned int emu10k2_chip:1; /* Audigy 1 or Audigy 2. */
1660 unsigned int ca0102_chip:1; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1661 /* Redundant with ca0108_chip being unset. */
1662 unsigned int ca0108_chip:1; /* Audigy 2 Value */
1663 unsigned int ca_cardbus_chip:1; /* Audigy 2 ZS Notebook */
1664 unsigned int ca0151_chip:1; /* P16V */
1665 unsigned int spk20:1; /* Stereo only */
1666 unsigned int spk71:1; /* Has 7.1 speakers */
1667 unsigned int no_adat:1; /* Has no ADAT, only SPDIF */
1668 unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1669 unsigned int spdif_bug:1; /* Has Spdif phasing bug */
1670 unsigned int ac97_chip:2; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1671 unsigned int ecard:1; /* APS EEPROM */
1672 unsigned int spi_dac:1; /* SPI interface for DAC; requires ca0108_chip */
1673 unsigned int i2c_adc:1; /* I2C interface for ADC; requires ca0108_chip */
1674 unsigned int adc_1361t:1; /* Use Philips 1361T ADC */
1675 unsigned int invert_shared_spdif:1; /* analog/digital switch inverted */
1676 const char *driver;
1677 const char *name;
1678 const char *id; /* for backward compatibility - can be NULL if not needed */
1679 };
1680
1681 #define NUM_OUTPUT_DESTS 28
1682 #define NUM_INPUT_DESTS 22
1683
1684 struct snd_emu1010 {
1685 unsigned char output_source[NUM_OUTPUT_DESTS];
1686 unsigned char input_source[NUM_INPUT_DESTS];
1687 unsigned int adc_pads; /* bit mask */
1688 unsigned int dac_pads; /* bit mask */
1689 unsigned int wclock; /* Cached register value */
1690 unsigned int word_clock; /* Cached effective value */
1691 unsigned int clock_source;
1692 unsigned int clock_fallback;
1693 unsigned int optical_in; /* 0:SPDIF, 1:ADAT */
1694 unsigned int optical_out; /* 0:SPDIF, 1:ADAT */
1695 struct work_struct work;
1696 struct mutex lock;
1697 };
1698
1699 struct snd_emu10k1 {
1700 int irq;
1701
1702 unsigned long port; /* I/O port number */
1703 unsigned int tos_link: 1, /* tos link detected */
1704 rear_ac97: 1, /* rear channels are on AC'97 */
1705 enable_ir: 1;
1706 unsigned int support_tlv :1;
1707 /* Contains profile of card capabilities */
1708 const struct snd_emu_chip_details *card_capabilities;
1709 unsigned int audigy; /* is Audigy? */
1710 unsigned int revision; /* chip revision */
1711 unsigned int serial; /* serial number */
1712 unsigned short model; /* subsystem id */
1713 unsigned int ecard_ctrl; /* ecard control bits */
1714 unsigned int address_mode; /* address mode */
1715 unsigned long dma_mask; /* PCI DMA mask */
1716 bool iommu_workaround; /* IOMMU workaround needed */
1717 int max_cache_pages; /* max memory size / PAGE_SIZE */
1718 struct snd_dma_buffer silent_page; /* silent page */
1719 struct snd_dma_buffer ptb_pages; /* page table pages */
1720 struct snd_dma_device p16v_dma_dev;
1721 struct snd_dma_buffer *p16v_buffer;
1722
1723 struct snd_util_memhdr *memhdr; /* page allocation list */
1724
1725 struct list_head mapped_link_head;
1726 struct list_head mapped_order_link_head;
1727 void **page_ptr_table;
1728 unsigned long *page_addr_table;
1729 spinlock_t memblk_lock;
1730
1731 unsigned int spdif_bits[3]; /* s/pdif out setup */
1732 unsigned int i2c_capture_source;
1733 u8 i2c_capture_volume[4][2];
1734
1735 struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */
1736 int gpr_base;
1737
1738 struct snd_ac97 *ac97;
1739
1740 struct pci_dev *pci;
1741 struct snd_card *card;
1742 struct snd_pcm *pcm;
1743 struct snd_pcm *pcm_mic;
1744 struct snd_pcm *pcm_efx;
1745 struct snd_pcm *pcm_multi;
1746 struct snd_pcm *pcm_p16v;
1747
1748 spinlock_t synth_lock;
1749 void *synth;
1750 int (*get_synth_voice)(struct snd_emu10k1 *emu);
1751
1752 spinlock_t reg_lock; // high-level driver lock
1753 spinlock_t emu_lock; // low-level i/o lock
1754 spinlock_t voice_lock; // voice allocator lock
1755 spinlock_t spi_lock; /* serialises access to spi port */
1756 spinlock_t i2c_lock; /* serialises access to i2c port */
1757
1758 struct snd_emu10k1_voice voices[NUM_G];
1759 int p16v_device_offset;
1760 u32 p16v_capture_source;
1761 u32 p16v_capture_channel;
1762 struct snd_emu1010 emu1010;
1763 struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1764 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1765 struct snd_kcontrol *ctl_send_routing;
1766 struct snd_kcontrol *ctl_send_volume;
1767 struct snd_kcontrol *ctl_attn;
1768 struct snd_kcontrol *ctl_efx_send_routing;
1769 struct snd_kcontrol *ctl_efx_send_volume;
1770 struct snd_kcontrol *ctl_efx_attn;
1771 struct snd_kcontrol *ctl_clock_source;
1772
1773 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1774 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1775 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1776 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1777 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1778 void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1779 void (*gpio_interrupt)(struct snd_emu10k1 *emu);
1780 void (*p16v_interrupt)(struct snd_emu10k1 *emu);
1781
1782 struct snd_pcm_substream *pcm_capture_substream;
1783 struct snd_pcm_substream *pcm_capture_mic_substream;
1784 struct snd_pcm_substream *pcm_capture_efx_substream;
1785
1786 struct snd_timer *timer;
1787
1788 struct snd_emu10k1_midi midi;
1789 struct snd_emu10k1_midi midi2; /* for audigy */
1790
1791 unsigned int efx_voices_mask[2];
1792 unsigned int next_free_voice;
1793
1794 const struct firmware *firmware;
1795 const struct firmware *dock_fw;
1796
1797 #ifdef CONFIG_PM_SLEEP
1798 unsigned int *saved_ptr;
1799 unsigned int *saved_gpr;
1800 unsigned int *tram_val_saved;
1801 unsigned int *tram_addr_saved;
1802 unsigned int *saved_icode;
1803 unsigned int *p16v_saved;
1804 unsigned int saved_a_iocfg, saved_hcfg;
1805 bool suspend;
1806 #endif
1807
1808 };
1809
1810 int snd_emu10k1_create(struct snd_card *card,
1811 struct pci_dev *pci,
1812 unsigned short extin_mask,
1813 unsigned short extout_mask,
1814 long max_cache_bytes,
1815 int enable_ir,
1816 uint subsystem);
1817
1818 int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device);
1819 int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device);
1820 int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device);
1821 int snd_p16v_pcm(struct snd_emu10k1 *emu, int device);
1822 int snd_p16v_mixer(struct snd_emu10k1 * emu);
1823 int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device);
1824 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device);
1825 int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1826 int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1827 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device);
1828
1829 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1830
1831 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1832 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1833 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1834 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1835 int snd_emu10k1_done(struct snd_emu10k1 * emu);
1836
1837 /* I/O functions */
1838 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1839 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1840 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...);
1841 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1842 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1843 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1844 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1845 static inline void snd_emu1010_fpga_lock(struct snd_emu10k1 *emu) { mutex_lock(&emu->emu1010.lock); };
1846 static inline void snd_emu1010_fpga_unlock(struct snd_emu10k1 *emu) { mutex_unlock(&emu->emu1010.lock); };
1847 void snd_emu1010_fpga_write_lock(struct snd_emu10k1 *emu, u32 reg, u32 value);
1848 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1849 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value);
1850 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src);
1851 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst);
1852 int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src);
1853 void snd_emu1010_update_clock(struct snd_emu10k1 *emu);
1854 void snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, int dock, const struct firmware *fw_entry);
1855 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1856 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1857 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1858 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1859 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1860 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1861 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1862 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1863 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1864 #if 0
1865 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1866 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1867 #endif
1868 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices);
1869 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices);
1870 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices);
1871 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
1872 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1873 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1874 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1875
1876 #ifdef CONFIG_PM_SLEEP
1877 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1878 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1879 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1880 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1881 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1882 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1883 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1884 int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1885 void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1886 void snd_p16v_suspend(struct snd_emu10k1 *emu);
1887 void snd_p16v_resume(struct snd_emu10k1 *emu);
1888 #endif
1889
1890 /* memory allocation */
1891 struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1892 int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1893 int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size,
1894 struct snd_dma_buffer *dmab);
1895 struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1896 int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1897 int snd_emu10k1_synth_memset(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size, u8 value);
1898 int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size, u32 xor);
1899 int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1900
1901 /* voice allocation */
1902 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int count, int channels,
1903 struct snd_emu10k1_pcm *epcm, struct snd_emu10k1_voice **rvoice);
1904 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1905
1906 /* MIDI uart */
1907 int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1908 int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1909
1910 /* proc interface */
1911 int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1912
1913 /* fx8010 irq handler */
1914 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1915 snd_fx8010_irq_handler_t *handler,
1916 unsigned char gpr_running,
1917 void *private_data,
1918 struct snd_emu10k1_fx8010_irq *irq);
1919 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1920 struct snd_emu10k1_fx8010_irq *irq);
1921
1922 #endif /* __SOUND_EMU10K1_H */
1923
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