1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2023 Intel Corporation
4 */
5
6 #ifndef _UAPI_XE_DRM_H_
7 #define _UAPI_XE_DRM_H_
8
9 #include "drm.h"
10
11 #if defined(__cplusplus)
12 extern "C" {
13 #endif
14
15 /*
16 * Please note that modifications to all structs defined here are
17 * subject to backwards-compatibility constraints.
18 * Sections in this file are organized as follows:
19 * 1. IOCTL definition
20 * 2. Extension definition and helper structs
21 * 3. IOCTL's Query structs in the order of the Query's entries.
22 * 4. The rest of IOCTL structs in the order of IOCTL declaration.
23 */
24
25 /**
26 * DOC: Xe Device Block Diagram
27 *
28 * The diagram below represents a high-level simplification of a discrete
29 * GPU supported by the Xe driver. It shows some device components which
30 * are necessary to understand this API, as well as how their relations
31 * to each other. This diagram does not represent real hardware::
32 *
33 * ┌──────────────────────────────────────────────────────────────────┐
34 * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │
35 * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │
36 * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │
37 * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │
38 * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │
39 * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │
40 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
41 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │
42 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
43 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
44 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │
45 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
46 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
47 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │
48 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
49 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
50 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │
51 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
52 * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
53 * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │
54 * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
55 * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │
56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
57 * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │
58 * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │
59 * └─────────────────────────────Device0───────┬──────────────────────┘
60 * │
61 * ───────────────────────┴────────── PCI bus
62 */
63
64 /**
65 * DOC: Xe uAPI Overview
66 *
67 * This section aims to describe the Xe's IOCTL entries, its structs, and other
68 * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related
69 * entries and usage.
70 *
71 * List of supported IOCTLs:
72 * - &DRM_IOCTL_XE_DEVICE_QUERY
73 * - &DRM_IOCTL_XE_GEM_CREATE
74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
75 * - &DRM_IOCTL_XE_VM_CREATE
76 * - &DRM_IOCTL_XE_VM_DESTROY
77 * - &DRM_IOCTL_XE_VM_BIND
78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
81 * - &DRM_IOCTL_XE_EXEC
82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE
83 * - &DRM_IOCTL_XE_OBSERVATION
84 */
85
86 /*
87 * xe specific ioctls.
88 *
89 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
90 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
91 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
92 */
93 #define DRM_XE_DEVICE_QUERY 0x00
94 #define DRM_XE_GEM_CREATE 0x01
95 #define DRM_XE_GEM_MMAP_OFFSET 0x02
96 #define DRM_XE_VM_CREATE 0x03
97 #define DRM_XE_VM_DESTROY 0x04
98 #define DRM_XE_VM_BIND 0x05
99 #define DRM_XE_EXEC_QUEUE_CREATE 0x06
100 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07
101 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08
102 #define DRM_XE_EXEC 0x09
103 #define DRM_XE_WAIT_USER_FENCE 0x0a
104 #define DRM_XE_OBSERVATION 0x0b
105
106 /* Must be kept compact -- no holes */
107
108 #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
109 #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
110 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
111 #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
112 #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
113 #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
114 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)
115 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
116 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)
117 #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
118 #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
119 #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
120
121 /**
122 * DOC: Xe IOCTL Extensions
123 *
124 * Before detailing the IOCTLs and its structs, it is important to highlight
125 * that every IOCTL in Xe is extensible.
126 *
127 * Many interfaces need to grow over time. In most cases we can simply
128 * extend the struct and have userspace pass in more data. Another option,
129 * as demonstrated by Vulkan's approach to providing extensions for forward
130 * and backward compatibility, is to use a list of optional structs to
131 * provide those extra details.
132 *
133 * The key advantage to using an extension chain is that it allows us to
134 * redefine the interface more easily than an ever growing struct of
135 * increasing complexity, and for large parts of that interface to be
136 * entirely optional. The downside is more pointer chasing; chasing across
137 * the __user boundary with pointers encapsulated inside u64.
138 *
139 * Example chaining:
140 *
141 * .. code-block:: C
142 *
143 * struct drm_xe_user_extension ext3 {
144 * .next_extension = 0, // end
145 * .name = ...,
146 * };
147 * struct drm_xe_user_extension ext2 {
148 * .next_extension = (uintptr_t)&ext3,
149 * .name = ...,
150 * };
151 * struct drm_xe_user_extension ext1 {
152 * .next_extension = (uintptr_t)&ext2,
153 * .name = ...,
154 * };
155 *
156 * Typically the struct drm_xe_user_extension would be embedded in some uAPI
157 * struct, and in this case we would feed it the head of the chain(i.e ext1),
158 * which would then apply all of the above extensions.
159 */
160
161 /**
162 * struct drm_xe_user_extension - Base class for defining a chain of extensions
163 */
164 struct drm_xe_user_extension {
165 /**
166 * @next_extension:
167 *
168 * Pointer to the next struct drm_xe_user_extension, or zero if the end.
169 */
170 __u64 next_extension;
171
172 /**
173 * @name: Name of the extension.
174 *
175 * Note that the name here is just some integer.
176 *
177 * Also note that the name space for this is not global for the whole
178 * driver, but rather its scope/meaning is limited to the specific piece
179 * of uAPI which has embedded the struct drm_xe_user_extension.
180 */
181 __u32 name;
182
183 /**
184 * @pad: MBZ
185 *
186 * All undefined bits must be zero.
187 */
188 __u32 pad;
189 };
190
191 /**
192 * struct drm_xe_ext_set_property - Generic set property extension
193 *
194 * A generic struct that allows any of the Xe's IOCTL to be extended
195 * with a set_property operation.
196 */
197 struct drm_xe_ext_set_property {
198 /** @base: base user extension */
199 struct drm_xe_user_extension base;
200
201 /** @property: property to set */
202 __u32 property;
203
204 /** @pad: MBZ */
205 __u32 pad;
206
207 /** @value: property value */
208 __u64 value;
209
210 /** @reserved: Reserved */
211 __u64 reserved[2];
212 };
213
214 /**
215 * struct drm_xe_engine_class_instance - instance of an engine class
216 *
217 * It is returned as part of the @drm_xe_engine, but it also is used as
218 * the input of engine selection for both @drm_xe_exec_queue_create and
219 * @drm_xe_query_engine_cycles
220 *
221 * The @engine_class can be:
222 * - %DRM_XE_ENGINE_CLASS_RENDER
223 * - %DRM_XE_ENGINE_CLASS_COPY
224 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE
225 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE
226 * - %DRM_XE_ENGINE_CLASS_COMPUTE
227 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual
228 * hardware engine class). Used for creating ordered queues of VM
229 * bind operations.
230 */
231 struct drm_xe_engine_class_instance {
232 #define DRM_XE_ENGINE_CLASS_RENDER 0
233 #define DRM_XE_ENGINE_CLASS_COPY 1
234 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
235 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
236 #define DRM_XE_ENGINE_CLASS_COMPUTE 4
237 #define DRM_XE_ENGINE_CLASS_VM_BIND 5
238 /** @engine_class: engine class id */
239 __u16 engine_class;
240 /** @engine_instance: engine instance id */
241 __u16 engine_instance;
242 /** @gt_id: Unique ID of this GT within the PCI Device */
243 __u16 gt_id;
244 /** @pad: MBZ */
245 __u16 pad;
246 };
247
248 /**
249 * struct drm_xe_engine - describe hardware engine
250 */
251 struct drm_xe_engine {
252 /** @instance: The @drm_xe_engine_class_instance */
253 struct drm_xe_engine_class_instance instance;
254
255 /** @reserved: Reserved */
256 __u64 reserved[3];
257 };
258
259 /**
260 * struct drm_xe_query_engines - describe engines
261 *
262 * If a query is made with a struct @drm_xe_device_query where .query
263 * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of
264 * struct @drm_xe_query_engines in .data.
265 */
266 struct drm_xe_query_engines {
267 /** @num_engines: number of engines returned in @engines */
268 __u32 num_engines;
269 /** @pad: MBZ */
270 __u32 pad;
271 /** @engines: The returned engines for this device */
272 struct drm_xe_engine engines[];
273 };
274
275 /**
276 * enum drm_xe_memory_class - Supported memory classes.
277 */
278 enum drm_xe_memory_class {
279 /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
280 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0,
281 /**
282 * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
283 * represents the memory that is local to the device, which we
284 * call VRAM. Not valid on integrated platforms.
285 */
286 DRM_XE_MEM_REGION_CLASS_VRAM
287 };
288
289 /**
290 * struct drm_xe_mem_region - Describes some region as known to
291 * the driver.
292 */
293 struct drm_xe_mem_region {
294 /**
295 * @mem_class: The memory class describing this region.
296 *
297 * See enum drm_xe_memory_class for supported values.
298 */
299 __u16 mem_class;
300 /**
301 * @instance: The unique ID for this region, which serves as the
302 * index in the placement bitmask used as argument for
303 * &DRM_IOCTL_XE_GEM_CREATE
304 */
305 __u16 instance;
306 /**
307 * @min_page_size: Min page-size in bytes for this region.
308 *
309 * When the kernel allocates memory for this region, the
310 * underlying pages will be at least @min_page_size in size.
311 * Buffer objects with an allowable placement in this region must be
312 * created with a size aligned to this value.
313 * GPU virtual address mappings of (parts of) buffer objects that
314 * may be placed in this region must also have their GPU virtual
315 * address and range aligned to this value.
316 * Affected IOCTLS will return %-EINVAL if alignment restrictions are
317 * not met.
318 */
319 __u32 min_page_size;
320 /**
321 * @total_size: The usable size in bytes for this region.
322 */
323 __u64 total_size;
324 /**
325 * @used: Estimate of the memory used in bytes for this region.
326 *
327 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
328 * accounting. Without this the value here will always equal
329 * zero.
330 */
331 __u64 used;
332 /**
333 * @cpu_visible_size: How much of this region can be CPU
334 * accessed, in bytes.
335 *
336 * This will always be <= @total_size, and the remainder (if
337 * any) will not be CPU accessible. If the CPU accessible part
338 * is smaller than @total_size then this is referred to as a
339 * small BAR system.
340 *
341 * On systems without small BAR (full BAR), the probed_size will
342 * always equal the @total_size, since all of it will be CPU
343 * accessible.
344 *
345 * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM
346 * regions (for other types the value here will always equal
347 * zero).
348 */
349 __u64 cpu_visible_size;
350 /**
351 * @cpu_visible_used: Estimate of CPU visible memory used, in
352 * bytes.
353 *
354 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
355 * accounting. Without this the value here will always equal
356 * zero. Note this is only currently tracked for
357 * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value
358 * here will always be zero).
359 */
360 __u64 cpu_visible_used;
361 /** @reserved: Reserved */
362 __u64 reserved[6];
363 };
364
365 /**
366 * struct drm_xe_query_mem_regions - describe memory regions
367 *
368 * If a query is made with a struct drm_xe_device_query where .query
369 * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses
370 * struct drm_xe_query_mem_regions in .data.
371 */
372 struct drm_xe_query_mem_regions {
373 /** @num_mem_regions: number of memory regions returned in @mem_regions */
374 __u32 num_mem_regions;
375 /** @pad: MBZ */
376 __u32 pad;
377 /** @mem_regions: The returned memory regions for this device */
378 struct drm_xe_mem_region mem_regions[];
379 };
380
381 /**
382 * struct drm_xe_query_config - describe the device configuration
383 *
384 * If a query is made with a struct drm_xe_device_query where .query
385 * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
386 * struct drm_xe_query_config in .data.
387 *
388 * The index in @info can be:
389 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits)
390 * and the device revision (next 8 bits)
391 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device
392 * configuration, see list below
393 *
394 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device
395 * has usable VRAM
396 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
397 * required by this device, typically SZ_4K or SZ_64K
398 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
399 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
400 * available exec queue priority
401 */
402 struct drm_xe_query_config {
403 /** @num_params: number of parameters returned in info */
404 __u32 num_params;
405
406 /** @pad: MBZ */
407 __u32 pad;
408
409 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
410 #define DRM_XE_QUERY_CONFIG_FLAGS 1
411 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
412 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
413 #define DRM_XE_QUERY_CONFIG_VA_BITS 3
414 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
415 /** @info: array of elements containing the config info */
416 __u64 info[];
417 };
418
419 /**
420 * struct drm_xe_gt - describe an individual GT.
421 *
422 * To be used with drm_xe_query_gt_list, which will return a list with all the
423 * existing GT individual descriptions.
424 * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for
425 * implementing graphics and/or media operations.
426 *
427 * The index in @type can be:
428 * - %DRM_XE_QUERY_GT_TYPE_MAIN
429 * - %DRM_XE_QUERY_GT_TYPE_MEDIA
430 */
431 struct drm_xe_gt {
432 #define DRM_XE_QUERY_GT_TYPE_MAIN 0
433 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1
434 /** @type: GT type: Main or Media */
435 __u16 type;
436 /** @tile_id: Tile ID where this GT lives (Information only) */
437 __u16 tile_id;
438 /** @gt_id: Unique ID of this GT within the PCI Device */
439 __u16 gt_id;
440 /** @pad: MBZ */
441 __u16 pad[3];
442 /** @reference_clock: A clock frequency for timestamp */
443 __u32 reference_clock;
444 /**
445 * @near_mem_regions: Bit mask of instances from
446 * drm_xe_query_mem_regions that are nearest to the current engines
447 * of this GT.
448 * Each index in this mask refers directly to the struct
449 * drm_xe_query_mem_regions' instance, no assumptions should
450 * be made about order. The type of each region is described
451 * by struct drm_xe_query_mem_regions' mem_class.
452 */
453 __u64 near_mem_regions;
454 /**
455 * @far_mem_regions: Bit mask of instances from
456 * drm_xe_query_mem_regions that are far from the engines of this GT.
457 * In general, they have extra indirections when compared to the
458 * @near_mem_regions. For a discrete device this could mean system
459 * memory and memory living in a different tile.
460 * Each index in this mask refers directly to the struct
461 * drm_xe_query_mem_regions' instance, no assumptions should
462 * be made about order. The type of each region is described
463 * by struct drm_xe_query_mem_regions' mem_class.
464 */
465 __u64 far_mem_regions;
466 /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */
467 __u16 ip_ver_major;
468 /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */
469 __u16 ip_ver_minor;
470 /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */
471 __u16 ip_ver_rev;
472 /** @pad2: MBZ */
473 __u16 pad2;
474 /** @reserved: Reserved */
475 __u64 reserved[7];
476 };
477
478 /**
479 * struct drm_xe_query_gt_list - A list with GT description items.
480 *
481 * If a query is made with a struct drm_xe_device_query where .query
482 * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct
483 * drm_xe_query_gt_list in .data.
484 */
485 struct drm_xe_query_gt_list {
486 /** @num_gt: number of GT items returned in gt_list */
487 __u32 num_gt;
488 /** @pad: MBZ */
489 __u32 pad;
490 /** @gt_list: The GT list returned for this device */
491 struct drm_xe_gt gt_list[];
492 };
493
494 /**
495 * struct drm_xe_query_topology_mask - describe the topology mask of a GT
496 *
497 * This is the hardware topology which reflects the internal physical
498 * structure of the GPU.
499 *
500 * If a query is made with a struct drm_xe_device_query where .query
501 * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
502 * struct drm_xe_query_topology_mask in .data.
503 *
504 * The @type can be:
505 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices
506 * (DSS) available for geometry operations. For example a query response
507 * containing the following in mask:
508 * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00``
509 * means 32 DSS are available for geometry.
510 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices
511 * (DSS) available for compute operations. For example a query response
512 * containing the following in mask:
513 * ``DSS_COMPUTE ff ff ff ff 00 00 00 00``
514 * means 32 DSS are available for compute.
515 * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks
516 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
517 * available per Dual Sub Slices (DSS). For example a query response
518 * containing the following in mask:
519 * ``EU_PER_DSS ff ff 00 00 00 00 00 00``
520 * means each DSS has 16 EU.
521 */
522 struct drm_xe_query_topology_mask {
523 /** @gt_id: GT ID the mask is associated with */
524 __u16 gt_id;
525
526 #define DRM_XE_TOPO_DSS_GEOMETRY 1
527 #define DRM_XE_TOPO_DSS_COMPUTE 2
528 #define DRM_XE_TOPO_L3_BANK 3
529 #define DRM_XE_TOPO_EU_PER_DSS 4
530 /** @type: type of mask */
531 __u16 type;
532
533 /** @num_bytes: number of bytes in requested mask */
534 __u32 num_bytes;
535
536 /** @mask: little-endian mask of @num_bytes */
537 __u8 mask[];
538 };
539
540 /**
541 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps
542 *
543 * If a query is made with a struct drm_xe_device_query where .query is equal to
544 * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles
545 * in .data. struct drm_xe_query_engine_cycles is allocated by the user and
546 * .data points to this allocated structure.
547 *
548 * The query returns the engine cycles, which along with GT's @reference_clock,
549 * can be used to calculate the engine timestamp. In addition the
550 * query returns a set of cpu timestamps that indicate when the command
551 * streamer cycle count was captured.
552 */
553 struct drm_xe_query_engine_cycles {
554 /**
555 * @eci: This is input by the user and is the engine for which command
556 * streamer cycles is queried.
557 */
558 struct drm_xe_engine_class_instance eci;
559
560 /**
561 * @clockid: This is input by the user and is the reference clock id for
562 * CPU timestamp. For definition, see clock_gettime(2) and
563 * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC,
564 * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.
565 */
566 __s32 clockid;
567
568 /** @width: Width of the engine cycle counter in bits. */
569 __u32 width;
570
571 /**
572 * @engine_cycles: Engine cycles as read from its register
573 * at 0x358 offset.
574 */
575 __u64 engine_cycles;
576
577 /**
578 * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before
579 * reading the engine_cycles register using the reference clockid set by the
580 * user.
581 */
582 __u64 cpu_timestamp;
583
584 /**
585 * @cpu_delta: Time delta in ns captured around reading the lower dword
586 * of the engine_cycles register.
587 */
588 __u64 cpu_delta;
589 };
590
591 /**
592 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version
593 *
594 * Given a uc_type this will return the branch, major, minor and patch version
595 * of the micro-controller firmware.
596 */
597 struct drm_xe_query_uc_fw_version {
598 /** @uc_type: The micro-controller type to query firmware version */
599 #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0
600 #define XE_QUERY_UC_TYPE_HUC 1
601 __u16 uc_type;
602
603 /** @pad: MBZ */
604 __u16 pad;
605
606 /** @branch_ver: branch uc fw version */
607 __u32 branch_ver;
608 /** @major_ver: major uc fw version */
609 __u32 major_ver;
610 /** @minor_ver: minor uc fw version */
611 __u32 minor_ver;
612 /** @patch_ver: patch uc fw version */
613 __u32 patch_ver;
614
615 /** @pad2: MBZ */
616 __u32 pad2;
617
618 /** @reserved: Reserved */
619 __u64 reserved;
620 };
621
622 /**
623 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main
624 * structure to query device information
625 *
626 * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_*
627 * and sets the value in the query member. This determines the type of
628 * the structure provided by the driver in data, among struct drm_xe_query_*.
629 *
630 * The @query can be:
631 * - %DRM_XE_DEVICE_QUERY_ENGINES
632 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS
633 * - %DRM_XE_DEVICE_QUERY_CONFIG
634 * - %DRM_XE_DEVICE_QUERY_GT_LIST
635 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware
636 * configuration of the device such as information on slices, memory,
637 * caches, and so on. It is provided as a table of key / value
638 * attributes.
639 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
640 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
641 *
642 * If size is set to 0, the driver fills it with the required size for
643 * the requested type of data to query. If size is equal to the required
644 * size, the queried information is copied into data. If size is set to
645 * a value different from 0 and different from the required size, the
646 * IOCTL call returns -EINVAL.
647 *
648 * For example the following code snippet allows retrieving and printing
649 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
650 *
651 * .. code-block:: C
652 *
653 * struct drm_xe_query_engines *engines;
654 * struct drm_xe_device_query query = {
655 * .extensions = 0,
656 * .query = DRM_XE_DEVICE_QUERY_ENGINES,
657 * .size = 0,
658 * .data = 0,
659 * };
660 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
661 * engines = malloc(query.size);
662 * query.data = (uintptr_t)engines;
663 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
664 * for (int i = 0; i < engines->num_engines; i++) {
665 * printf("Engine %d: %s\n", i,
666 * engines->engines[i].instance.engine_class ==
667 * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER":
668 * engines->engines[i].instance.engine_class ==
669 * DRM_XE_ENGINE_CLASS_COPY ? "COPY":
670 * engines->engines[i].instance.engine_class ==
671 * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE":
672 * engines->engines[i].instance.engine_class ==
673 * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE":
674 * engines->engines[i].instance.engine_class ==
675 * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE":
676 * "UNKNOWN");
677 * }
678 * free(engines);
679 */
680 struct drm_xe_device_query {
681 /** @extensions: Pointer to the first extension struct, if any */
682 __u64 extensions;
683
684 #define DRM_XE_DEVICE_QUERY_ENGINES 0
685 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1
686 #define DRM_XE_DEVICE_QUERY_CONFIG 2
687 #define DRM_XE_DEVICE_QUERY_GT_LIST 3
688 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4
689 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
690 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6
691 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7
692 #define DRM_XE_DEVICE_QUERY_OA_UNITS 8
693 /** @query: The type of data to query */
694 __u32 query;
695
696 /** @size: Size of the queried data */
697 __u32 size;
698
699 /** @data: Queried data is placed here */
700 __u64 data;
701
702 /** @reserved: Reserved */
703 __u64 reserved[2];
704 };
705
706 /**
707 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for
708 * gem creation
709 *
710 * The @flags can be:
711 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING
712 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
713 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
714 * possible placement, ensure that the corresponding VRAM allocation
715 * will always use the CPU accessible part of VRAM. This is important
716 * for small-bar systems (on full-bar systems this gets turned into a
717 * noop).
718 * Note1: System memory can be used as an extra placement if the kernel
719 * should spill the allocation to system memory, if space can't be made
720 * available in the CPU accessible part of VRAM (giving the same
721 * behaviour as the i915 interface, see
722 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
723 * Note2: For clear-color CCS surfaces the kernel needs to read the
724 * clear-color value stored in the buffer, and on discrete platforms we
725 * need to use VRAM for display surfaces, therefore the kernel requires
726 * setting this flag for such objects, otherwise an error is thrown on
727 * small-bar systems.
728 *
729 * @cpu_caching supports the following values:
730 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
731 * caching. On iGPU this can't be used for scanout surfaces. Currently
732 * not allowed for objects placed in VRAM.
733 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This
734 * is uncached. Scanout surfaces should likely use this. All objects
735 * that can be placed in VRAM must use this.
736 */
737 struct drm_xe_gem_create {
738 /** @extensions: Pointer to the first extension struct, if any */
739 __u64 extensions;
740
741 /**
742 * @size: Size of the object to be created, must match region
743 * (system or vram) minimum alignment (&min_page_size).
744 */
745 __u64 size;
746
747 /**
748 * @placement: A mask of memory instances of where BO can be placed.
749 * Each index in this mask refers directly to the struct
750 * drm_xe_query_mem_regions' instance, no assumptions should
751 * be made about order. The type of each region is described
752 * by struct drm_xe_query_mem_regions' mem_class.
753 */
754 __u32 placement;
755
756 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0)
757 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1)
758 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2)
759 /**
760 * @flags: Flags, currently a mask of memory instances of where BO can
761 * be placed
762 */
763 __u32 flags;
764
765 /**
766 * @vm_id: Attached VM, if any
767 *
768 * If a VM is specified, this BO must:
769 *
770 * 1. Only ever be bound to that VM.
771 * 2. Cannot be exported as a PRIME fd.
772 */
773 __u32 vm_id;
774
775 /**
776 * @handle: Returned handle for the object.
777 *
778 * Object handles are nonzero.
779 */
780 __u32 handle;
781
782 #define DRM_XE_GEM_CPU_CACHING_WB 1
783 #define DRM_XE_GEM_CPU_CACHING_WC 2
784 /**
785 * @cpu_caching: The CPU caching mode to select for this object. If
786 * mmaping the object the mode selected here will also be used. The
787 * exception is when mapping system memory (including data evicted
788 * to system) on discrete GPUs. The caching mode selected will
789 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency
790 * between GPU- and CPU is guaranteed. The caching mode of
791 * existing CPU-mappings will be updated transparently to
792 * user-space clients.
793 */
794 __u16 cpu_caching;
795 /** @pad: MBZ */
796 __u16 pad[3];
797
798 /** @reserved: Reserved */
799 __u64 reserved[2];
800 };
801
802 /**
803 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET
804 */
805 struct drm_xe_gem_mmap_offset {
806 /** @extensions: Pointer to the first extension struct, if any */
807 __u64 extensions;
808
809 /** @handle: Handle for the object being mapped. */
810 __u32 handle;
811
812 /** @flags: Must be zero */
813 __u32 flags;
814
815 /** @offset: The fake offset to use for subsequent mmap call */
816 __u64 offset;
817
818 /** @reserved: Reserved */
819 __u64 reserved[2];
820 };
821
822 /**
823 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
824 *
825 * The @flags can be:
826 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE
827 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
828 * exec submissions to its exec_queues that don't have an upper time
829 * limit on the job execution time. But exec submissions to these
830 * don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ,
831 * DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF,
832 * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL.
833 * LR VMs can be created in recoverable page-fault mode using
834 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it.
835 * If that flag is omitted, the UMD can not rely on the slightly
836 * different per-VM overcommit semantics that are enabled by
837 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may
838 * still enable recoverable pagefaults if supported by the device.
839 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also
840 * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on
841 * demand when accessed, and also allows per-VM overcommit of memory.
842 * The xe driver internally uses recoverable pagefaults to implement
843 * this.
844 */
845 struct drm_xe_vm_create {
846 /** @extensions: Pointer to the first extension struct, if any */
847 __u64 extensions;
848
849 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0)
850 #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1)
851 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2)
852 /** @flags: Flags */
853 __u32 flags;
854
855 /** @vm_id: Returned VM ID */
856 __u32 vm_id;
857
858 /** @reserved: Reserved */
859 __u64 reserved[2];
860 };
861
862 /**
863 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY
864 */
865 struct drm_xe_vm_destroy {
866 /** @vm_id: VM ID */
867 __u32 vm_id;
868
869 /** @pad: MBZ */
870 __u32 pad;
871
872 /** @reserved: Reserved */
873 __u64 reserved[2];
874 };
875
876 /**
877 * struct drm_xe_vm_bind_op - run bind operations
878 *
879 * The @op can be:
880 * - %DRM_XE_VM_BIND_OP_MAP
881 * - %DRM_XE_VM_BIND_OP_UNMAP
882 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR
883 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL
884 * - %DRM_XE_VM_BIND_OP_PREFETCH
885 *
886 * and the @flags can be:
887 * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only
888 * to ensure write protection
889 * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the
890 * MAP operation immediately rather than deferring the MAP to the page
891 * fault handler. This is implied on a non-faulting VM as there is no
892 * fault handler to defer to.
893 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page
894 * tables are setup with a special bit which indicates writes are
895 * dropped and all reads return zero. In the future, the NULL flags
896 * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
897 * handle MBZ, and the BO offset MBZ. This flag is intended to
898 * implement VK sparse bindings.
899 */
900 struct drm_xe_vm_bind_op {
901 /** @extensions: Pointer to the first extension struct, if any */
902 __u64 extensions;
903
904 /**
905 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP
906 */
907 __u32 obj;
908
909 /**
910 * @pat_index: The platform defined @pat_index to use for this mapping.
911 * The index basically maps to some predefined memory attributes,
912 * including things like caching, coherency, compression etc. The exact
913 * meaning of the pat_index is platform specific and defined in the
914 * Bspec and PRMs. When the KMD sets up the binding the index here is
915 * encoded into the ppGTT PTE.
916 *
917 * For coherency the @pat_index needs to be at least 1way coherent when
918 * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD
919 * will extract the coherency mode from the @pat_index and reject if
920 * there is a mismatch (see note below for pre-MTL platforms).
921 *
922 * Note: On pre-MTL platforms there is only a caching mode and no
923 * explicit coherency mode, but on such hardware there is always a
924 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with
925 * CPU caches even with the caching mode set as uncached. It's only the
926 * display engine that is incoherent (on dgpu it must be in VRAM which
927 * is always mapped as WC on the CPU). However to keep the uapi somewhat
928 * consistent with newer platforms the KMD groups the different cache
929 * levels into the following coherency buckets on all pre-MTL platforms:
930 *
931 * ppGTT UC -> COH_NONE
932 * ppGTT WC -> COH_NONE
933 * ppGTT WT -> COH_NONE
934 * ppGTT WB -> COH_AT_LEAST_1WAY
935 *
936 * In practice UC/WC/WT should only ever used for scanout surfaces on
937 * such platforms (or perhaps in general for dma-buf if shared with
938 * another device) since it is only the display engine that is actually
939 * incoherent. Everything else should typically use WB given that we
940 * have a shared-LLC. On MTL+ this completely changes and the HW
941 * defines the coherency mode as part of the @pat_index, where
942 * incoherent GT access is possible.
943 *
944 * Note: For userptr and externally imported dma-buf the kernel expects
945 * either 1WAY or 2WAY for the @pat_index.
946 *
947 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions
948 * on the @pat_index. For such mappings there is no actual memory being
949 * mapped (the address in the PTE is invalid), so the various PAT memory
950 * attributes likely do not apply. Simply leaving as zero is one
951 * option (still a valid pat_index).
952 */
953 __u16 pat_index;
954
955 /** @pad: MBZ */
956 __u16 pad;
957
958 union {
959 /**
960 * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE,
961 * ignored for unbind
962 */
963 __u64 obj_offset;
964
965 /** @userptr: user pointer to bind on */
966 __u64 userptr;
967 };
968
969 /**
970 * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL
971 */
972 __u64 range;
973
974 /** @addr: Address to operate on, MBZ for UNMAP_ALL */
975 __u64 addr;
976
977 #define DRM_XE_VM_BIND_OP_MAP 0x0
978 #define DRM_XE_VM_BIND_OP_UNMAP 0x1
979 #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2
980 #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3
981 #define DRM_XE_VM_BIND_OP_PREFETCH 0x4
982 /** @op: Bind operation to perform */
983 __u32 op;
984
985 #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0)
986 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1)
987 #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2)
988 #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3)
989 /** @flags: Bind flags */
990 __u32 flags;
991
992 /**
993 * @prefetch_mem_region_instance: Memory region to prefetch VMA to.
994 * It is a region instance, not a mask.
995 * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation.
996 */
997 __u32 prefetch_mem_region_instance;
998
999 /** @pad2: MBZ */
1000 __u32 pad2;
1001
1002 /** @reserved: Reserved */
1003 __u64 reserved[3];
1004 };
1005
1006 /**
1007 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND
1008 *
1009 * Below is an example of a minimal use of @drm_xe_vm_bind to
1010 * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to
1011 * illustrate `userptr`. It can be synchronized by using the example
1012 * provided for @drm_xe_sync.
1013 *
1014 * .. code-block:: C
1015 *
1016 * data = aligned_alloc(ALIGNMENT, BO_SIZE);
1017 * struct drm_xe_vm_bind bind = {
1018 * .vm_id = vm,
1019 * .num_binds = 1,
1020 * .bind.obj = 0,
1021 * .bind.obj_offset = to_user_pointer(data),
1022 * .bind.range = BO_SIZE,
1023 * .bind.addr = BIND_ADDRESS,
1024 * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR,
1025 * .bind.flags = 0,
1026 * .num_syncs = 1,
1027 * .syncs = &sync,
1028 * .exec_queue_id = 0,
1029 * };
1030 * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);
1031 *
1032 */
1033 struct drm_xe_vm_bind {
1034 /** @extensions: Pointer to the first extension struct, if any */
1035 __u64 extensions;
1036
1037 /** @vm_id: The ID of the VM to bind to */
1038 __u32 vm_id;
1039
1040 /**
1041 * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND
1042 * and exec queue must have same vm_id. If zero, the default VM bind engine
1043 * is used.
1044 */
1045 __u32 exec_queue_id;
1046
1047 /** @pad: MBZ */
1048 __u32 pad;
1049
1050 /** @num_binds: number of binds in this IOCTL */
1051 __u32 num_binds;
1052
1053 union {
1054 /** @bind: used if num_binds == 1 */
1055 struct drm_xe_vm_bind_op bind;
1056
1057 /**
1058 * @vector_of_binds: userptr to array of struct
1059 * drm_xe_vm_bind_op if num_binds > 1
1060 */
1061 __u64 vector_of_binds;
1062 };
1063
1064 /** @pad2: MBZ */
1065 __u32 pad2;
1066
1067 /** @num_syncs: amount of syncs to wait on */
1068 __u32 num_syncs;
1069
1070 /** @syncs: pointer to struct drm_xe_sync array */
1071 __u64 syncs;
1072
1073 /** @reserved: Reserved */
1074 __u64 reserved[2];
1075 };
1076
1077 /**
1078 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
1079 *
1080 * The example below shows how to use @drm_xe_exec_queue_create to create
1081 * a simple exec_queue (no parallel submission) of class
1082 * &DRM_XE_ENGINE_CLASS_RENDER.
1083 *
1084 * .. code-block:: C
1085 *
1086 * struct drm_xe_engine_class_instance instance = {
1087 * .engine_class = DRM_XE_ENGINE_CLASS_RENDER,
1088 * };
1089 * struct drm_xe_exec_queue_create exec_queue_create = {
1090 * .extensions = 0,
1091 * .vm_id = vm,
1092 * .num_bb_per_exec = 1,
1093 * .num_eng_per_bb = 1,
1094 * .instances = to_user_pointer(&instance),
1095 * };
1096 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
1097 *
1098 */
1099 struct drm_xe_exec_queue_create {
1100 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
1101 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
1102 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
1103
1104 /** @extensions: Pointer to the first extension struct, if any */
1105 __u64 extensions;
1106
1107 /** @width: submission width (number BB per exec) for this exec queue */
1108 __u16 width;
1109
1110 /** @num_placements: number of valid placements for this exec queue */
1111 __u16 num_placements;
1112
1113 /** @vm_id: VM to use for this exec queue */
1114 __u32 vm_id;
1115
1116 /** @flags: MBZ */
1117 __u32 flags;
1118
1119 /** @exec_queue_id: Returned exec queue ID */
1120 __u32 exec_queue_id;
1121
1122 /**
1123 * @instances: user pointer to a 2-d array of struct
1124 * drm_xe_engine_class_instance
1125 *
1126 * length = width (i) * num_placements (j)
1127 * index = j + i * width
1128 */
1129 __u64 instances;
1130
1131 /** @reserved: Reserved */
1132 __u64 reserved[2];
1133 };
1134
1135 /**
1136 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
1137 */
1138 struct drm_xe_exec_queue_destroy {
1139 /** @exec_queue_id: Exec queue ID */
1140 __u32 exec_queue_id;
1141
1142 /** @pad: MBZ */
1143 __u32 pad;
1144
1145 /** @reserved: Reserved */
1146 __u64 reserved[2];
1147 };
1148
1149 /**
1150 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
1151 *
1152 * The @property can be:
1153 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN
1154 */
1155 struct drm_xe_exec_queue_get_property {
1156 /** @extensions: Pointer to the first extension struct, if any */
1157 __u64 extensions;
1158
1159 /** @exec_queue_id: Exec queue ID */
1160 __u32 exec_queue_id;
1161
1162 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
1163 /** @property: property to get */
1164 __u32 property;
1165
1166 /** @value: property value */
1167 __u64 value;
1168
1169 /** @reserved: Reserved */
1170 __u64 reserved[2];
1171 };
1172
1173 /**
1174 * struct drm_xe_sync - sync object
1175 *
1176 * The @type can be:
1177 * - %DRM_XE_SYNC_TYPE_SYNCOBJ
1178 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ
1179 * - %DRM_XE_SYNC_TYPE_USER_FENCE
1180 *
1181 * and the @flags can be:
1182 * - %DRM_XE_SYNC_FLAG_SIGNAL
1183 *
1184 * A minimal use of @drm_xe_sync looks like this:
1185 *
1186 * .. code-block:: C
1187 *
1188 * struct drm_xe_sync sync = {
1189 * .flags = DRM_XE_SYNC_FLAG_SIGNAL,
1190 * .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
1191 * };
1192 * struct drm_syncobj_create syncobj_create = { 0 };
1193 * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create);
1194 * sync.handle = syncobj_create.handle;
1195 * ...
1196 * use of &sync in drm_xe_exec or drm_xe_vm_bind
1197 * ...
1198 * struct drm_syncobj_wait wait = {
1199 * .handles = &sync.handle,
1200 * .timeout_nsec = INT64_MAX,
1201 * .count_handles = 1,
1202 * .flags = 0,
1203 * .first_signaled = 0,
1204 * .pad = 0,
1205 * };
1206 * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
1207 */
1208 struct drm_xe_sync {
1209 /** @extensions: Pointer to the first extension struct, if any */
1210 __u64 extensions;
1211
1212 #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0
1213 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1
1214 #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2
1215 /** @type: Type of the this sync object */
1216 __u32 type;
1217
1218 #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0)
1219 /** @flags: Sync Flags */
1220 __u32 flags;
1221
1222 union {
1223 /** @handle: Handle for the object */
1224 __u32 handle;
1225
1226 /**
1227 * @addr: Address of user fence. When sync is passed in via exec
1228 * IOCTL this is a GPU address in the VM. When sync passed in via
1229 * VM bind IOCTL this is a user pointer. In either case, it is
1230 * the users responsibility that this address is present and
1231 * mapped when the user fence is signalled. Must be qword
1232 * aligned.
1233 */
1234 __u64 addr;
1235 };
1236
1237 /**
1238 * @timeline_value: Input for the timeline sync object. Needs to be
1239 * different than 0 when used with %DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ.
1240 */
1241 __u64 timeline_value;
1242
1243 /** @reserved: Reserved */
1244 __u64 reserved[2];
1245 };
1246
1247 /**
1248 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC
1249 *
1250 * This is an example to use @drm_xe_exec for execution of the object
1251 * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue
1252 * (see example in @drm_xe_exec_queue_create). It can be synchronized
1253 * by using the example provided for @drm_xe_sync.
1254 *
1255 * .. code-block:: C
1256 *
1257 * struct drm_xe_exec exec = {
1258 * .exec_queue_id = exec_queue,
1259 * .syncs = &sync,
1260 * .num_syncs = 1,
1261 * .address = BIND_ADDRESS,
1262 * .num_batch_buffer = 1,
1263 * };
1264 * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);
1265 *
1266 */
1267 struct drm_xe_exec {
1268 /** @extensions: Pointer to the first extension struct, if any */
1269 __u64 extensions;
1270
1271 /** @exec_queue_id: Exec queue ID for the batch buffer */
1272 __u32 exec_queue_id;
1273
1274 /** @num_syncs: Amount of struct drm_xe_sync in array. */
1275 __u32 num_syncs;
1276
1277 /** @syncs: Pointer to struct drm_xe_sync array. */
1278 __u64 syncs;
1279
1280 /**
1281 * @address: address of batch buffer if num_batch_buffer == 1 or an
1282 * array of batch buffer addresses
1283 */
1284 __u64 address;
1285
1286 /**
1287 * @num_batch_buffer: number of batch buffer in this exec, must match
1288 * the width of the engine
1289 */
1290 __u16 num_batch_buffer;
1291
1292 /** @pad: MBZ */
1293 __u16 pad[3];
1294
1295 /** @reserved: Reserved */
1296 __u64 reserved[2];
1297 };
1298
1299 /**
1300 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE
1301 *
1302 * Wait on user fence, XE will wake-up on every HW engine interrupt in the
1303 * instances list and check if user fence is complete::
1304 *
1305 * (*addr & MASK) OP (VALUE & MASK)
1306 *
1307 * Returns to user on user fence completion or timeout.
1308 *
1309 * The @op can be:
1310 * - %DRM_XE_UFENCE_WAIT_OP_EQ
1311 * - %DRM_XE_UFENCE_WAIT_OP_NEQ
1312 * - %DRM_XE_UFENCE_WAIT_OP_GT
1313 * - %DRM_XE_UFENCE_WAIT_OP_GTE
1314 * - %DRM_XE_UFENCE_WAIT_OP_LT
1315 * - %DRM_XE_UFENCE_WAIT_OP_LTE
1316 *
1317 * and the @flags can be:
1318 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
1319 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP
1320 *
1321 * The @mask values can be for example:
1322 * - 0xffu for u8
1323 * - 0xffffu for u16
1324 * - 0xffffffffu for u32
1325 * - 0xffffffffffffffffu for u64
1326 */
1327 struct drm_xe_wait_user_fence {
1328 /** @extensions: Pointer to the first extension struct, if any */
1329 __u64 extensions;
1330
1331 /**
1332 * @addr: user pointer address to wait on, must qword aligned
1333 */
1334 __u64 addr;
1335
1336 #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0
1337 #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1
1338 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2
1339 #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3
1340 #define DRM_XE_UFENCE_WAIT_OP_LT 0x4
1341 #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5
1342 /** @op: wait operation (type of comparison) */
1343 __u16 op;
1344
1345 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0)
1346 /** @flags: wait flags */
1347 __u16 flags;
1348
1349 /** @pad: MBZ */
1350 __u32 pad;
1351
1352 /** @value: compare value */
1353 __u64 value;
1354
1355 /** @mask: comparison mask */
1356 __u64 mask;
1357
1358 /**
1359 * @timeout: how long to wait before bailing, value in nanoseconds.
1360 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout)
1361 * it contains timeout expressed in nanoseconds to wait (fence will
1362 * expire at now() + timeout).
1363 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait
1364 * will end at timeout (uses system MONOTONIC_CLOCK).
1365 * Passing negative timeout leads to neverending wait.
1366 *
1367 * On relative timeout this value is updated with timeout left
1368 * (for restarting the call in case of signal delivery).
1369 * On absolute timeout this value stays intact (restarted call still
1370 * expire at the same point of time).
1371 */
1372 __s64 timeout;
1373
1374 /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */
1375 __u32 exec_queue_id;
1376
1377 /** @pad2: MBZ */
1378 __u32 pad2;
1379
1380 /** @reserved: Reserved */
1381 __u64 reserved[2];
1382 };
1383
1384 /**
1385 * enum drm_xe_observation_type - Observation stream types
1386 */
1387 enum drm_xe_observation_type {
1388 /** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */
1389 DRM_XE_OBSERVATION_TYPE_OA,
1390 };
1391
1392 /**
1393 * enum drm_xe_observation_op - Observation stream ops
1394 */
1395 enum drm_xe_observation_op {
1396 /** @DRM_XE_OBSERVATION_OP_STREAM_OPEN: Open an observation stream */
1397 DRM_XE_OBSERVATION_OP_STREAM_OPEN,
1398
1399 /** @DRM_XE_OBSERVATION_OP_ADD_CONFIG: Add observation stream config */
1400 DRM_XE_OBSERVATION_OP_ADD_CONFIG,
1401
1402 /** @DRM_XE_OBSERVATION_OP_REMOVE_CONFIG: Remove observation stream config */
1403 DRM_XE_OBSERVATION_OP_REMOVE_CONFIG,
1404 };
1405
1406 /**
1407 * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION
1408 *
1409 * The observation layer enables multiplexing observation streams of
1410 * multiple types. The actual params for a particular stream operation are
1411 * supplied via the @param pointer (use __copy_from_user to get these
1412 * params).
1413 */
1414 struct drm_xe_observation_param {
1415 /** @extensions: Pointer to the first extension struct, if any */
1416 __u64 extensions;
1417 /** @observation_type: observation stream type, of enum @drm_xe_observation_type */
1418 __u64 observation_type;
1419 /** @observation_op: observation stream op, of enum @drm_xe_observation_op */
1420 __u64 observation_op;
1421 /** @param: Pointer to actual stream params */
1422 __u64 param;
1423 };
1424
1425 /**
1426 * enum drm_xe_observation_ioctls - Observation stream fd ioctl's
1427 *
1428 * Information exchanged between userspace and kernel for observation fd
1429 * ioctl's is stream type specific
1430 */
1431 enum drm_xe_observation_ioctls {
1432 /** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */
1433 DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0),
1434
1435 /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */
1436 DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1),
1437
1438 /** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */
1439 DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2),
1440
1441 /** @DRM_XE_OBSERVATION_IOCTL_STATUS: Return observation stream status */
1442 DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3),
1443
1444 /** @DRM_XE_OBSERVATION_IOCTL_INFO: Return observation stream info */
1445 DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4),
1446 };
1447
1448 /**
1449 * enum drm_xe_oa_unit_type - OA unit types
1450 */
1451 enum drm_xe_oa_unit_type {
1452 /**
1453 * @DRM_XE_OA_UNIT_TYPE_OAG: OAG OA unit. OAR/OAC are considered
1454 * sub-types of OAG. For OAR/OAC, use OAG.
1455 */
1456 DRM_XE_OA_UNIT_TYPE_OAG,
1457
1458 /** @DRM_XE_OA_UNIT_TYPE_OAM: OAM OA unit */
1459 DRM_XE_OA_UNIT_TYPE_OAM,
1460 };
1461
1462 /**
1463 * struct drm_xe_oa_unit - describe OA unit
1464 */
1465 struct drm_xe_oa_unit {
1466 /** @extensions: Pointer to the first extension struct, if any */
1467 __u64 extensions;
1468
1469 /** @oa_unit_id: OA unit ID */
1470 __u32 oa_unit_id;
1471
1472 /** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */
1473 __u32 oa_unit_type;
1474
1475 /** @capabilities: OA capabilities bit-mask */
1476 __u64 capabilities;
1477 #define DRM_XE_OA_CAPS_BASE (1 << 0)
1478
1479 /** @oa_timestamp_freq: OA timestamp freq */
1480 __u64 oa_timestamp_freq;
1481
1482 /** @reserved: MBZ */
1483 __u64 reserved[4];
1484
1485 /** @num_engines: number of engines in @eci array */
1486 __u64 num_engines;
1487
1488 /** @eci: engines attached to this OA unit */
1489 struct drm_xe_engine_class_instance eci[];
1490 };
1491
1492 /**
1493 * struct drm_xe_query_oa_units - describe OA units
1494 *
1495 * If a query is made with a struct drm_xe_device_query where .query
1496 * is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct
1497 * drm_xe_query_oa_units in .data.
1498 *
1499 * OA unit properties for all OA units can be accessed using a code block
1500 * such as the one below:
1501 *
1502 * .. code-block:: C
1503 *
1504 * struct drm_xe_query_oa_units *qoa;
1505 * struct drm_xe_oa_unit *oau;
1506 * u8 *poau;
1507 *
1508 * // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then:
1509 * poau = (u8 *)&qoa->oa_units[0];
1510 * for (int i = 0; i < qoa->num_oa_units; i++) {
1511 * oau = (struct drm_xe_oa_unit *)poau;
1512 * // Access 'struct drm_xe_oa_unit' fields here
1513 * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
1514 * }
1515 */
1516 struct drm_xe_query_oa_units {
1517 /** @extensions: Pointer to the first extension struct, if any */
1518 __u64 extensions;
1519 /** @num_oa_units: number of OA units returned in oau[] */
1520 __u32 num_oa_units;
1521 /** @pad: MBZ */
1522 __u32 pad;
1523 /**
1524 * @oa_units: struct @drm_xe_oa_unit array returned for this device.
1525 * Written below as a u64 array to avoid problems with nested flexible
1526 * arrays with some compilers
1527 */
1528 __u64 oa_units[];
1529 };
1530
1531 /**
1532 * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec
1533 * 52198/60942
1534 */
1535 enum drm_xe_oa_format_type {
1536 /** @DRM_XE_OA_FMT_TYPE_OAG: OAG report format */
1537 DRM_XE_OA_FMT_TYPE_OAG,
1538 /** @DRM_XE_OA_FMT_TYPE_OAR: OAR report format */
1539 DRM_XE_OA_FMT_TYPE_OAR,
1540 /** @DRM_XE_OA_FMT_TYPE_OAM: OAM report format */
1541 DRM_XE_OA_FMT_TYPE_OAM,
1542 /** @DRM_XE_OA_FMT_TYPE_OAC: OAC report format */
1543 DRM_XE_OA_FMT_TYPE_OAC,
1544 /** @DRM_XE_OA_FMT_TYPE_OAM_MPEC: OAM SAMEDIA or OAM MPEC report format */
1545 DRM_XE_OA_FMT_TYPE_OAM_MPEC,
1546 /** @DRM_XE_OA_FMT_TYPE_PEC: PEC report format */
1547 DRM_XE_OA_FMT_TYPE_PEC,
1548 };
1549
1550 /**
1551 * enum drm_xe_oa_property_id - OA stream property id's
1552 *
1553 * Stream params are specified as a chain of @drm_xe_ext_set_property
1554 * struct's, with @property values from enum @drm_xe_oa_property_id and
1555 * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY.
1556 * @param field in struct @drm_xe_observation_param points to the first
1557 * @drm_xe_ext_set_property struct.
1558 *
1559 * Exactly the same mechanism is also used for stream reconfiguration using the
1560 * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a
1561 * subset of properties below can be specified for stream reconfiguration.
1562 */
1563 enum drm_xe_oa_property_id {
1564 #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0
1565 /**
1566 * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open
1567 * the OA stream, see @oa_unit_id in 'struct
1568 * drm_xe_query_oa_units'. Defaults to 0 if not provided.
1569 */
1570 DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1,
1571
1572 /**
1573 * @DRM_XE_OA_PROPERTY_SAMPLE_OA: A value of 1 requests inclusion of raw
1574 * OA unit reports or stream samples in a global buffer attached to an
1575 * OA unit.
1576 */
1577 DRM_XE_OA_PROPERTY_SAMPLE_OA,
1578
1579 /**
1580 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA
1581 * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG.
1582 */
1583 DRM_XE_OA_PROPERTY_OA_METRIC_SET,
1584
1585 /** @DRM_XE_OA_PROPERTY_OA_FORMAT: OA counter report format */
1586 DRM_XE_OA_PROPERTY_OA_FORMAT,
1587 /*
1588 * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942,
1589 * in terms of the following quantities: a. enum @drm_xe_oa_format_type
1590 * b. Counter select c. Counter size and d. BC report. Also refer to the
1591 * oa_formats array in drivers/gpu/drm/xe/xe_oa.c.
1592 */
1593 #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xff << 0)
1594 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xff << 8)
1595 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xff << 16)
1596 #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xff << 24)
1597
1598 /**
1599 * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit
1600 * sampling with sampling frequency proportional to 2^(period_exponent + 1)
1601 */
1602 DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT,
1603
1604 /**
1605 * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA
1606 * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE).
1607 */
1608 DRM_XE_OA_PROPERTY_OA_DISABLED,
1609
1610 /**
1611 * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific
1612 * @exec_queue_id. OA queries can be executed on this exec queue.
1613 */
1614 DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID,
1615
1616 /**
1617 * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to
1618 * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0.
1619 */
1620 DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE,
1621
1622 /**
1623 * @DRM_XE_OA_PROPERTY_NO_PREEMPT: Allow preemption and timeslicing
1624 * to be disabled for the stream exec queue.
1625 */
1626 DRM_XE_OA_PROPERTY_NO_PREEMPT,
1627 };
1628
1629 /**
1630 * struct drm_xe_oa_config - OA metric configuration
1631 *
1632 * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A
1633 * particular config can be specified when opening an OA stream using
1634 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property.
1635 */
1636 struct drm_xe_oa_config {
1637 /** @extensions: Pointer to the first extension struct, if any */
1638 __u64 extensions;
1639
1640 /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */
1641 char uuid[36];
1642
1643 /** @n_regs: Number of regs in @regs_ptr */
1644 __u32 n_regs;
1645
1646 /**
1647 * @regs_ptr: Pointer to (register address, value) pairs for OA config
1648 * registers. Expected length of buffer is: (2 * sizeof(u32) * @n_regs).
1649 */
1650 __u64 regs_ptr;
1651 };
1652
1653 /**
1654 * struct drm_xe_oa_stream_status - OA stream status returned from
1655 * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can
1656 * call the ioctl to query stream status in response to EIO errno from
1657 * observation fd read().
1658 */
1659 struct drm_xe_oa_stream_status {
1660 /** @extensions: Pointer to the first extension struct, if any */
1661 __u64 extensions;
1662
1663 /** @oa_status: OA stream status (see Bspec 46717/61226) */
1664 __u64 oa_status;
1665 #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3)
1666 #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2)
1667 #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1)
1668 #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0)
1669
1670 /** @reserved: reserved for future use */
1671 __u64 reserved[3];
1672 };
1673
1674 /**
1675 * struct drm_xe_oa_stream_info - OA stream info returned from
1676 * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl
1677 */
1678 struct drm_xe_oa_stream_info {
1679 /** @extensions: Pointer to the first extension struct, if any */
1680 __u64 extensions;
1681
1682 /** @oa_buf_size: OA buffer size */
1683 __u64 oa_buf_size;
1684
1685 /** @reserved: reserved for future use */
1686 __u64 reserved[3];
1687 };
1688
1689 #if defined(__cplusplus)
1690 }
1691 #endif
1692
1693 #endif /* _UAPI_XE_DRM_H_ */
1694
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