1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12 #ifndef _UFSHCD_H
13 #define _UFSHCD_H
14
15 #include <linux/bitfield.h>
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
18 #include <linux/devfreq.h>
19 #include <linux/fault-inject.h>
20 #include <linux/msi.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/dma-direction.h>
23 #include <scsi/scsi_device.h>
24 #include <scsi/scsi_host.h>
25 #include <ufs/unipro.h>
26 #include <ufs/ufs.h>
27 #include <ufs/ufs_quirks.h>
28 #include <ufs/ufshci.h>
29
30 #define UFSHCD "ufshcd"
31
32 struct scsi_device;
33 struct ufs_hba;
34
35 enum dev_cmd_type {
36 DEV_CMD_TYPE_NOP = 0x0,
37 DEV_CMD_TYPE_QUERY = 0x1,
38 DEV_CMD_TYPE_RPMB = 0x2,
39 };
40
41 enum ufs_event_type {
42 /* uic specific errors */
43 UFS_EVT_PA_ERR = 0,
44 UFS_EVT_DL_ERR,
45 UFS_EVT_NL_ERR,
46 UFS_EVT_TL_ERR,
47 UFS_EVT_DME_ERR,
48
49 /* fatal errors */
50 UFS_EVT_AUTO_HIBERN8_ERR,
51 UFS_EVT_FATAL_ERR,
52 UFS_EVT_LINK_STARTUP_FAIL,
53 UFS_EVT_RESUME_ERR,
54 UFS_EVT_SUSPEND_ERR,
55 UFS_EVT_WL_SUSP_ERR,
56 UFS_EVT_WL_RES_ERR,
57
58 /* abnormal events */
59 UFS_EVT_DEV_RESET,
60 UFS_EVT_HOST_RESET,
61 UFS_EVT_ABORT,
62
63 UFS_EVT_CNT,
64 };
65
66 /**
67 * struct uic_command - UIC command structure
68 * @command: UIC command
69 * @argument1: UIC command argument 1
70 * @argument2: UIC command argument 2
71 * @argument3: UIC command argument 3
72 * @cmd_active: Indicate if UIC command is outstanding
73 * @done: UIC command completion
74 */
75 struct uic_command {
76 const u32 command;
77 const u32 argument1;
78 u32 argument2;
79 u32 argument3;
80 int cmd_active;
81 struct completion done;
82 };
83
84 /* Used to differentiate the power management options */
85 enum ufs_pm_op {
86 UFS_RUNTIME_PM,
87 UFS_SYSTEM_PM,
88 UFS_SHUTDOWN_PM,
89 };
90
91 /* Host <-> Device UniPro Link state */
92 enum uic_link_state {
93 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
94 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
95 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
96 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */
97 };
98
99 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
100 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
101 UIC_LINK_ACTIVE_STATE)
102 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
103 UIC_LINK_HIBERN8_STATE)
104 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
105 UIC_LINK_BROKEN_STATE)
106 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
107 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
108 UIC_LINK_ACTIVE_STATE)
109 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
110 UIC_LINK_HIBERN8_STATE)
111 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
112 UIC_LINK_BROKEN_STATE)
113
114 #define ufshcd_set_ufs_dev_active(h) \
115 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
116 #define ufshcd_set_ufs_dev_sleep(h) \
117 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
118 #define ufshcd_set_ufs_dev_poweroff(h) \
119 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
120 #define ufshcd_set_ufs_dev_deepsleep(h) \
121 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
122 #define ufshcd_is_ufs_dev_active(h) \
123 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
124 #define ufshcd_is_ufs_dev_sleep(h) \
125 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
126 #define ufshcd_is_ufs_dev_poweroff(h) \
127 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
128 #define ufshcd_is_ufs_dev_deepsleep(h) \
129 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
130
131 /*
132 * UFS Power management levels.
133 * Each level is in increasing order of power savings, except DeepSleep
134 * which is lower than PowerDown with power on but not PowerDown with
135 * power off.
136 */
137 enum ufs_pm_level {
138 UFS_PM_LVL_0,
139 UFS_PM_LVL_1,
140 UFS_PM_LVL_2,
141 UFS_PM_LVL_3,
142 UFS_PM_LVL_4,
143 UFS_PM_LVL_5,
144 UFS_PM_LVL_6,
145 UFS_PM_LVL_MAX
146 };
147
148 struct ufs_pm_lvl_states {
149 enum ufs_dev_pwr_mode dev_state;
150 enum uic_link_state link_state;
151 };
152
153 /**
154 * struct ufshcd_lrb - local reference block
155 * @utr_descriptor_ptr: UTRD address of the command
156 * @ucd_req_ptr: UCD address of the command
157 * @ucd_rsp_ptr: Response UPIU address for this command
158 * @ucd_prdt_ptr: PRDT address of the command
159 * @utrd_dma_addr: UTRD dma address for debug
160 * @ucd_prdt_dma_addr: PRDT dma address for debug
161 * @ucd_rsp_dma_addr: UPIU response dma address for debug
162 * @ucd_req_dma_addr: UPIU request dma address for debug
163 * @cmd: pointer to SCSI command
164 * @scsi_status: SCSI status of the command
165 * @command_type: SCSI, UFS, Query.
166 * @task_tag: Task tag of the command
167 * @lun: LUN of the command
168 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
169 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
170 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
171 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
172 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
173 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
174 * @data_unit_num: the data unit number for the first block for inline crypto
175 * @req_abort_skip: skip request abort task flag
176 */
177 struct ufshcd_lrb {
178 struct utp_transfer_req_desc *utr_descriptor_ptr;
179 struct utp_upiu_req *ucd_req_ptr;
180 struct utp_upiu_rsp *ucd_rsp_ptr;
181 struct ufshcd_sg_entry *ucd_prdt_ptr;
182
183 dma_addr_t utrd_dma_addr;
184 dma_addr_t ucd_req_dma_addr;
185 dma_addr_t ucd_rsp_dma_addr;
186 dma_addr_t ucd_prdt_dma_addr;
187
188 struct scsi_cmnd *cmd;
189 int scsi_status;
190
191 int command_type;
192 int task_tag;
193 u8 lun; /* UPIU LUN id field is only 8-bit wide */
194 bool intr_cmd;
195 ktime_t issue_time_stamp;
196 u64 issue_time_stamp_local_clock;
197 ktime_t compl_time_stamp;
198 u64 compl_time_stamp_local_clock;
199 #ifdef CONFIG_SCSI_UFS_CRYPTO
200 int crypto_key_slot;
201 u64 data_unit_num;
202 #endif
203
204 bool req_abort_skip;
205 };
206
207 /**
208 * struct ufs_query_req - parameters for building a query request
209 * @query_func: UPIU header query function
210 * @upiu_req: the query request data
211 */
212 struct ufs_query_req {
213 u8 query_func;
214 struct utp_upiu_query upiu_req;
215 };
216
217 /**
218 * struct ufs_query_resp - UPIU QUERY
219 * @response: device response code
220 * @upiu_res: query response data
221 */
222 struct ufs_query_res {
223 struct utp_upiu_query upiu_res;
224 };
225
226 /**
227 * struct ufs_query - holds relevant data structures for query request
228 * @request: request upiu and function
229 * @descriptor: buffer for sending/receiving descriptor
230 * @response: response upiu and response
231 */
232 struct ufs_query {
233 struct ufs_query_req request;
234 u8 *descriptor;
235 struct ufs_query_res response;
236 };
237
238 /**
239 * struct ufs_dev_cmd - all assosiated fields with device management commands
240 * @type: device management command type - Query, NOP OUT
241 * @lock: lock to allow one command at a time
242 * @complete: internal commands completion
243 * @query: Device management query information
244 */
245 struct ufs_dev_cmd {
246 enum dev_cmd_type type;
247 struct mutex lock;
248 struct completion *complete;
249 struct ufs_query query;
250 };
251
252 /**
253 * struct ufs_clk_info - UFS clock related info
254 * @list: list headed by hba->clk_list_head
255 * @clk: clock node
256 * @name: clock name
257 * @max_freq: maximum frequency supported by the clock
258 * @min_freq: min frequency that can be used for clock scaling
259 * @curr_freq: indicates the current frequency that it is set to
260 * @keep_link_active: indicates that the clk should not be disabled if
261 * link is active
262 * @enabled: variable to check against multiple enable/disable
263 */
264 struct ufs_clk_info {
265 struct list_head list;
266 struct clk *clk;
267 const char *name;
268 u32 max_freq;
269 u32 min_freq;
270 u32 curr_freq;
271 bool keep_link_active;
272 bool enabled;
273 };
274
275 enum ufs_notify_change_status {
276 PRE_CHANGE,
277 POST_CHANGE,
278 };
279
280 struct ufs_pa_layer_attr {
281 u32 gear_rx;
282 u32 gear_tx;
283 u32 lane_rx;
284 u32 lane_tx;
285 u32 pwr_rx;
286 u32 pwr_tx;
287 u32 hs_rate;
288 };
289
290 struct ufs_pwr_mode_info {
291 bool is_valid;
292 struct ufs_pa_layer_attr info;
293 };
294
295 /**
296 * struct ufs_hba_variant_ops - variant specific callbacks
297 * @name: variant name
298 * @max_num_rtt: maximum RTT supported by the host
299 * @init: called when the driver is initialized
300 * @exit: called to cleanup everything done in init
301 * @get_ufs_hci_version: called to get UFS HCI version
302 * @clk_scale_notify: notifies that clks are scaled up/down
303 * @setup_clocks: called before touching any of the controller registers
304 * @hce_enable_notify: called before and after HCE enable bit is set to allow
305 * variant specific Uni-Pro initialization.
306 * @link_startup_notify: called before and after Link startup is carried out
307 * to allow variant specific Uni-Pro initialization.
308 * @pwr_change_notify: called before and after a power mode change
309 * is carried out to allow vendor spesific capabilities
310 * to be set.
311 * @setup_xfer_req: called before any transfer request is issued
312 * to set some things
313 * @setup_task_mgmt: called before any task management request is issued
314 * to set some things
315 * @hibern8_notify: called around hibern8 enter/exit
316 * @apply_dev_quirks: called to apply device specific quirks
317 * @fixup_dev_quirks: called to modify device specific quirks
318 * @suspend: called during host controller PM callback
319 * @resume: called during host controller PM callback
320 * @dbg_register_dump: used to dump controller debug information
321 * @phy_initialization: used to initialize phys
322 * @device_reset: called to issue a reset pulse on the UFS device
323 * @config_scaling_param: called to configure clock scaling parameters
324 * @program_key: program or evict an inline encryption key
325 * @fill_crypto_prdt: initialize crypto-related fields in the PRDT
326 * @event_notify: called to notify important events
327 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch
328 * @mcq_config_resource: called to configure MCQ platform resources
329 * @get_hba_mac: reports maximum number of outstanding commands supported by
330 * the controller. Should be implemented for UFSHCI 4.0 or later
331 * controllers that are not compliant with the UFSHCI 4.0 specification.
332 * @op_runtime_config: called to config Operation and runtime regs Pointers
333 * @get_outstanding_cqs: called to get outstanding completion queues
334 * @config_esi: called to config Event Specific Interrupt
335 * @config_scsi_dev: called to configure SCSI device parameters
336 */
337 struct ufs_hba_variant_ops {
338 const char *name;
339 int max_num_rtt;
340 int (*init)(struct ufs_hba *);
341 void (*exit)(struct ufs_hba *);
342 u32 (*get_ufs_hci_version)(struct ufs_hba *);
343 int (*clk_scale_notify)(struct ufs_hba *, bool,
344 enum ufs_notify_change_status);
345 int (*setup_clocks)(struct ufs_hba *, bool,
346 enum ufs_notify_change_status);
347 int (*hce_enable_notify)(struct ufs_hba *,
348 enum ufs_notify_change_status);
349 int (*link_startup_notify)(struct ufs_hba *,
350 enum ufs_notify_change_status);
351 int (*pwr_change_notify)(struct ufs_hba *,
352 enum ufs_notify_change_status status,
353 struct ufs_pa_layer_attr *,
354 struct ufs_pa_layer_attr *);
355 void (*setup_xfer_req)(struct ufs_hba *hba, int tag,
356 bool is_scsi_cmd);
357 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
358 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
359 enum ufs_notify_change_status);
360 int (*apply_dev_quirks)(struct ufs_hba *hba);
361 void (*fixup_dev_quirks)(struct ufs_hba *hba);
362 int (*suspend)(struct ufs_hba *, enum ufs_pm_op,
363 enum ufs_notify_change_status);
364 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
365 void (*dbg_register_dump)(struct ufs_hba *hba);
366 int (*phy_initialization)(struct ufs_hba *);
367 int (*device_reset)(struct ufs_hba *hba);
368 void (*config_scaling_param)(struct ufs_hba *hba,
369 struct devfreq_dev_profile *profile,
370 struct devfreq_simple_ondemand_data *data);
371 int (*program_key)(struct ufs_hba *hba,
372 const union ufs_crypto_cfg_entry *cfg, int slot);
373 int (*fill_crypto_prdt)(struct ufs_hba *hba,
374 const struct bio_crypt_ctx *crypt_ctx,
375 void *prdt, unsigned int num_segments);
376 void (*event_notify)(struct ufs_hba *hba,
377 enum ufs_event_type evt, void *data);
378 void (*reinit_notify)(struct ufs_hba *);
379 int (*mcq_config_resource)(struct ufs_hba *hba);
380 int (*get_hba_mac)(struct ufs_hba *hba);
381 int (*op_runtime_config)(struct ufs_hba *hba);
382 int (*get_outstanding_cqs)(struct ufs_hba *hba,
383 unsigned long *ocqs);
384 int (*config_esi)(struct ufs_hba *hba);
385 };
386
387 /* clock gating state */
388 enum clk_gating_state {
389 CLKS_OFF,
390 CLKS_ON,
391 REQ_CLKS_OFF,
392 REQ_CLKS_ON,
393 };
394
395 /**
396 * struct ufs_clk_gating - UFS clock gating related info
397 * @gate_work: worker to turn off clocks after some delay as specified in
398 * delay_ms
399 * @ungate_work: worker to turn on clocks that will be used in case of
400 * interrupt context
401 * @state: the current clocks state
402 * @delay_ms: gating delay in ms
403 * @is_suspended: clk gating is suspended when set to 1 which can be used
404 * during suspend/resume
405 * @delay_attr: sysfs attribute to control delay_attr
406 * @enable_attr: sysfs attribute to enable/disable clock gating
407 * @is_enabled: Indicates the current status of clock gating
408 * @is_initialized: Indicates whether clock gating is initialized or not
409 * @active_reqs: number of requests that are pending and should be waited for
410 * completion before gating clocks.
411 * @clk_gating_workq: workqueue for clock gating work.
412 */
413 struct ufs_clk_gating {
414 struct delayed_work gate_work;
415 struct work_struct ungate_work;
416 enum clk_gating_state state;
417 unsigned long delay_ms;
418 bool is_suspended;
419 struct device_attribute delay_attr;
420 struct device_attribute enable_attr;
421 bool is_enabled;
422 bool is_initialized;
423 int active_reqs;
424 struct workqueue_struct *clk_gating_workq;
425 };
426
427 /**
428 * struct ufs_clk_scaling - UFS clock scaling related data
429 * @active_reqs: number of requests that are pending. If this is zero when
430 * devfreq ->target() function is called then schedule "suspend_work" to
431 * suspend devfreq.
432 * @tot_busy_t: Total busy time in current polling window
433 * @window_start_t: Start time (in jiffies) of the current polling window
434 * @busy_start_t: Start time of current busy period
435 * @enable_attr: sysfs attribute to enable/disable clock scaling
436 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
437 * one keeps track of previous power mode.
438 * @workq: workqueue to schedule devfreq suspend/resume work
439 * @suspend_work: worker to suspend devfreq
440 * @resume_work: worker to resume devfreq
441 * @target_freq: frequency requested by devfreq framework
442 * @min_gear: lowest HS gear to scale down to
443 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
444 * clkscale_enable sysfs node
445 * @is_allowed: tracks if scaling is currently allowed or not, used to block
446 * clock scaling which is not invoked from devfreq governor
447 * @is_initialized: Indicates whether clock scaling is initialized or not
448 * @is_busy_started: tracks if busy period has started or not
449 * @is_suspended: tracks if devfreq is suspended or not
450 */
451 struct ufs_clk_scaling {
452 int active_reqs;
453 unsigned long tot_busy_t;
454 ktime_t window_start_t;
455 ktime_t busy_start_t;
456 struct device_attribute enable_attr;
457 struct ufs_pa_layer_attr saved_pwr_info;
458 struct workqueue_struct *workq;
459 struct work_struct suspend_work;
460 struct work_struct resume_work;
461 unsigned long target_freq;
462 u32 min_gear;
463 bool is_enabled;
464 bool is_allowed;
465 bool is_initialized;
466 bool is_busy_started;
467 bool is_suspended;
468 bool suspend_on_no_request;
469 };
470
471 #define UFS_EVENT_HIST_LENGTH 8
472 /**
473 * struct ufs_event_hist - keeps history of errors
474 * @pos: index to indicate cyclic buffer position
475 * @val: cyclic buffer for registers value
476 * @tstamp: cyclic buffer for time stamp
477 * @cnt: error counter
478 */
479 struct ufs_event_hist {
480 int pos;
481 u32 val[UFS_EVENT_HIST_LENGTH];
482 u64 tstamp[UFS_EVENT_HIST_LENGTH];
483 unsigned long long cnt;
484 };
485
486 /**
487 * struct ufs_stats - keeps usage/err statistics
488 * @last_intr_status: record the last interrupt status.
489 * @last_intr_ts: record the last interrupt timestamp.
490 * @hibern8_exit_cnt: Counter to keep track of number of exits,
491 * reset this after link-startup.
492 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
493 * Clear after the first successful command completion.
494 * @event: array with event history.
495 */
496 struct ufs_stats {
497 u32 last_intr_status;
498 u64 last_intr_ts;
499
500 u32 hibern8_exit_cnt;
501 u64 last_hibern8_exit_tstamp;
502 struct ufs_event_hist event[UFS_EVT_CNT];
503 };
504
505 /**
506 * enum ufshcd_state - UFS host controller state
507 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
508 * processing.
509 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
510 * SCSI commands.
511 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
512 * SCSI commands may be submitted to the controller.
513 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
514 * newly submitted SCSI commands with error code DID_BAD_TARGET.
515 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
516 * failed. Fail all SCSI commands with error code DID_ERROR.
517 */
518 enum ufshcd_state {
519 UFSHCD_STATE_RESET,
520 UFSHCD_STATE_OPERATIONAL,
521 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
522 UFSHCD_STATE_EH_SCHEDULED_FATAL,
523 UFSHCD_STATE_ERROR,
524 };
525
526 enum ufshcd_quirks {
527 /* Interrupt aggregation support is broken */
528 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
529
530 /*
531 * delay before each dme command is required as the unipro
532 * layer has shown instabilities
533 */
534 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
535
536 /*
537 * If UFS host controller is having issue in processing LCC (Line
538 * Control Command) coming from device then enable this quirk.
539 * When this quirk is enabled, host controller driver should disable
540 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
541 * attribute of device to 0).
542 */
543 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
544
545 /*
546 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
547 * inbound Link supports unterminated line in HS mode. Setting this
548 * attribute to 1 fixes moving to HS gear.
549 */
550 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
551
552 /*
553 * This quirk needs to be enabled if the host controller only allows
554 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
555 * SLOW AUTO).
556 */
557 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
558
559 /*
560 * This quirk needs to be enabled if the host controller doesn't
561 * advertise the correct version in UFS_VER register. If this quirk
562 * is enabled, standard UFS host driver will call the vendor specific
563 * ops (get_ufs_hci_version) to get the correct version.
564 */
565 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
566
567 /*
568 * Clear handling for transfer/task request list is just opposite.
569 */
570 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
571
572 /*
573 * This quirk needs to be enabled if host controller doesn't allow
574 * that the interrupt aggregation timer and counter are reset by s/w.
575 */
576 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
577
578 /*
579 * This quirks needs to be enabled if host controller cannot be
580 * enabled via HCE register.
581 */
582 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
583
584 /*
585 * This quirk needs to be enabled if the host controller regards
586 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
587 */
588 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
589
590 /*
591 * This quirk needs to be enabled if the host controller reports
592 * OCS FATAL ERROR with device error through sense data
593 */
594 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
595
596 /*
597 * This quirk needs to be enabled if the host controller has
598 * auto-hibernate capability but it doesn't work.
599 */
600 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
601
602 /*
603 * This quirk needs to disable manual flush for write booster
604 */
605 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
606
607 /*
608 * This quirk needs to disable unipro timeout values
609 * before power mode change
610 */
611 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
612
613 /*
614 * This quirk needs to be enabled if the host controller does not
615 * support UIC command
616 */
617 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,
618
619 /*
620 * This quirk needs to be enabled if the host controller cannot
621 * support physical host configuration.
622 */
623 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,
624
625 /*
626 * This quirk needs to be enabled if the host controller has
627 * 64-bit addressing supported capability but it doesn't work.
628 */
629 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17,
630
631 /*
632 * This quirk needs to be enabled if the host controller has
633 * auto-hibernate capability but it's FASTAUTO only.
634 */
635 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
636
637 /*
638 * This quirk needs to be enabled if the host controller needs
639 * to reinit the device after switching to maximum gear.
640 */
641 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
642
643 /*
644 * Some host raises interrupt (per queue) in addition to
645 * CQES (traditional) when ESI is disabled.
646 * Enable this quirk will disable CQES and use per queue interrupt.
647 */
648 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,
649
650 /*
651 * Some host does not implement SQ Run Time Command (SQRTC) register
652 * thus need this quirk to skip related flow.
653 */
654 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
655
656 /*
657 * This quirk needs to be enabled if the host controller supports inline
658 * encryption but it needs to initialize the crypto capabilities in a
659 * nonstandard way and/or needs to override blk_crypto_ll_ops. If
660 * enabled, the standard code won't initialize the blk_crypto_profile;
661 * ufs_hba_variant_ops::init() must do it instead.
662 */
663 UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22,
664
665 /*
666 * This quirk needs to be enabled if the host controller supports inline
667 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
668 * host controller initialization fails if that bit is set.
669 */
670 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23,
671
672 /*
673 * This quirk needs to be enabled if the host controller driver copies
674 * cryptographic keys into the PRDT in order to send them to hardware,
675 * and therefore the PRDT should be zeroized after each request (as per
676 * the standard best practice for managing keys).
677 */
678 UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24,
679 };
680
681 enum ufshcd_caps {
682 /* Allow dynamic clk gating */
683 UFSHCD_CAP_CLK_GATING = 1 << 0,
684
685 /* Allow hiberb8 with clk gating */
686 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
687
688 /* Allow dynamic clk scaling */
689 UFSHCD_CAP_CLK_SCALING = 1 << 2,
690
691 /* Allow auto bkops to enabled during runtime suspend */
692 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
693
694 /*
695 * This capability allows host controller driver to use the UFS HCI's
696 * interrupt aggregation capability.
697 * CAUTION: Enabling this might reduce overall UFS throughput.
698 */
699 UFSHCD_CAP_INTR_AGGR = 1 << 4,
700
701 /*
702 * This capability allows the device auto-bkops to be always enabled
703 * except during suspend (both runtime and suspend).
704 * Enabling this capability means that device will always be allowed
705 * to do background operation when it's active but it might degrade
706 * the performance of ongoing read/write operations.
707 */
708 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
709
710 /*
711 * This capability allows host controller driver to automatically
712 * enable runtime power management by itself instead of waiting
713 * for userspace to control the power management.
714 */
715 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
716
717 /*
718 * This capability allows the host controller driver to turn-on
719 * WriteBooster, if the underlying device supports it and is
720 * provisioned to be used. This would increase the write performance.
721 */
722 UFSHCD_CAP_WB_EN = 1 << 7,
723
724 /*
725 * This capability allows the host controller driver to use the
726 * inline crypto engine, if it is present
727 */
728 UFSHCD_CAP_CRYPTO = 1 << 8,
729
730 /*
731 * This capability allows the controller regulators to be put into
732 * lpm mode aggressively during clock gating.
733 * This would increase power savings.
734 */
735 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,
736
737 /*
738 * This capability allows the host controller driver to use DeepSleep,
739 * if it is supported by the UFS device. The host controller driver must
740 * support device hardware reset via the hba->device_reset() callback,
741 * in order to exit DeepSleep state.
742 */
743 UFSHCD_CAP_DEEPSLEEP = 1 << 10,
744
745 /*
746 * This capability allows the host controller driver to use temperature
747 * notification if it is supported by the UFS device.
748 */
749 UFSHCD_CAP_TEMP_NOTIF = 1 << 11,
750
751 /*
752 * Enable WriteBooster when scaling up the clock and disable
753 * WriteBooster when scaling the clock down.
754 */
755 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,
756 };
757
758 struct ufs_hba_variant_params {
759 struct devfreq_dev_profile devfreq_profile;
760 struct devfreq_simple_ondemand_data ondemand_data;
761 u16 hba_enable_delay_us;
762 u32 wb_flush_threshold;
763 };
764
765 struct ufs_hba_monitor {
766 unsigned long chunk_size;
767
768 unsigned long nr_sec_rw[2];
769 ktime_t total_busy[2];
770
771 unsigned long nr_req[2];
772 /* latencies*/
773 ktime_t lat_sum[2];
774 ktime_t lat_max[2];
775 ktime_t lat_min[2];
776
777 u32 nr_queued[2];
778 ktime_t busy_start_ts[2];
779
780 ktime_t enabled_ts;
781 bool enabled;
782 };
783
784 /**
785 * struct ufshcd_res_info_t - MCQ related resource regions
786 *
787 * @name: resource name
788 * @resource: pointer to resource region
789 * @base: register base address
790 */
791 struct ufshcd_res_info {
792 const char *name;
793 struct resource *resource;
794 void __iomem *base;
795 };
796
797 enum ufshcd_res {
798 RES_UFS,
799 RES_MCQ,
800 RES_MCQ_SQD,
801 RES_MCQ_SQIS,
802 RES_MCQ_CQD,
803 RES_MCQ_CQIS,
804 RES_MCQ_VS,
805 RES_MAX,
806 };
807
808 /**
809 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
810 *
811 * @offset: Doorbell Address Offset
812 * @stride: Steps proportional to queue [0...31]
813 * @base: base address
814 */
815 struct ufshcd_mcq_opr_info_t {
816 unsigned long offset;
817 unsigned long stride;
818 void __iomem *base;
819 };
820
821 enum ufshcd_mcq_opr {
822 OPR_SQD,
823 OPR_SQIS,
824 OPR_CQD,
825 OPR_CQIS,
826 OPR_MAX,
827 };
828
829 /**
830 * struct ufs_hba - per adapter private structure
831 * @mmio_base: UFSHCI base register address
832 * @ucdl_base_addr: UFS Command Descriptor base address
833 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
834 * @utmrdl_base_addr: UTP Task Management Descriptor base address
835 * @ucdl_dma_addr: UFS Command Descriptor DMA address
836 * @utrdl_dma_addr: UTRDL DMA address
837 * @utmrdl_dma_addr: UTMRDL DMA address
838 * @host: Scsi_Host instance of the driver
839 * @dev: device handle
840 * @ufs_device_wlun: WLUN that controls the entire UFS device.
841 * @hwmon_device: device instance registered with the hwmon core.
842 * @curr_dev_pwr_mode: active UFS device power mode.
843 * @uic_link_state: active state of the link to the UFS device.
844 * @rpm_lvl: desired UFS power management level during runtime PM.
845 * @spm_lvl: desired UFS power management level during system PM.
846 * @pm_op_in_progress: whether or not a PM operation is in progress.
847 * @ahit: value of Auto-Hibernate Idle Timer register.
848 * @lrb: local reference block
849 * @outstanding_tasks: Bits representing outstanding task requests
850 * @outstanding_lock: Protects @outstanding_reqs.
851 * @outstanding_reqs: Bits representing outstanding transfer requests
852 * @capabilities: UFS Controller Capabilities
853 * @mcq_capabilities: UFS Multi Circular Queue capabilities
854 * @nutrs: Transfer Request Queue depth supported by controller
855 * @nortt - Max outstanding RTTs supported by controller
856 * @nutmrs: Task Management Queue depth supported by controller
857 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
858 * @ufs_version: UFS Version to which controller complies
859 * @vops: pointer to variant specific operations
860 * @vps: pointer to variant specific parameters
861 * @priv: pointer to variant specific private data
862 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
863 * @irq: Irq number of the controller
864 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
865 * @dev_ref_clk_freq: reference clock frequency
866 * @quirks: bitmask with information about deviations from the UFSHCI standard.
867 * @dev_quirks: bitmask with information about deviations from the UFS standard.
868 * @tmf_tag_set: TMF tag set.
869 * @tmf_queue: Used to allocate TMF tags.
870 * @tmf_rqs: array with pointers to TMF requests while these are in progress.
871 * @active_uic_cmd: handle of active UIC command
872 * @uic_cmd_mutex: mutex for UIC command
873 * @uic_async_done: completion used during UIC processing
874 * @ufshcd_state: UFSHCD state
875 * @eh_flags: Error handling flags
876 * @intr_mask: Interrupt Mask Bits
877 * @ee_ctrl_mask: Exception event control mask
878 * @ee_drv_mask: Exception event mask for driver
879 * @ee_usr_mask: Exception event mask for user (set via debugfs)
880 * @ee_ctrl_mutex: Used to serialize exception event information.
881 * @is_powered: flag to check if HBA is powered
882 * @shutting_down: flag to check if shutdown has been invoked
883 * @host_sem: semaphore used to serialize concurrent contexts
884 * @eh_wq: Workqueue that eh_work works on
885 * @eh_work: Worker to handle UFS errors that require s/w attention
886 * @eeh_work: Worker to handle exception events
887 * @errors: HBA errors
888 * @uic_error: UFS interconnect layer error status
889 * @saved_err: sticky error mask
890 * @saved_uic_err: sticky UIC error mask
891 * @ufs_stats: various error counters
892 * @force_reset: flag to force eh_work perform a full reset
893 * @force_pmc: flag to force a power mode change
894 * @silence_err_logs: flag to silence error logs
895 * @dev_cmd: ufs device management command information
896 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
897 * @nop_out_timeout: NOP OUT timeout value
898 * @dev_info: information about the UFS device
899 * @auto_bkops_enabled: to track whether bkops is enabled in device
900 * @vreg_info: UFS device voltage regulator information
901 * @clk_list_head: UFS host controller clocks list node head
902 * @use_pm_opp: Indicates whether OPP based scaling is used or not
903 * @req_abort_count: number of times ufshcd_abort() has been called
904 * @lanes_per_direction: number of lanes per data direction between the UFS
905 * controller and the UFS device.
906 * @pwr_info: holds current power mode
907 * @max_pwr_info: keeps the device max valid pwm
908 * @clk_gating: information related to clock gating
909 * @caps: bitmask with information about UFS controller capabilities
910 * @devfreq: frequency scaling information owned by the devfreq core
911 * @clk_scaling: frequency scaling information owned by the UFS driver
912 * @system_suspending: system suspend has been started and system resume has
913 * not yet finished.
914 * @is_sys_suspended: UFS device has been suspended because of system suspend
915 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
916 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
917 * device is known or not.
918 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
919 * @clk_scaling_lock: used to serialize device commands and clock scaling
920 * @desc_size: descriptor sizes reported by device
921 * @scsi_block_reqs_cnt: reference counting for scsi block requests
922 * @bsg_dev: struct device associated with the BSG queue
923 * @bsg_queue: BSG queue associated with the UFS controller
924 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
925 * management) after the UFS device has finished a WriteBooster buffer
926 * flush or auto BKOP.
927 * @monitor: statistics about UFS commands
928 * @crypto_capabilities: Content of crypto capabilities register (0x100)
929 * @crypto_cap_array: Array of crypto capabilities
930 * @crypto_cfg_register: Start of the crypto cfg array
931 * @crypto_profile: the crypto profile of this hba (if applicable)
932 * @debugfs_root: UFS controller debugfs root directory
933 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
934 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
935 * ee_ctrl_mask
936 * @luns_avail: number of regular and well known LUNs supported by the UFS
937 * device
938 * @nr_hw_queues: number of hardware queues configured
939 * @nr_queues: number of Queues of different queue types
940 * @complete_put: whether or not to call ufshcd_rpm_put() from inside
941 * ufshcd_resume_complete()
942 * @ext_iid_sup: is EXT_IID is supported by UFSHC
943 * @mcq_sup: is mcq supported by UFSHC
944 * @mcq_enabled: is mcq ready to accept requests
945 * @res: array of resource info of MCQ registers
946 * @mcq_base: Multi circular queue registers base address
947 * @uhq: array of supported hardware queues
948 * @dev_cmd_queue: Queue for issuing device management commands
949 * @mcq_opr: MCQ operation and runtime registers
950 * @ufs_rtc_update_work: A work for UFS RTC periodic update
951 * @pm_qos_req: PM QoS request handle
952 * @pm_qos_enabled: flag to check if pm qos is enabled
953 */
954 struct ufs_hba {
955 void __iomem *mmio_base;
956
957 /* Virtual memory reference */
958 struct utp_transfer_cmd_desc *ucdl_base_addr;
959 struct utp_transfer_req_desc *utrdl_base_addr;
960 struct utp_task_req_desc *utmrdl_base_addr;
961
962 /* DMA memory reference */
963 dma_addr_t ucdl_dma_addr;
964 dma_addr_t utrdl_dma_addr;
965 dma_addr_t utmrdl_dma_addr;
966
967 struct Scsi_Host *host;
968 struct device *dev;
969 struct scsi_device *ufs_device_wlun;
970
971 #ifdef CONFIG_SCSI_UFS_HWMON
972 struct device *hwmon_device;
973 #endif
974
975 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
976 enum uic_link_state uic_link_state;
977 /* Desired UFS power management level during runtime PM */
978 enum ufs_pm_level rpm_lvl;
979 /* Desired UFS power management level during system PM */
980 enum ufs_pm_level spm_lvl;
981 int pm_op_in_progress;
982
983 /* Auto-Hibernate Idle Timer register value */
984 u32 ahit;
985
986 struct ufshcd_lrb *lrb;
987
988 unsigned long outstanding_tasks;
989 spinlock_t outstanding_lock;
990 unsigned long outstanding_reqs;
991
992 u32 capabilities;
993 int nutrs;
994 int nortt;
995 u32 mcq_capabilities;
996 int nutmrs;
997 u32 reserved_slot;
998 u32 ufs_version;
999 const struct ufs_hba_variant_ops *vops;
1000 struct ufs_hba_variant_params *vps;
1001 void *priv;
1002 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1003 size_t sg_entry_size;
1004 #endif
1005 unsigned int irq;
1006 bool is_irq_enabled;
1007 enum ufs_ref_clk_freq dev_ref_clk_freq;
1008
1009 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
1010
1011 /* Device deviations from standard UFS device spec. */
1012 unsigned int dev_quirks;
1013
1014 struct blk_mq_tag_set tmf_tag_set;
1015 struct request_queue *tmf_queue;
1016 struct request **tmf_rqs;
1017
1018 struct uic_command *active_uic_cmd;
1019 struct mutex uic_cmd_mutex;
1020 struct completion *uic_async_done;
1021
1022 enum ufshcd_state ufshcd_state;
1023 u32 eh_flags;
1024 u32 intr_mask;
1025 u16 ee_ctrl_mask;
1026 u16 ee_drv_mask;
1027 u16 ee_usr_mask;
1028 struct mutex ee_ctrl_mutex;
1029 bool is_powered;
1030 bool shutting_down;
1031 struct semaphore host_sem;
1032
1033 /* Work Queues */
1034 struct workqueue_struct *eh_wq;
1035 struct work_struct eh_work;
1036 struct work_struct eeh_work;
1037
1038 /* HBA Errors */
1039 u32 errors;
1040 u32 uic_error;
1041 u32 saved_err;
1042 u32 saved_uic_err;
1043 struct ufs_stats ufs_stats;
1044 bool force_reset;
1045 bool force_pmc;
1046 bool silence_err_logs;
1047
1048 /* Device management request data */
1049 struct ufs_dev_cmd dev_cmd;
1050 ktime_t last_dme_cmd_tstamp;
1051 int nop_out_timeout;
1052
1053 /* Keeps information of the UFS device connected to this host */
1054 struct ufs_dev_info dev_info;
1055 bool auto_bkops_enabled;
1056 struct ufs_vreg_info vreg_info;
1057 struct list_head clk_list_head;
1058 bool use_pm_opp;
1059
1060 /* Number of requests aborts */
1061 int req_abort_count;
1062
1063 /* Number of lanes available (1 or 2) for Rx/Tx */
1064 u32 lanes_per_direction;
1065 struct ufs_pa_layer_attr pwr_info;
1066 struct ufs_pwr_mode_info max_pwr_info;
1067
1068 struct ufs_clk_gating clk_gating;
1069 /* Control to enable/disable host capabilities */
1070 u32 caps;
1071
1072 struct devfreq *devfreq;
1073 struct ufs_clk_scaling clk_scaling;
1074 bool system_suspending;
1075 bool is_sys_suspended;
1076
1077 enum bkops_status urgent_bkops_lvl;
1078 bool is_urgent_bkops_lvl_checked;
1079
1080 struct mutex wb_mutex;
1081 struct rw_semaphore clk_scaling_lock;
1082 atomic_t scsi_block_reqs_cnt;
1083
1084 struct device bsg_dev;
1085 struct request_queue *bsg_queue;
1086 struct delayed_work rpm_dev_flush_recheck_work;
1087
1088 struct ufs_hba_monitor monitor;
1089
1090 #ifdef CONFIG_SCSI_UFS_CRYPTO
1091 union ufs_crypto_capabilities crypto_capabilities;
1092 union ufs_crypto_cap_entry *crypto_cap_array;
1093 u32 crypto_cfg_register;
1094 struct blk_crypto_profile crypto_profile;
1095 #endif
1096 #ifdef CONFIG_DEBUG_FS
1097 struct dentry *debugfs_root;
1098 struct delayed_work debugfs_ee_work;
1099 u32 debugfs_ee_rate_limit_ms;
1100 #endif
1101 #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION
1102 struct fault_attr trigger_eh_attr;
1103 struct fault_attr timeout_attr;
1104 #endif
1105 u32 luns_avail;
1106 unsigned int nr_hw_queues;
1107 unsigned int nr_queues[HCTX_MAX_TYPES];
1108 bool complete_put;
1109 bool ext_iid_sup;
1110 bool scsi_host_added;
1111 bool mcq_sup;
1112 bool lsdb_sup;
1113 bool mcq_enabled;
1114 struct ufshcd_res_info res[RES_MAX];
1115 void __iomem *mcq_base;
1116 struct ufs_hw_queue *uhq;
1117 struct ufs_hw_queue *dev_cmd_queue;
1118 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1119
1120 struct delayed_work ufs_rtc_update_work;
1121 struct pm_qos_request pm_qos_req;
1122 bool pm_qos_enabled;
1123 };
1124
1125 /**
1126 * struct ufs_hw_queue - per hardware queue structure
1127 * @mcq_sq_head: base address of submission queue head pointer
1128 * @mcq_sq_tail: base address of submission queue tail pointer
1129 * @mcq_cq_head: base address of completion queue head pointer
1130 * @mcq_cq_tail: base address of completion queue tail pointer
1131 * @sqe_base_addr: submission queue entry base address
1132 * @sqe_dma_addr: submission queue dma address
1133 * @cqe_base_addr: completion queue base address
1134 * @cqe_dma_addr: completion queue dma address
1135 * @max_entries: max number of slots in this hardware queue
1136 * @id: hardware queue ID
1137 * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1138 * @sq_lock: serialize submission queue access
1139 * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1140 * @cq_head_slot: current slot to which CQ head pointer is pointing
1141 * @cq_lock: Synchronize between multiple polling instances
1142 * @sq_mutex: prevent submission queue concurrent access
1143 */
1144 struct ufs_hw_queue {
1145 void __iomem *mcq_sq_head;
1146 void __iomem *mcq_sq_tail;
1147 void __iomem *mcq_cq_head;
1148 void __iomem *mcq_cq_tail;
1149
1150 struct utp_transfer_req_desc *sqe_base_addr;
1151 dma_addr_t sqe_dma_addr;
1152 struct cq_entry *cqe_base_addr;
1153 dma_addr_t cqe_dma_addr;
1154 u32 max_entries;
1155 u32 id;
1156 u32 sq_tail_slot;
1157 spinlock_t sq_lock;
1158 u32 cq_tail_slot;
1159 u32 cq_head_slot;
1160 spinlock_t cq_lock;
1161 /* prevent concurrent access to submission queue */
1162 struct mutex sq_mutex;
1163 };
1164
1165 #define MCQ_QCFG_SIZE 0x40
1166
1167 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,
1168 enum ufshcd_mcq_opr opr, int idx)
1169 {
1170 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1171 }
1172
1173 static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx)
1174 {
1175 return reg + MCQ_QCFG_SIZE * idx;
1176 }
1177
1178 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1179 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1180 {
1181 return hba->sg_entry_size;
1182 }
1183
1184 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1185 {
1186 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1187 hba->sg_entry_size = sg_entry_size;
1188 }
1189 #else
1190 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1191 {
1192 return sizeof(struct ufshcd_sg_entry);
1193 }
1194
1195 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \
1196 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1197 #endif
1198
1199 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1200 {
1201 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1202 }
1203
1204 /* Returns true if clocks can be gated. Otherwise false */
1205 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1206 {
1207 return hba->caps & UFSHCD_CAP_CLK_GATING;
1208 }
1209 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1210 {
1211 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1212 }
1213 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1214 {
1215 return hba->caps & UFSHCD_CAP_CLK_SCALING;
1216 }
1217 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1218 {
1219 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1220 }
1221 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1222 {
1223 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1224 }
1225
1226 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1227 {
1228 return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1229 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1230 }
1231
1232 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1233 {
1234 return !!(ufshcd_is_link_hibern8(hba) &&
1235 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1236 }
1237
1238 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1239 {
1240 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1241 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1242 }
1243
1244 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1245 {
1246 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1247 }
1248
1249 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1250 {
1251 return hba->caps & UFSHCD_CAP_WB_EN;
1252 }
1253
1254 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1255 {
1256 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1257 }
1258
1259 #define ufsmcq_writel(hba, val, reg) \
1260 writel((val), (hba)->mcq_base + (reg))
1261 #define ufsmcq_readl(hba, reg) \
1262 readl((hba)->mcq_base + (reg))
1263
1264 #define ufsmcq_writelx(hba, val, reg) \
1265 writel_relaxed((val), (hba)->mcq_base + (reg))
1266 #define ufsmcq_readlx(hba, reg) \
1267 readl_relaxed((hba)->mcq_base + (reg))
1268
1269 #define ufshcd_writel(hba, val, reg) \
1270 writel((val), (hba)->mmio_base + (reg))
1271 #define ufshcd_readl(hba, reg) \
1272 readl((hba)->mmio_base + (reg))
1273
1274 /**
1275 * ufshcd_rmwl - perform read/modify/write for a controller register
1276 * @hba: per adapter instance
1277 * @mask: mask to apply on read value
1278 * @val: actual value to write
1279 * @reg: register address
1280 */
1281 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1282 {
1283 u32 tmp;
1284
1285 tmp = ufshcd_readl(hba, reg);
1286 tmp &= ~mask;
1287 tmp |= (val & mask);
1288 ufshcd_writel(hba, tmp, reg);
1289 }
1290
1291 void ufshcd_enable_irq(struct ufs_hba *hba);
1292 void ufshcd_disable_irq(struct ufs_hba *hba);
1293 int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1294 void ufshcd_dealloc_host(struct ufs_hba *);
1295 int ufshcd_hba_enable(struct ufs_hba *hba);
1296 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1297 int ufshcd_link_recovery(struct ufs_hba *hba);
1298 int ufshcd_make_hba_operational(struct ufs_hba *hba);
1299 void ufshcd_remove(struct ufs_hba *);
1300 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1301 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1302 void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1303 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1304 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1305 void ufshcd_hba_stop(struct ufs_hba *hba);
1306 void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1307 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);
1308 unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba);
1309 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);
1310 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1311 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1312 struct ufs_hw_queue *hwq);
1313 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
1314 void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1315 void ufshcd_mcq_enable(struct ufs_hba *hba);
1316 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1317
1318 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1319 struct dev_pm_opp *opp, void *data,
1320 bool scaling_down);
1321 /**
1322 * ufshcd_set_variant - set variant specific data to the hba
1323 * @hba: per adapter instance
1324 * @variant: pointer to variant specific data
1325 */
1326 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1327 {
1328 BUG_ON(!hba);
1329 hba->priv = variant;
1330 }
1331
1332 /**
1333 * ufshcd_get_variant - get variant specific data from the hba
1334 * @hba: per adapter instance
1335 */
1336 static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1337 {
1338 BUG_ON(!hba);
1339 return hba->priv;
1340 }
1341
1342 #ifdef CONFIG_PM
1343 extern int ufshcd_runtime_suspend(struct device *dev);
1344 extern int ufshcd_runtime_resume(struct device *dev);
1345 #endif
1346 #ifdef CONFIG_PM_SLEEP
1347 extern int ufshcd_system_suspend(struct device *dev);
1348 extern int ufshcd_system_resume(struct device *dev);
1349 extern int ufshcd_system_freeze(struct device *dev);
1350 extern int ufshcd_system_thaw(struct device *dev);
1351 extern int ufshcd_system_restore(struct device *dev);
1352 #endif
1353
1354 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1355 int agreed_gear,
1356 int adapt_val);
1357 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1358 u8 attr_set, u32 mib_val, u8 peer);
1359 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1360 u32 *mib_val, u8 peer);
1361 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1362 struct ufs_pa_layer_attr *desired_pwr_mode);
1363 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1364
1365 /* UIC command interfaces for DME primitives */
1366 #define DME_LOCAL 0
1367 #define DME_PEER 1
1368 #define ATTR_SET_NOR 0 /* NORMAL */
1369 #define ATTR_SET_ST 1 /* STATIC */
1370
1371 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1372 u32 mib_val)
1373 {
1374 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1375 mib_val, DME_LOCAL);
1376 }
1377
1378 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1379 u32 mib_val)
1380 {
1381 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1382 mib_val, DME_LOCAL);
1383 }
1384
1385 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1386 u32 mib_val)
1387 {
1388 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1389 mib_val, DME_PEER);
1390 }
1391
1392 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1393 u32 mib_val)
1394 {
1395 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1396 mib_val, DME_PEER);
1397 }
1398
1399 static inline int ufshcd_dme_get(struct ufs_hba *hba,
1400 u32 attr_sel, u32 *mib_val)
1401 {
1402 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1403 }
1404
1405 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1406 u32 attr_sel, u32 *mib_val)
1407 {
1408 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1409 }
1410
1411 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
1412 {
1413 return (pwr_info->pwr_rx == FAST_MODE ||
1414 pwr_info->pwr_rx == FASTAUTO_MODE) &&
1415 (pwr_info->pwr_tx == FAST_MODE ||
1416 pwr_info->pwr_tx == FASTAUTO_MODE);
1417 }
1418
1419 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1420 {
1421 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1422 }
1423
1424 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1425 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1426 const struct ufs_dev_quirk *fixups);
1427 #define SD_ASCII_STD true
1428 #define SD_RAW false
1429 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1430 u8 **buf, bool ascii);
1431
1432 void ufshcd_hold(struct ufs_hba *hba);
1433 void ufshcd_release(struct ufs_hba *hba);
1434
1435 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1436
1437 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1438
1439 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1440
1441 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1442 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1443 struct ufs_ehs *ehs_rsp, int sg_cnt,
1444 struct scatterlist *sg_list, enum dma_data_direction dir);
1445 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1446 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1447 int ufshcd_suspend_prepare(struct device *dev);
1448 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1449 void ufshcd_resume_complete(struct device *dev);
1450 bool ufshcd_is_hba_active(struct ufs_hba *hba);
1451 void ufshcd_pm_qos_init(struct ufs_hba *hba);
1452 void ufshcd_pm_qos_exit(struct ufs_hba *hba);
1453
1454 /* Wrapper functions for safely calling variant operations */
1455 static inline int ufshcd_vops_init(struct ufs_hba *hba)
1456 {
1457 if (hba->vops && hba->vops->init)
1458 return hba->vops->init(hba);
1459
1460 return 0;
1461 }
1462
1463 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1464 {
1465 if (hba->vops && hba->vops->phy_initialization)
1466 return hba->vops->phy_initialization(hba);
1467
1468 return 0;
1469 }
1470
1471 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1472
1473 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1474 const char *prefix);
1475
1476 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1477 int ufshcd_write_ee_control(struct ufs_hba *hba);
1478 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1479 const u16 *other_mask, u16 set, u16 clr);
1480
1481 #endif /* End of Header */
1482
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