1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 *
6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */
10
11 #ifndef _UFSHCI_H
12 #define _UFSHCI_H
13
14 #include <linux/types.h>
15 #include <ufs/ufs.h>
16
17 enum {
18 TASK_REQ_UPIU_SIZE_DWORDS = 8,
19 TASK_RSP_UPIU_SIZE_DWORDS = 8,
20 ALIGNED_UPIU_SIZE = 512,
21 };
22
23 /* UFSHCI Registers */
24 enum {
25 REG_CONTROLLER_CAPABILITIES = 0x00,
26 REG_MCQCAP = 0x04,
27 REG_UFS_VERSION = 0x08,
28 REG_CONTROLLER_DEV_ID = 0x10,
29 REG_CONTROLLER_PROD_ID = 0x14,
30 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
31 REG_INTERRUPT_STATUS = 0x20,
32 REG_INTERRUPT_ENABLE = 0x24,
33 REG_CONTROLLER_STATUS = 0x30,
34 REG_CONTROLLER_ENABLE = 0x34,
35 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
36 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
37 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
38 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
39 REG_UIC_ERROR_CODE_DME = 0x48,
40 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
41 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
42 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
43 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
44 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
45 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
46 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
47 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
48 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
49 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
50 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
51 REG_UIC_COMMAND = 0x90,
52 REG_UIC_COMMAND_ARG_1 = 0x94,
53 REG_UIC_COMMAND_ARG_2 = 0x98,
54 REG_UIC_COMMAND_ARG_3 = 0x9C,
55
56 UFSHCI_REG_SPACE_SIZE = 0xA0,
57
58 REG_UFS_CCAP = 0x100,
59 REG_UFS_CRYPTOCAP = 0x104,
60
61 REG_UFS_MEM_CFG = 0x300,
62 REG_UFS_MCQ_CFG = 0x380,
63 REG_UFS_ESILBA = 0x384,
64 REG_UFS_ESIUBA = 0x388,
65 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
66 };
67
68 /* Controller capability masks */
69 enum {
70 MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F,
71 MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF,
72 MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00,
73 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
74 MASK_EHSLUTRD_SUPPORTED = 0x00400000,
75 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
76 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
77 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
78 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
79 MASK_CRYPTO_SUPPORT = 0x10000000,
80 MASK_LSDB_SUPPORT = 0x20000000,
81 MASK_MCQ_SUPPORT = 0x40000000,
82 };
83
84 /* MCQ capability mask */
85 enum {
86 MASK_EXT_IID_SUPPORT = 0x00000400,
87 };
88
89 enum {
90 REG_SQATTR = 0x0,
91 REG_SQLBA = 0x4,
92 REG_SQUBA = 0x8,
93 REG_SQDAO = 0xC,
94 REG_SQISAO = 0x10,
95
96 REG_CQATTR = 0x20,
97 REG_CQLBA = 0x24,
98 REG_CQUBA = 0x28,
99 REG_CQDAO = 0x2C,
100 REG_CQISAO = 0x30,
101 };
102
103 enum {
104 REG_SQHP = 0x0,
105 REG_SQTP = 0x4,
106 REG_SQRTC = 0x8,
107 REG_SQCTI = 0xC,
108 REG_SQRTS = 0x10,
109 };
110
111 enum {
112 REG_CQHP = 0x0,
113 REG_CQTP = 0x4,
114 };
115
116 enum {
117 REG_CQIS = 0x0,
118 REG_CQIE = 0x4,
119 };
120
121 enum {
122 SQ_START = 0x0,
123 SQ_STOP = 0x1,
124 SQ_ICU = 0x2,
125 };
126
127 enum {
128 SQ_STS = 0x1,
129 SQ_CUS = 0x2,
130 };
131
132 #define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)
133 #define UFS_MASK(mask, offset) ((mask) << (offset))
134
135 /* UFS Version 08h */
136 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
137 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
138
139 #define UFSHCD_NUM_RESERVED 1
140 /*
141 * Controller UFSHCI version
142 * - 2.x and newer use the following scheme:
143 * major << 8 + minor << 4
144 * - 1.x has been converted to match this in
145 * ufshcd_get_ufs_version()
146 */
147 static inline u32 ufshci_version(u32 major, u32 minor)
148 {
149 return (major << 8) + (minor << 4);
150 }
151
152 /*
153 * HCDDID - Host Controller Identification Descriptor
154 * - Device ID and Device Class 10h
155 */
156 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
157 #define DEVICE_ID UFS_MASK(0xFF, 24)
158
159 /*
160 * HCPMID - Host Controller Identification Descriptor
161 * - Product/Manufacturer ID 14h
162 */
163 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
164 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
165
166 /* AHIT - Auto-Hibernate Idle Timer */
167 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
168 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
169 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
170 #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
171
172 /*
173 * IS - Interrupt Status - 20h
174 */
175 #define UTP_TRANSFER_REQ_COMPL 0x1
176 #define UIC_DME_END_PT_RESET 0x2
177 #define UIC_ERROR 0x4
178 #define UIC_TEST_MODE 0x8
179 #define UIC_POWER_MODE 0x10
180 #define UIC_HIBERNATE_EXIT 0x20
181 #define UIC_HIBERNATE_ENTER 0x40
182 #define UIC_LINK_LOST 0x80
183 #define UIC_LINK_STARTUP 0x100
184 #define UTP_TASK_REQ_COMPL 0x200
185 #define UIC_COMMAND_COMPL 0x400
186 #define DEVICE_FATAL_ERROR 0x800
187 #define CONTROLLER_FATAL_ERROR 0x10000
188 #define SYSTEM_BUS_FATAL_ERROR 0x20000
189 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000
190 #define MCQ_CQ_EVENT_STATUS 0x100000
191
192 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
193 UIC_HIBERNATE_EXIT)
194
195 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
196 UIC_POWER_MODE)
197
198 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
199
200 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
201
202 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
203 CONTROLLER_FATAL_ERROR |\
204 SYSTEM_BUS_FATAL_ERROR |\
205 CRYPTO_ENGINE_FATAL_ERROR |\
206 UIC_LINK_LOST)
207
208 /* HCS - Host Controller Status 30h */
209 #define DEVICE_PRESENT 0x1
210 #define UTP_TRANSFER_REQ_LIST_READY 0x2
211 #define UTP_TASK_REQ_LIST_READY 0x4
212 #define UIC_COMMAND_READY 0x8
213 #define HOST_ERROR_INDICATOR 0x10
214 #define DEVICE_ERROR_INDICATOR 0x20
215 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
216
217 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
218 UTP_TASK_REQ_LIST_READY |\
219 UIC_COMMAND_READY)
220
221 enum {
222 PWR_OK = 0x0,
223 PWR_LOCAL = 0x01,
224 PWR_REMOTE = 0x02,
225 PWR_BUSY = 0x03,
226 PWR_ERROR_CAP = 0x04,
227 PWR_FATAL_ERROR = 0x05,
228 };
229
230 /* HCE - Host Controller Enable 34h */
231 #define CONTROLLER_ENABLE 0x1
232 #define CONTROLLER_DISABLE 0x0
233 #define CRYPTO_GENERAL_ENABLE 0x2
234
235 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
236 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
237 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
238 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
239 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
240
241 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
242 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
243 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
244 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
245 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
246 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
247 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
248 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
249 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
250 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
251
252 /* UECN - Host UIC Error Code Network Layer 40h */
253 #define UIC_NETWORK_LAYER_ERROR 0x80000000
254 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
255 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
256 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
257 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
258
259 /* UECT - Host UIC Error Code Transport Layer 44h */
260 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
261 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
262 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
263 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
264 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
265 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
266 #define UIC_TRANSPORT_BAD_TC 0x10
267 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
268 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
269
270 /* UECDME - Host UIC Error Code DME 48h */
271 #define UIC_DME_ERROR 0x80000000
272 #define UIC_DME_ERROR_CODE_MASK 0x1
273
274 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
275 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
276 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
277 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
278 #define INT_AGGR_STATUS_BIT 0x100000
279 #define INT_AGGR_PARAM_WRITE 0x1000000
280 #define INT_AGGR_ENABLE 0x80000000
281
282 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
283 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
284
285 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
286 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
287
288 /* REG_UFS_MEM_CFG - Global Config Registers 300h */
289 #define MCQ_MODE_SELECT BIT(0)
290
291 /* CQISy - CQ y Interrupt Status Register */
292 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
293
294 /* UICCMD - UIC Command */
295 #define COMMAND_OPCODE_MASK 0xFF
296 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
297
298 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
299 #define RESET_LEVEL 0xFF
300
301 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
302 #define CONFIG_RESULT_CODE_MASK 0xFF
303 #define GENERIC_ERROR_CODE_MASK 0xFF
304
305 /* GenSelectorIndex calculation macros for M-PHY attributes */
306 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
307 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
308
309 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
310 ((sel) & 0xFFFF))
311 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
312 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
313 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
314
315 /* Link Status*/
316 enum link_status {
317 UFSHCD_LINK_IS_DOWN = 1,
318 UFSHCD_LINK_IS_UP = 2,
319 };
320
321 /* UIC Commands */
322 enum uic_cmd_dme {
323 UIC_CMD_DME_GET = 0x01,
324 UIC_CMD_DME_SET = 0x02,
325 UIC_CMD_DME_PEER_GET = 0x03,
326 UIC_CMD_DME_PEER_SET = 0x04,
327 UIC_CMD_DME_POWERON = 0x10,
328 UIC_CMD_DME_POWEROFF = 0x11,
329 UIC_CMD_DME_ENABLE = 0x12,
330 UIC_CMD_DME_RESET = 0x14,
331 UIC_CMD_DME_END_PT_RST = 0x15,
332 UIC_CMD_DME_LINK_STARTUP = 0x16,
333 UIC_CMD_DME_HIBER_ENTER = 0x17,
334 UIC_CMD_DME_HIBER_EXIT = 0x18,
335 UIC_CMD_DME_TEST_MODE = 0x1A,
336 };
337
338 /* UIC Config result code / Generic error code */
339 enum {
340 UIC_CMD_RESULT_SUCCESS = 0x00,
341 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
342 UIC_CMD_RESULT_FAILURE = 0x01,
343 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
344 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
345 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
346 UIC_CMD_RESULT_BAD_INDEX = 0x05,
347 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
348 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
349 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
350 UIC_CMD_RESULT_BUSY = 0x09,
351 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
352 };
353
354 #define MASK_UIC_COMMAND_RESULT 0xFF
355
356 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
357 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
358
359 /* Interrupt disable masks */
360 enum {
361 /* Interrupt disable mask for UFSHCI v1.1 */
362 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
363
364 /* Interrupt disable mask for UFSHCI v2.1 */
365 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
366 };
367
368 /* CCAP - Crypto Capability 100h */
369 union ufs_crypto_capabilities {
370 __le32 reg_val;
371 struct {
372 u8 num_crypto_cap;
373 u8 config_count;
374 u8 reserved;
375 u8 config_array_ptr;
376 };
377 };
378
379 enum ufs_crypto_key_size {
380 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
381 UFS_CRYPTO_KEY_SIZE_128 = 0x1,
382 UFS_CRYPTO_KEY_SIZE_192 = 0x2,
383 UFS_CRYPTO_KEY_SIZE_256 = 0x3,
384 UFS_CRYPTO_KEY_SIZE_512 = 0x4,
385 };
386
387 enum ufs_crypto_alg {
388 UFS_CRYPTO_ALG_AES_XTS = 0x0,
389 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
390 UFS_CRYPTO_ALG_AES_ECB = 0x2,
391 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
392 };
393
394 /* x-CRYPTOCAP - Crypto Capability X */
395 union ufs_crypto_cap_entry {
396 __le32 reg_val;
397 struct {
398 u8 algorithm_id;
399 u8 sdus_mask; /* Supported data unit size mask */
400 u8 key_size;
401 u8 reserved;
402 };
403 };
404
405 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
406 #define UFS_CRYPTO_KEY_MAX_SIZE 64
407 /* x-CRYPTOCFG - Crypto Configuration X */
408 union ufs_crypto_cfg_entry {
409 __le32 reg_val[32];
410 struct {
411 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
412 u8 data_unit_size;
413 u8 crypto_cap_idx;
414 u8 reserved_1;
415 u8 config_enable;
416 u8 reserved_multi_host;
417 u8 reserved_2;
418 u8 vsb[2];
419 u8 reserved_3[56];
420 };
421 };
422
423 /*
424 * Request Descriptor Definitions
425 */
426
427 /* To accommodate UFS2.0 required Command type */
428 enum {
429 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
430 };
431
432 enum {
433 UTP_SCSI_COMMAND = 0x00000000,
434 UTP_NATIVE_UFS_COMMAND = 0x10000000,
435 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
436 };
437
438 /* UTP Transfer Request Data Direction (DD) */
439 enum utp_data_direction {
440 UTP_NO_DATA_TRANSFER = 0,
441 UTP_HOST_TO_DEVICE = 1,
442 UTP_DEVICE_TO_HOST = 2,
443 };
444
445 /* Overall command status values */
446 enum utp_ocs {
447 OCS_SUCCESS = 0x0,
448 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
449 OCS_INVALID_PRDT_ATTR = 0x2,
450 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
451 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
452 OCS_PEER_COMM_FAILURE = 0x5,
453 OCS_ABORTED = 0x6,
454 OCS_FATAL_ERROR = 0x7,
455 OCS_DEVICE_FATAL_ERROR = 0x8,
456 OCS_INVALID_CRYPTO_CONFIG = 0x9,
457 OCS_GENERAL_CRYPTO_ERROR = 0xA,
458 OCS_INVALID_COMMAND_STATUS = 0x0F,
459 };
460
461 enum {
462 MASK_OCS = 0x0F,
463 };
464
465 /* The maximum length of the data byte count field in the PRDT is 256KB */
466 #define PRDT_DATA_BYTE_COUNT_MAX SZ_256K
467 /* The granularity of the data byte count field in the PRDT is 32-bit */
468 #define PRDT_DATA_BYTE_COUNT_PAD 4
469
470 /**
471 * struct ufshcd_sg_entry - UFSHCI PRD Entry
472 * @addr: Physical address; DW-0 and DW-1.
473 * @reserved: Reserved for future use DW-2
474 * @size: size of physical segment DW-3
475 */
476 struct ufshcd_sg_entry {
477 __le64 addr;
478 __le32 reserved;
479 __le32 size;
480 /*
481 * followed by variant-specific fields if
482 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
483 */
484 };
485
486 /**
487 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
488 * @command_upiu: Command UPIU Frame address
489 * @response_upiu: Response UPIU Frame address
490 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
491 * ufshcd_sg_entry's. Variant-specific fields may be present after each.
492 */
493 struct utp_transfer_cmd_desc {
494 u8 command_upiu[ALIGNED_UPIU_SIZE];
495 u8 response_upiu[ALIGNED_UPIU_SIZE];
496 u8 prd_table[];
497 };
498
499 /**
500 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
501 */
502 struct request_desc_header {
503 u8 cci;
504 u8 ehs_length;
505 #if defined(__BIG_ENDIAN)
506 u8 enable_crypto:1;
507 u8 reserved2:7;
508
509 u8 command_type:4;
510 u8 reserved1:1;
511 u8 data_direction:2;
512 u8 interrupt:1;
513 #elif defined(__LITTLE_ENDIAN)
514 u8 reserved2:7;
515 u8 enable_crypto:1;
516
517 u8 interrupt:1;
518 u8 data_direction:2;
519 u8 reserved1:1;
520 u8 command_type:4;
521 #else
522 #error
523 #endif
524
525 __le32 dunl;
526 u8 ocs;
527 u8 cds;
528 __le16 ldbc;
529 __le32 dunu;
530 };
531
532 static_assert(sizeof(struct request_desc_header) == 16);
533
534 /**
535 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
536 * @header: UTRD header DW-0 to DW-3
537 * @command_desc_base_addr: UCD base address DW 4-5
538 * @response_upiu_length: response UPIU length DW-6
539 * @response_upiu_offset: response UPIU offset DW-6
540 * @prd_table_length: Physical region descriptor length DW-7
541 * @prd_table_offset: Physical region descriptor offset DW-7
542 */
543 struct utp_transfer_req_desc {
544
545 /* DW 0-3 */
546 struct request_desc_header header;
547
548 /* DW 4-5*/
549 __le64 command_desc_base_addr;
550
551 /* DW 6 */
552 __le16 response_upiu_length;
553 __le16 response_upiu_offset;
554
555 /* DW 7 */
556 __le16 prd_table_length;
557 __le16 prd_table_offset;
558 };
559
560 /* MCQ Completion Queue Entry */
561 struct cq_entry {
562 /* DW 0-1 */
563 __le64 command_desc_base_addr;
564
565 /* DW 2 */
566 __le16 response_upiu_length;
567 __le16 response_upiu_offset;
568
569 /* DW 3 */
570 __le16 prd_table_length;
571 __le16 prd_table_offset;
572
573 /* DW 4 */
574 __le32 status;
575
576 /* DW 5-7 */
577 __le32 reserved[3];
578 };
579
580 static_assert(sizeof(struct cq_entry) == 32);
581
582 /*
583 * UTMRD structure.
584 */
585 struct utp_task_req_desc {
586 /* DW 0-3 */
587 struct request_desc_header header;
588
589 /* DW 4-11 - Task request UPIU structure */
590 struct {
591 struct utp_upiu_header req_header;
592 __be32 input_param1;
593 __be32 input_param2;
594 __be32 input_param3;
595 __be32 __reserved1[2];
596 } upiu_req;
597
598 /* DW 12-19 - Task Management Response UPIU structure */
599 struct {
600 struct utp_upiu_header rsp_header;
601 __be32 output_param1;
602 __be32 output_param2;
603 __be32 __reserved2[3];
604 } upiu_rsp;
605 };
606
607 #endif /* End of Header */
608
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