1 /*
2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
10 */
11
12 #ifndef __DRM_IPU_H__
13 #define __DRM_IPU_H__
14
15 #include <linux/types.h>
16 #include <linux/videodev2.h>
17 #include <linux/bitmap.h>
18 #include <linux/fb.h>
19 #include <linux/of.h>
20 #include <drm/drm_color_mgmt.h>
21 #include <media/v4l2-mediabus.h>
22 #include <video/videomode.h>
23
24 struct ipu_soc;
25
26 enum ipuv3_type {
27 IPUV3EX,
28 IPUV3M,
29 IPUV3H,
30 };
31
32 #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
33
34 /*
35 * Bitfield of Display Interface signal polarities.
36 */
37 struct ipu_di_signal_cfg {
38 unsigned data_pol:1; /* true = inverted */
39 unsigned clk_pol:1; /* true = rising edge */
40 unsigned enable_pol:1;
41
42 struct videomode mode;
43
44 u32 bus_format;
45 u32 v_to_h_sync;
46
47 #define IPU_DI_CLKMODE_SYNC (1 << 0)
48 #define IPU_DI_CLKMODE_EXT (1 << 1)
49 unsigned long clkflags;
50
51 u8 hsync_pin;
52 u8 vsync_pin;
53 };
54
55 /*
56 * Enumeration of CSI destinations
57 */
58 enum ipu_csi_dest {
59 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
60 IPU_CSI_DEST_IC, /* to Image Converter */
61 IPU_CSI_DEST_VDIC, /* to VDIC */
62 };
63
64 /*
65 * Enumeration of IPU rotation modes
66 */
67 #define IPU_ROT_BIT_VFLIP (1 << 0)
68 #define IPU_ROT_BIT_HFLIP (1 << 1)
69 #define IPU_ROT_BIT_90 (1 << 2)
70
71 enum ipu_rotate_mode {
72 IPU_ROTATE_NONE = 0,
73 IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
74 IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
75 IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
76 IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
77 IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
78 IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
79 IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
80 IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
81 };
82
83 /* 90-degree rotations require the IRT unit */
84 #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
85
86 enum ipu_color_space {
87 IPUV3_COLORSPACE_RGB,
88 IPUV3_COLORSPACE_YUV,
89 IPUV3_COLORSPACE_UNKNOWN,
90 };
91
92 /*
93 * Enumeration of VDI MOTION select
94 */
95 enum ipu_motion_sel {
96 MOTION_NONE = 0,
97 LOW_MOTION,
98 MED_MOTION,
99 HIGH_MOTION,
100 };
101
102 struct ipuv3_channel;
103
104 enum ipu_channel_irq {
105 IPU_IRQ_EOF = 0,
106 IPU_IRQ_NFACK = 64,
107 IPU_IRQ_NFB4EOF = 128,
108 IPU_IRQ_EOS = 192,
109 };
110
111 /*
112 * Enumeration of IDMAC channels
113 */
114 #define IPUV3_CHANNEL_CSI0 0
115 #define IPUV3_CHANNEL_CSI1 1
116 #define IPUV3_CHANNEL_CSI2 2
117 #define IPUV3_CHANNEL_CSI3 3
118 #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
119 /*
120 * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
121 * but the direct CSI->VDI linking is handled the same way as IDMAC
122 * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
123 * these channel names are used to support the direct CSI->VDI link.
124 */
125 #define IPUV3_CHANNEL_CSI_DIRECT 6
126 #define IPUV3_CHANNEL_CSI_VDI_PREV 7
127 #define IPUV3_CHANNEL_MEM_VDI_PREV 8
128 #define IPUV3_CHANNEL_MEM_VDI_CUR 9
129 #define IPUV3_CHANNEL_MEM_VDI_NEXT 10
130 #define IPUV3_CHANNEL_MEM_IC_PP 11
131 #define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
132 #define IPUV3_CHANNEL_VDI_MEM_RECENT 13
133 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
134 #define IPUV3_CHANNEL_G_MEM_IC_PP 15
135 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
136 #define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
137 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
138 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
139 #define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
140 #define IPUV3_CHANNEL_IC_PP_MEM 22
141 #define IPUV3_CHANNEL_MEM_BG_SYNC 23
142 #define IPUV3_CHANNEL_MEM_BG_ASYNC 24
143 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
144 #define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
145 #define IPUV3_CHANNEL_MEM_FG_SYNC 27
146 #define IPUV3_CHANNEL_MEM_DC_SYNC 28
147 #define IPUV3_CHANNEL_MEM_FG_ASYNC 29
148 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
149 #define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
150 #define IPUV3_CHANNEL_DC_MEM_READ 40
151 #define IPUV3_CHANNEL_MEM_DC_ASYNC 41
152 #define IPUV3_CHANNEL_MEM_DC_COMMAND 42
153 #define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
154 #define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
155 #define IPUV3_CHANNEL_MEM_ROT_ENC 45
156 #define IPUV3_CHANNEL_MEM_ROT_VF 46
157 #define IPUV3_CHANNEL_MEM_ROT_PP 47
158 #define IPUV3_CHANNEL_ROT_ENC_MEM 48
159 #define IPUV3_CHANNEL_ROT_VF_MEM 49
160 #define IPUV3_CHANNEL_ROT_PP_MEM 50
161 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
162 #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
163 #define IPUV3_NUM_CHANNELS 64
164
165 static inline int ipu_channel_alpha_channel(int ch_num)
166 {
167 switch (ch_num) {
168 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
169 return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
170 case IPUV3_CHANNEL_G_MEM_IC_PP:
171 return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
172 case IPUV3_CHANNEL_MEM_FG_SYNC:
173 return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
174 case IPUV3_CHANNEL_MEM_FG_ASYNC:
175 return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
176 case IPUV3_CHANNEL_MEM_BG_SYNC:
177 return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
178 case IPUV3_CHANNEL_MEM_BG_ASYNC:
179 return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
180 case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
181 return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
182 default:
183 return -EINVAL;
184 }
185 }
186
187 int ipu_map_irq(struct ipu_soc *ipu, int irq);
188 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
189 enum ipu_channel_irq irq);
190
191 #define IPU_IRQ_DP_SF_START (448 + 2)
192 #define IPU_IRQ_DP_SF_END (448 + 3)
193 #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
194 #define IPU_IRQ_DC_FC_0 (448 + 8)
195 #define IPU_IRQ_DC_FC_1 (448 + 9)
196 #define IPU_IRQ_DC_FC_2 (448 + 10)
197 #define IPU_IRQ_DC_FC_3 (448 + 11)
198 #define IPU_IRQ_DC_FC_4 (448 + 12)
199 #define IPU_IRQ_DC_FC_6 (448 + 13)
200 #define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
201 #define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
202
203 /*
204 * IPU Common functions
205 */
206 int ipu_get_num(struct ipu_soc *ipu);
207 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
208 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
209 void ipu_dump(struct ipu_soc *ipu);
210
211 /*
212 * IPU Image DMA Controller (idmac) functions
213 */
214 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
215 void ipu_idmac_put(struct ipuv3_channel *);
216
217 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
218 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
219 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
220 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
221 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
222
223 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
224 bool doublebuffer);
225 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
226 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
227 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
228 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
229 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
230 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
231 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
232 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
233
234 /*
235 * IPU Channel Parameter Memory (cpmem) functions
236 */
237 struct ipu_rgb {
238 struct fb_bitfield red;
239 struct fb_bitfield green;
240 struct fb_bitfield blue;
241 struct fb_bitfield transp;
242 int bits_per_pixel;
243 };
244
245 struct ipu_image {
246 struct v4l2_pix_format pix;
247 struct v4l2_rect rect;
248 dma_addr_t phys0;
249 dma_addr_t phys1;
250 /* chroma plane offset overrides */
251 u32 u_offset;
252 u32 v_offset;
253 };
254
255 void ipu_cpmem_zero(struct ipuv3_channel *ch);
256 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
257 void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
258 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
259 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
260 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
261 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
262 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
263 u32 pixelformat);
264 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
265 int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
266 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
267 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
268 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
269 enum ipu_rotate_mode rot);
270 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
271 const struct ipu_rgb *rgb);
272 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
273 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
274 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
275 unsigned int uv_stride,
276 unsigned int u_offset,
277 unsigned int v_offset);
278 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
279 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
280 void ipu_cpmem_dump(struct ipuv3_channel *ch);
281
282 /*
283 * IPU Display Controller (dc) functions
284 */
285 struct ipu_dc;
286 struct ipu_di;
287 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
288 void ipu_dc_put(struct ipu_dc *dc);
289 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
290 u32 pixel_fmt, u32 width);
291 void ipu_dc_enable(struct ipu_soc *ipu);
292 void ipu_dc_enable_channel(struct ipu_dc *dc);
293 void ipu_dc_disable_channel(struct ipu_dc *dc);
294 void ipu_dc_disable(struct ipu_soc *ipu);
295
296 /*
297 * IPU Display Interface (di) functions
298 */
299 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
300 void ipu_di_put(struct ipu_di *);
301 int ipu_di_disable(struct ipu_di *);
302 int ipu_di_enable(struct ipu_di *);
303 int ipu_di_get_num(struct ipu_di *);
304 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
305 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
306
307 /*
308 * IPU Display Multi FIFO Controller (dmfc) functions
309 */
310 struct dmfc_channel;
311 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
312 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
313 void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
314 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
315 void ipu_dmfc_put(struct dmfc_channel *dmfc);
316
317 /*
318 * IPU Display Processor (dp) functions
319 */
320 #define IPU_DP_FLOW_SYNC_BG 0
321 #define IPU_DP_FLOW_SYNC_FG 1
322 #define IPU_DP_FLOW_ASYNC0_BG 2
323 #define IPU_DP_FLOW_ASYNC0_FG 3
324 #define IPU_DP_FLOW_ASYNC1_BG 4
325 #define IPU_DP_FLOW_ASYNC1_FG 5
326
327 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
328 void ipu_dp_put(struct ipu_dp *);
329 int ipu_dp_enable(struct ipu_soc *ipu);
330 int ipu_dp_enable_channel(struct ipu_dp *dp);
331 void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
332 void ipu_dp_disable(struct ipu_soc *ipu);
333 int ipu_dp_setup_channel(struct ipu_dp *dp,
334 enum drm_color_encoding ycbcr_enc, enum drm_color_range range,
335 enum ipu_color_space in, enum ipu_color_space out);
336 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
337 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
338 bool bg_chan);
339
340 /*
341 * IPU Prefetch Resolve Gasket (prg) functions
342 */
343 int ipu_prg_max_active_channels(void);
344 bool ipu_prg_present(struct ipu_soc *ipu);
345 bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
346 uint64_t modifier);
347 int ipu_prg_enable(struct ipu_soc *ipu);
348 void ipu_prg_disable(struct ipu_soc *ipu);
349 void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
350 int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
351 unsigned int axi_id, unsigned int width,
352 unsigned int height, unsigned int stride,
353 u32 format, uint64_t modifier, unsigned long *eba);
354 bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan);
355
356 /*
357 * IPU CMOS Sensor Interface (csi) functions
358 */
359 struct ipu_csi;
360 int ipu_csi_init_interface(struct ipu_csi *csi,
361 const struct v4l2_mbus_config *mbus_cfg,
362 const struct v4l2_mbus_framefmt *infmt,
363 const struct v4l2_mbus_framefmt *outfmt);
364 bool ipu_csi_is_interlaced(struct ipu_csi *csi);
365 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
366 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
367 void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
368 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
369 u32 r_value, u32 g_value, u32 b_value,
370 u32 pix_clk);
371 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
372 struct v4l2_mbus_framefmt *mbus_fmt);
373 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
374 u32 max_ratio, u32 id);
375 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
376 int ipu_csi_enable(struct ipu_csi *csi);
377 int ipu_csi_disable(struct ipu_csi *csi);
378 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
379 void ipu_csi_put(struct ipu_csi *csi);
380 void ipu_csi_dump(struct ipu_csi *csi);
381
382 /*
383 * IPU Image Converter (ic) functions
384 */
385 enum ipu_ic_task {
386 IC_TASK_ENCODER,
387 IC_TASK_VIEWFINDER,
388 IC_TASK_POST_PROCESSOR,
389 IC_NUM_TASKS,
390 };
391
392 /*
393 * The parameters that describe a colorspace according to the
394 * Image Converter:
395 * - Y'CbCr encoding
396 * - quantization
397 * - "colorspace" (RGB or YUV).
398 */
399 struct ipu_ic_colorspace {
400 enum v4l2_ycbcr_encoding enc;
401 enum v4l2_quantization quant;
402 enum ipu_color_space cs;
403 };
404
405 static inline void
406 ipu_ic_fill_colorspace(struct ipu_ic_colorspace *ic_cs,
407 enum v4l2_ycbcr_encoding enc,
408 enum v4l2_quantization quant,
409 enum ipu_color_space cs)
410 {
411 ic_cs->enc = enc;
412 ic_cs->quant = quant;
413 ic_cs->cs = cs;
414 }
415
416 struct ipu_ic_csc_params {
417 s16 coeff[3][3]; /* signed 9-bit integer coefficients */
418 s16 offset[3]; /* signed 11+2-bit fixed point offset */
419 u8 scale:2; /* scale coefficients * 2^(scale-1) */
420 bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */
421 };
422
423 struct ipu_ic_csc {
424 struct ipu_ic_colorspace in_cs;
425 struct ipu_ic_colorspace out_cs;
426 struct ipu_ic_csc_params params;
427 };
428
429 struct ipu_ic;
430
431 int __ipu_ic_calc_csc(struct ipu_ic_csc *csc);
432 int ipu_ic_calc_csc(struct ipu_ic_csc *csc,
433 enum v4l2_ycbcr_encoding in_enc,
434 enum v4l2_quantization in_quant,
435 enum ipu_color_space in_cs,
436 enum v4l2_ycbcr_encoding out_enc,
437 enum v4l2_quantization out_quant,
438 enum ipu_color_space out_cs);
439 int ipu_ic_task_init(struct ipu_ic *ic,
440 const struct ipu_ic_csc *csc,
441 int in_width, int in_height,
442 int out_width, int out_height);
443 int ipu_ic_task_init_rsc(struct ipu_ic *ic,
444 const struct ipu_ic_csc *csc,
445 int in_width, int in_height,
446 int out_width, int out_height,
447 u32 rsc);
448 int ipu_ic_task_graphics_init(struct ipu_ic *ic,
449 const struct ipu_ic_colorspace *g_in_cs,
450 bool galpha_en, u32 galpha,
451 bool colorkey_en, u32 colorkey);
452 void ipu_ic_task_enable(struct ipu_ic *ic);
453 void ipu_ic_task_disable(struct ipu_ic *ic);
454 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
455 u32 width, u32 height, int burst_size,
456 enum ipu_rotate_mode rot);
457 int ipu_ic_enable(struct ipu_ic *ic);
458 int ipu_ic_disable(struct ipu_ic *ic);
459 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
460 void ipu_ic_put(struct ipu_ic *ic);
461 void ipu_ic_dump(struct ipu_ic *ic);
462
463 /*
464 * IPU Video De-Interlacer (vdi) functions
465 */
466 struct ipu_vdi;
467 void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
468 void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
469 void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
470 void ipu_vdi_unsetup(struct ipu_vdi *vdi);
471 int ipu_vdi_enable(struct ipu_vdi *vdi);
472 int ipu_vdi_disable(struct ipu_vdi *vdi);
473 struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
474 void ipu_vdi_put(struct ipu_vdi *vdi);
475
476 /*
477 * IPU Sensor Multiple FIFO Controller (SMFC) functions
478 */
479 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
480 void ipu_smfc_put(struct ipu_smfc *smfc);
481 int ipu_smfc_enable(struct ipu_smfc *smfc);
482 int ipu_smfc_disable(struct ipu_smfc *smfc);
483 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
484 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
485 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
486
487 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
488 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
489 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
490 bool hflip, bool vflip);
491 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
492 bool hflip, bool vflip);
493
494 struct ipu_client_platformdata {
495 int csi;
496 int di;
497 int dc;
498 int dp;
499 int dma[2];
500 struct device_node *of_node;
501 };
502
503 #endif /* __DRM_IPU_H__ */
504
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