1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
4 */
5
6 /*
7 * Device Tree for ARC HS Development Kit
8 */
9 /dts-v1/;
10
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
13
14 / {
15 model = "snps,hsdk";
16 compatible = "snps,hsdk";
17
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen {
22 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
23 };
24
25 aliases {
26 ethernet = &gmac;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "snps,archs38";
36 reg = <0>;
37 clocks = <&core_clk>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "snps,archs38";
43 reg = <1>;
44 clocks = <&core_clk>;
45 };
46
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "snps,archs38";
50 reg = <2>;
51 clocks = <&core_clk>;
52 };
53
54 cpu@3 {
55 device_type = "cpu";
56 compatible = "snps,archs38";
57 reg = <3>;
58 clocks = <&core_clk>;
59 };
60 };
61
62 input_clk: input-clk {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <33333333>;
66 };
67
68 reg_5v0: regulator-5v0 {
69 compatible = "regulator-fixed";
70
71 regulator-name = "5v0-supply";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 };
75
76 cpu_intc: cpu-interrupt-controller {
77 compatible = "snps,archs-intc";
78 interrupt-controller;
79 #interrupt-cells = <1>;
80 };
81
82 idu_intc: idu-interrupt-controller {
83 compatible = "snps,archs-idu-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 interrupt-parent = <&cpu_intc>;
87 };
88
89 arcpct: pct {
90 compatible = "snps,archs-pct";
91 interrupt-parent = <&cpu_intc>;
92 interrupts = <20>;
93 };
94
95 /* TIMER0 with interrupt for clockevent */
96 timer {
97 compatible = "snps,arc-timer";
98 interrupts = <16>;
99 interrupt-parent = <&cpu_intc>;
100 clocks = <&core_clk>;
101 };
102
103 /* 64-bit Global Free Running Counter */
104 gfrc {
105 compatible = "snps,archs-timer-gfrc";
106 clocks = <&core_clk>;
107 };
108
109 soc {
110 compatible = "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 interrupt-parent = <&idu_intc>;
114
115 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
116
117 cgu_rst: reset-controller@8a0 {
118 compatible = "snps,hsdk-reset";
119 #reset-cells = <1>;
120 reg = <0x8a0 0x4>, <0xff0 0x4>;
121 };
122
123 core_clk: core-clk@0 {
124 compatible = "snps,hsdk-core-pll-clock";
125 reg = <0x00 0x10>, <0x14b8 0x4>;
126 #clock-cells = <0>;
127 clocks = <&input_clk>;
128
129 /*
130 * Set initial core pll output frequency to 1GHz.
131 * It will be applied at the core pll driver probing
132 * on early boot.
133 */
134 assigned-clocks = <&core_clk>;
135 assigned-clock-rates = <1000000000>;
136 };
137
138 serial: serial@5000 {
139 compatible = "snps,dw-apb-uart";
140 reg = <0x5000 0x100>;
141 clock-frequency = <33330000>;
142 interrupts = <6>;
143 baud = <115200>;
144 reg-shift = <2>;
145 reg-io-width = <4>;
146 };
147
148 gmacclk: gmacclk {
149 compatible = "fixed-clock";
150 clock-frequency = <400000000>;
151 #clock-cells = <0>;
152 };
153
154 mmcclk_ciu: mmcclk-ciu {
155 compatible = "fixed-clock";
156 /*
157 * DW sdio controller has external ciu clock divider
158 * controlled via register in SDIO IP. Due to its
159 * unexpected default value (it should divide by 1
160 * but it divides by 8) SDIO IP uses wrong clock and
161 * works unstable (see STAR 9001204800)
162 * We switched to the minimum possible value of the
163 * divisor (div-by-2) in HSDK platform code.
164 * So add temporary fix and change clock frequency
165 * to 50000000 Hz until we fix dw sdio driver itself.
166 */
167 clock-frequency = <50000000>;
168 #clock-cells = <0>;
169 };
170
171 mmcclk_biu: mmcclk-biu {
172 compatible = "fixed-clock";
173 clock-frequency = <400000000>;
174 #clock-cells = <0>;
175 };
176
177 gpu_core_clk: gpu-core-clk {
178 compatible = "fixed-clock";
179 clock-frequency = <400000000>;
180 #clock-cells = <0>;
181 };
182
183 gpu_dma_clk: gpu-dma-clk {
184 compatible = "fixed-clock";
185 clock-frequency = <400000000>;
186 #clock-cells = <0>;
187 };
188
189 gpu_cfg_clk: gpu-cfg-clk {
190 compatible = "fixed-clock";
191 clock-frequency = <200000000>;
192 #clock-cells = <0>;
193 };
194
195 dmac_core_clk: dmac-core-clk {
196 compatible = "fixed-clock";
197 clock-frequency = <400000000>;
198 #clock-cells = <0>;
199 };
200
201 dmac_cfg_clk: dmac-gpu-cfg-clk {
202 compatible = "fixed-clock";
203 clock-frequency = <200000000>;
204 #clock-cells = <0>;
205 };
206
207 gmac: ethernet@8000 {
208 compatible = "snps,dwmac";
209 reg = <0x8000 0x2000>;
210 interrupts = <10>;
211 interrupt-names = "macirq";
212 phy-mode = "rgmii-id";
213 snps,pbl = <32>;
214 snps,multicast-filter-bins = <256>;
215 clocks = <&gmacclk>;
216 clock-names = "stmmaceth";
217 phy-handle = <&phy0>;
218 resets = <&cgu_rst HSDK_ETH_RESET>;
219 reset-names = "stmmaceth";
220 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
221 dma-coherent;
222
223 tx-fifo-depth = <4096>;
224 rx-fifo-depth = <4096>;
225
226 mdio {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "snps,dwmac-mdio";
230 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
231 reg = <0>;
232 };
233 };
234 };
235
236 usb@60000 {
237 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
238 reg = <0x60000 0x100>;
239 interrupts = <15>;
240 resets = <&cgu_rst HSDK_USB_RESET>;
241 dma-coherent;
242 };
243
244 usb@40000 {
245 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
246 reg = <0x40000 0x100>;
247 interrupts = <15>;
248 resets = <&cgu_rst HSDK_USB_RESET>;
249 dma-coherent;
250 };
251
252 mmc@a000 {
253 compatible = "altr,socfpga-dw-mshc";
254 reg = <0xa000 0x400>;
255 num-slots = <1>;
256 fifo-depth = <16>;
257 card-detect-delay = <200>;
258 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
259 clock-names = "biu", "ciu";
260 interrupts = <12>;
261 bus-width = <4>;
262 dma-coherent;
263 };
264
265 spi0: spi@20000 {
266 compatible = "snps,dw-apb-ssi";
267 reg = <0x20000 0x100>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 interrupts = <16>;
271 num-cs = <2>;
272 reg-io-width = <4>;
273 clocks = <&input_clk>;
274 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
275 <&creg_gpio 1 GPIO_ACTIVE_LOW>;
276
277 flash@0 {
278 compatible = "sst26wf016b", "jedec,spi-nor";
279 reg = <0>;
280 #address-cells = <1>;
281 #size-cells = <1>;
282 spi-max-frequency = <4000000>;
283 };
284
285 adc@1 {
286 compatible = "ti,adc108s102";
287 reg = <1>;
288 vref-supply = <®_5v0>;
289 spi-max-frequency = <1000000>;
290 };
291 };
292
293 creg_gpio: gpio@14b0 {
294 compatible = "snps,creg-gpio-hsdk";
295 reg = <0x14b0 0x4>;
296 gpio-controller;
297 #gpio-cells = <2>;
298 ngpios = <2>;
299 };
300
301 gpio: gpio@3000 {
302 compatible = "snps,dw-apb-gpio";
303 reg = <0x3000 0x20>;
304 #address-cells = <1>;
305 #size-cells = <0>;
306
307 gpio_port_a: gpio-controller@0 {
308 compatible = "snps,dw-apb-gpio-port";
309 gpio-controller;
310 #gpio-cells = <2>;
311 snps,nr-gpios = <24>;
312 reg = <0>;
313 };
314 };
315
316 gpu_3d: gpu@90000 {
317 compatible = "vivante,gc";
318 reg = <0x90000 0x4000>;
319 clocks = <&gpu_dma_clk>,
320 <&gpu_cfg_clk>,
321 <&gpu_core_clk>,
322 <&gpu_core_clk>;
323 clock-names = "bus", "reg", "core", "shader";
324 interrupts = <28>;
325 };
326
327 dmac: dmac@80000 {
328 compatible = "snps,axi-dma-1.01a";
329 reg = <0x80000 0x400>;
330 interrupts = <27>;
331 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
332 clock-names = "core-clk", "cfgr-clk";
333
334 dma-channels = <4>;
335 snps,dma-masters = <2>;
336 snps,data-width = <3>;
337 snps,block-size = <4096 4096 4096 4096>;
338 snps,priority = <0 1 2 3>;
339 snps,axi-max-burst-len = <16>;
340 };
341 };
342
343 memory@80000000 {
344 #address-cells = <2>;
345 #size-cells = <2>;
346 device_type = "memory";
347 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
348 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */
349 };
350 };
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