1 /*
2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun6i-rtc.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r40-ccu.h>
48 #include <dt-bindings/clock/sun8i-tcon-top.h>
49 #include <dt-bindings/reset/sun8i-r40-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/thermal/thermal.h>
52
53 / {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 interrupt-parent = <&gic>;
57
58 clocks {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 osc24M: osc24M {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <24000000>;
67 clock-accuracy = <50000>;
68 clock-output-names = "osc24M";
69 };
70
71 osc32k: osc32k {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <32768>;
75 clock-accuracy = <20000>;
76 clock-output-names = "ext-osc32k";
77 };
78 };
79
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu0: cpu@0 {
85 compatible = "arm,cortex-a7";
86 device_type = "cpu";
87 reg = <0>;
88 clocks = <&ccu CLK_CPU>;
89 clock-names = "cpu";
90 #cooling-cells = <2>;
91 };
92
93 cpu1: cpu@1 {
94 compatible = "arm,cortex-a7";
95 device_type = "cpu";
96 reg = <1>;
97 clocks = <&ccu CLK_CPU>;
98 clock-names = "cpu";
99 #cooling-cells = <2>;
100 };
101
102 cpu2: cpu@2 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 reg = <2>;
106 clocks = <&ccu CLK_CPU>;
107 clock-names = "cpu";
108 #cooling-cells = <2>;
109 };
110
111 cpu3: cpu@3 {
112 compatible = "arm,cortex-a7";
113 device_type = "cpu";
114 reg = <3>;
115 clocks = <&ccu CLK_CPU>;
116 clock-names = "cpu";
117 #cooling-cells = <2>;
118 };
119 };
120
121 de: display-engine {
122 compatible = "allwinner,sun8i-r40-display-engine";
123 allwinner,pipelines = <&mixer0>, <&mixer1>;
124 status = "disabled";
125 };
126
127 thermal-zones {
128 cpu_thermal: cpu0-thermal {
129 /* milliseconds */
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
133
134 trips {
135 cpu_hot_trip: cpu-hot {
136 temperature = <80000>;
137 hysteresis = <2000>;
138 type = "passive";
139 };
140
141 cpu_very_hot_trip: cpu-very-hot {
142 temperature = <115000>;
143 hysteresis = <0>;
144 type = "critical";
145 };
146 };
147
148 cooling-maps {
149 cpu-hot-limit {
150 trip = <&cpu_hot_trip>;
151 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
152 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
153 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
154 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
155 };
156 };
157 };
158
159 gpu_thermal: gpu-thermal {
160 /* milliseconds */
161 polling-delay-passive = <0>;
162 polling-delay = <0>;
163 thermal-sensors = <&ths 1>;
164 };
165 };
166
167 soc {
168 compatible = "simple-bus";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges;
172
173 display_clocks: clock@1000000 {
174 compatible = "allwinner,sun8i-r40-de2-clk",
175 "allwinner,sun8i-h3-de2-clk";
176 reg = <0x01000000 0x10000>;
177 clocks = <&ccu CLK_BUS_DE>,
178 <&ccu CLK_DE>;
179 clock-names = "bus",
180 "mod";
181 resets = <&ccu RST_BUS_DE>;
182 #clock-cells = <1>;
183 #reset-cells = <1>;
184 };
185
186 mixer0: mixer@1100000 {
187 compatible = "allwinner,sun8i-r40-de2-mixer-0";
188 reg = <0x01100000 0x100000>;
189 clocks = <&display_clocks CLK_BUS_MIXER0>,
190 <&display_clocks CLK_MIXER0>;
191 clock-names = "bus",
192 "mod";
193 resets = <&display_clocks RST_MIXER0>;
194
195 ports {
196 #address-cells = <1>;
197 #size-cells = <0>;
198
199 mixer0_out: port@1 {
200 reg = <1>;
201 mixer0_out_tcon_top: endpoint {
202 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
203 };
204 };
205 };
206 };
207
208 mixer1: mixer@1200000 {
209 compatible = "allwinner,sun8i-r40-de2-mixer-1";
210 reg = <0x01200000 0x100000>;
211 clocks = <&display_clocks CLK_BUS_MIXER1>,
212 <&display_clocks CLK_MIXER1>;
213 clock-names = "bus",
214 "mod";
215 resets = <&display_clocks RST_WB>;
216
217 ports {
218 #address-cells = <1>;
219 #size-cells = <0>;
220
221 mixer1_out: port@1 {
222 reg = <1>;
223 mixer1_out_tcon_top: endpoint {
224 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
225 };
226 };
227 };
228 };
229
230 deinterlace: deinterlace@1400000 {
231 compatible = "allwinner,sun8i-r40-deinterlace",
232 "allwinner,sun8i-h3-deinterlace";
233 reg = <0x01400000 0x20000>;
234 clocks = <&ccu CLK_BUS_DEINTERLACE>,
235 <&ccu CLK_DEINTERLACE>,
236 /*
237 * NOTE: Contrary to what datasheet claims,
238 * DRAM deinterlace gate doesn't exist and
239 * it's shared with CSI1.
240 */
241 <&ccu CLK_DRAM_CSI1>;
242 clock-names = "bus", "mod", "ram";
243 resets = <&ccu RST_BUS_DEINTERLACE>;
244 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
245 interconnects = <&mbus 9>;
246 interconnect-names = "dma-mem";
247 };
248
249 syscon: system-control@1c00000 {
250 compatible = "allwinner,sun8i-r40-system-control",
251 "allwinner,sun4i-a10-system-control";
252 reg = <0x01c00000 0x30>;
253 #address-cells = <1>;
254 #size-cells = <1>;
255 ranges;
256
257 sram_c: sram@1d00000 {
258 compatible = "mmio-sram";
259 reg = <0x01d00000 0xd0000>;
260 #address-cells = <1>;
261 #size-cells = <1>;
262 ranges = <0 0x01d00000 0xd0000>;
263
264 ve_sram: sram-section@0 {
265 compatible = "allwinner,sun8i-r40-sram-c1",
266 "allwinner,sun4i-a10-sram-c1";
267 reg = <0x000000 0x80000>;
268 };
269 };
270 };
271
272 nmi_intc: interrupt-controller@1c00030 {
273 compatible = "allwinner,sun7i-a20-sc-nmi";
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 reg = <0x01c00030 0x0c>;
277 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
278 };
279
280 dma: dma-controller@1c02000 {
281 compatible = "allwinner,sun8i-r40-dma",
282 "allwinner,sun50i-a64-dma";
283 reg = <0x01c02000 0x1000>;
284 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&ccu CLK_BUS_DMA>;
286 dma-channels = <16>;
287 dma-requests = <31>;
288 resets = <&ccu RST_BUS_DMA>;
289 #dma-cells = <1>;
290 };
291
292 spi0: spi@1c05000 {
293 compatible = "allwinner,sun8i-r40-spi",
294 "allwinner,sun8i-h3-spi";
295 reg = <0x01c05000 0x1000>;
296 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
298 clock-names = "ahb", "mod";
299 resets = <&ccu RST_BUS_SPI0>;
300 status = "disabled";
301 #address-cells = <1>;
302 #size-cells = <0>;
303 };
304
305 spi1: spi@1c06000 {
306 compatible = "allwinner,sun8i-r40-spi",
307 "allwinner,sun8i-h3-spi";
308 reg = <0x01c06000 0x1000>;
309 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
311 clock-names = "ahb", "mod";
312 resets = <&ccu RST_BUS_SPI1>;
313 status = "disabled";
314 #address-cells = <1>;
315 #size-cells = <0>;
316 };
317
318 csi0: csi@1c09000 {
319 compatible = "allwinner,sun8i-r40-csi0",
320 "allwinner,sun7i-a20-csi0";
321 reg = <0x01c09000 0x1000>;
322 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
324 <&ccu CLK_DRAM_CSI0>;
325 clock-names = "bus", "isp", "ram";
326 resets = <&ccu RST_BUS_CSI0>;
327 interconnects = <&mbus 5>;
328 interconnect-names = "dma-mem";
329 status = "disabled";
330 };
331
332 video-codec@1c0e000 {
333 compatible = "allwinner,sun8i-r40-video-engine";
334 reg = <0x01c0e000 0x1000>;
335 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
336 <&ccu CLK_DRAM_VE>;
337 clock-names = "ahb", "mod", "ram";
338 resets = <&ccu RST_BUS_VE>;
339 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
340 allwinner,sram = <&ve_sram 1>;
341 interconnects = <&mbus 4>;
342 interconnect-names = "dma-mem";
343 };
344
345 mmc0: mmc@1c0f000 {
346 compatible = "allwinner,sun8i-r40-mmc",
347 "allwinner,sun50i-a64-mmc";
348 reg = <0x01c0f000 0x1000>;
349 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
350 clock-names = "ahb", "mmc";
351 resets = <&ccu RST_BUS_MMC0>;
352 reset-names = "ahb";
353 pinctrl-0 = <&mmc0_pins>;
354 pinctrl-names = "default";
355 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
356 status = "disabled";
357 #address-cells = <1>;
358 #size-cells = <0>;
359 };
360
361 mmc1: mmc@1c10000 {
362 compatible = "allwinner,sun8i-r40-mmc",
363 "allwinner,sun50i-a64-mmc";
364 reg = <0x01c10000 0x1000>;
365 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
366 clock-names = "ahb", "mmc";
367 resets = <&ccu RST_BUS_MMC1>;
368 reset-names = "ahb";
369 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
370 status = "disabled";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 };
374
375 mmc2: mmc@1c11000 {
376 compatible = "allwinner,sun8i-r40-emmc",
377 "allwinner,sun50i-a64-emmc";
378 reg = <0x01c11000 0x1000>;
379 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
380 clock-names = "ahb", "mmc";
381 resets = <&ccu RST_BUS_MMC2>;
382 reset-names = "ahb";
383 pinctrl-0 = <&mmc2_pins>;
384 pinctrl-names = "default";
385 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
386 status = "disabled";
387 #address-cells = <1>;
388 #size-cells = <0>;
389 };
390
391 mmc3: mmc@1c12000 {
392 compatible = "allwinner,sun8i-r40-mmc",
393 "allwinner,sun50i-a64-mmc";
394 reg = <0x01c12000 0x1000>;
395 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
396 clock-names = "ahb", "mmc";
397 resets = <&ccu RST_BUS_MMC3>;
398 reset-names = "ahb";
399 pinctrl-0 = <&mmc3_pins>;
400 pinctrl-names = "default";
401 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
402 status = "disabled";
403 #address-cells = <1>;
404 #size-cells = <0>;
405 };
406
407 usbphy: phy@1c13400 {
408 compatible = "allwinner,sun8i-r40-usb-phy";
409 reg = <0x01c13400 0x14>,
410 <0x01c14800 0x4>,
411 <0x01c19800 0x4>,
412 <0x01c1c800 0x4>;
413 reg-names = "phy_ctrl",
414 "pmu0",
415 "pmu1",
416 "pmu2";
417 clocks = <&ccu CLK_USB_PHY0>,
418 <&ccu CLK_USB_PHY1>,
419 <&ccu CLK_USB_PHY2>;
420 clock-names = "usb0_phy",
421 "usb1_phy",
422 "usb2_phy";
423 resets = <&ccu RST_USB_PHY0>,
424 <&ccu RST_USB_PHY1>,
425 <&ccu RST_USB_PHY2>;
426 reset-names = "usb0_reset",
427 "usb1_reset",
428 "usb2_reset";
429 status = "disabled";
430 #phy-cells = <1>;
431 };
432
433 crypto: crypto@1c15000 {
434 compatible = "allwinner,sun8i-r40-crypto";
435 reg = <0x01c15000 0x1000>;
436 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
438 clock-names = "bus", "mod";
439 resets = <&ccu RST_BUS_CE>;
440 };
441
442 spi2: spi@1c17000 {
443 compatible = "allwinner,sun8i-r40-spi",
444 "allwinner,sun8i-h3-spi";
445 reg = <0x01c17000 0x1000>;
446 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
448 clock-names = "ahb", "mod";
449 resets = <&ccu RST_BUS_SPI2>;
450 status = "disabled";
451 #address-cells = <1>;
452 #size-cells = <0>;
453 };
454
455 ahci: sata@1c18000 {
456 compatible = "allwinner,sun8i-r40-ahci";
457 reg = <0x01c18000 0x1000>;
458 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
460 resets = <&ccu RST_BUS_SATA>;
461 reset-names = "ahci";
462 status = "disabled";
463 };
464
465 ehci1: usb@1c19000 {
466 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
467 reg = <0x01c19000 0x100>;
468 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&ccu CLK_BUS_EHCI1>;
470 resets = <&ccu RST_BUS_EHCI1>;
471 phys = <&usbphy 1>;
472 phy-names = "usb";
473 status = "disabled";
474 };
475
476 ohci1: usb@1c19400 {
477 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
478 reg = <0x01c19400 0x100>;
479 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&ccu CLK_BUS_OHCI1>,
481 <&ccu CLK_USB_OHCI1>;
482 resets = <&ccu RST_BUS_OHCI1>;
483 phys = <&usbphy 1>;
484 phy-names = "usb";
485 status = "disabled";
486 };
487
488 ehci2: usb@1c1c000 {
489 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
490 reg = <0x01c1c000 0x100>;
491 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&ccu CLK_BUS_EHCI2>;
493 resets = <&ccu RST_BUS_EHCI2>;
494 phys = <&usbphy 2>;
495 phy-names = "usb";
496 status = "disabled";
497 };
498
499 ohci2: usb@1c1c400 {
500 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
501 reg = <0x01c1c400 0x100>;
502 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&ccu CLK_BUS_OHCI2>,
504 <&ccu CLK_USB_OHCI2>;
505 resets = <&ccu RST_BUS_OHCI2>;
506 phys = <&usbphy 2>;
507 phy-names = "usb";
508 status = "disabled";
509 };
510
511 spi3: spi@1c1f000 {
512 compatible = "allwinner,sun8i-r40-spi",
513 "allwinner,sun8i-h3-spi";
514 reg = <0x01c1f000 0x1000>;
515 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
517 clock-names = "ahb", "mod";
518 resets = <&ccu RST_BUS_SPI3>;
519 status = "disabled";
520 #address-cells = <1>;
521 #size-cells = <0>;
522 };
523
524 ccu: clock@1c20000 {
525 compatible = "allwinner,sun8i-r40-ccu";
526 reg = <0x01c20000 0x400>;
527 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
528 clock-names = "hosc", "losc";
529 #clock-cells = <1>;
530 #reset-cells = <1>;
531 };
532
533 rtc: rtc@1c20400 {
534 compatible = "allwinner,sun8i-r40-rtc";
535 reg = <0x01c20400 0x400>;
536 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
537 clock-output-names = "osc32k", "osc32k-out";
538 clocks = <&osc32k>;
539 #clock-cells = <1>;
540 };
541
542 pio: pinctrl@1c20800 {
543 compatible = "allwinner,sun8i-r40-pinctrl";
544 reg = <0x01c20800 0x400>;
545 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
547 <&rtc CLK_OSC32K>;
548 clock-names = "apb", "hosc", "losc";
549 gpio-controller;
550 interrupt-controller;
551 #interrupt-cells = <3>;
552 #gpio-cells = <3>;
553
554 can_ph_pins: can-ph-pins {
555 pins = "PH20", "PH21";
556 function = "can";
557 };
558
559 can_pa_pins: can-pa-pins {
560 pins = "PA16", "PA17";
561 function = "can";
562 };
563
564 clk_out_a_pin: clk-out-a-pin {
565 pins = "PI12";
566 function = "clk_out_a";
567 };
568
569 /omit-if-no-ref/
570 csi0_8bits_pins: csi0-8bits-pins {
571 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
572 "PE6", "PE7", "PE8", "PE9", "PE10",
573 "PE11";
574 function = "csi0";
575 };
576
577 /omit-if-no-ref/
578 csi0_mclk_pin: csi0-mclk-pin {
579 pins = "PE1";
580 function = "csi0";
581 };
582
583 gmac_rgmii_pins: gmac-rgmii-pins {
584 pins = "PA0", "PA1", "PA2", "PA3",
585 "PA4", "PA5", "PA6", "PA7",
586 "PA8", "PA10", "PA11", "PA12",
587 "PA13", "PA15", "PA16";
588 function = "gmac";
589 /*
590 * data lines in RGMII mode use DDR mode
591 * and need a higher signal drive strength
592 */
593 drive-strength = <40>;
594 };
595
596 i2c0_pins: i2c0-pins {
597 pins = "PB0", "PB1";
598 function = "i2c0";
599 };
600
601 i2c1_pins: i2c1-pins {
602 pins = "PB18", "PB19";
603 function = "i2c1";
604 };
605
606 i2c2_pins: i2c2-pins {
607 pins = "PB20", "PB21";
608 function = "i2c2";
609 };
610
611 i2c3_pins: i2c3-pins {
612 pins = "PI0", "PI1";
613 function = "i2c3";
614 };
615
616 i2c4_pins: i2c4-pins {
617 pins = "PI2", "PI3";
618 function = "i2c4";
619 };
620
621 ir0_pins: ir0-pins {
622 pins = "PB4";
623 function = "ir0";
624 };
625
626 ir1_pins: ir1-pins {
627 pins = "PB23";
628 function = "ir1";
629 };
630
631 mmc0_pins: mmc0-pins {
632 pins = "PF0", "PF1", "PF2",
633 "PF3", "PF4", "PF5";
634 function = "mmc0";
635 drive-strength = <30>;
636 bias-pull-up;
637 };
638
639 mmc1_pg_pins: mmc1-pg-pins {
640 pins = "PG0", "PG1", "PG2",
641 "PG3", "PG4", "PG5";
642 function = "mmc1";
643 drive-strength = <30>;
644 bias-pull-up;
645 };
646
647 mmc2_pins: mmc2-pins {
648 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
649 "PC10", "PC11", "PC12", "PC13", "PC14",
650 "PC15", "PC24";
651 function = "mmc2";
652 drive-strength = <30>;
653 bias-pull-up;
654 };
655
656 /omit-if-no-ref/
657 mmc3_pins: mmc3-pins {
658 pins = "PI4", "PI5", "PI6",
659 "PI7", "PI8", "PI9";
660 function = "mmc3";
661 drive-strength = <30>;
662 bias-pull-up;
663 };
664
665 /omit-if-no-ref/
666 spi0_pc_pins: spi0-pc-pins {
667 pins = "PC0", "PC1", "PC2";
668 function = "spi0";
669 };
670
671 /omit-if-no-ref/
672 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
673 pins = "PC23";
674 function = "spi0";
675 };
676
677 /omit-if-no-ref/
678 spi1_pi_pins: spi1-pi-pins {
679 pins = "PI17", "PI18", "PI19";
680 function = "spi1";
681 };
682
683 /omit-if-no-ref/
684 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
685 pins = "PI16";
686 function = "spi1";
687 };
688
689 /omit-if-no-ref/
690 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
691 pins = "PI15";
692 function = "spi1";
693 };
694
695 /omit-if-no-ref/
696 uart0_pb_pins: uart0-pb-pins {
697 pins = "PB22", "PB23";
698 function = "uart0";
699 };
700
701 /omit-if-no-ref/
702 uart2_pi_pins: uart2-pi-pins {
703 pins = "PI18", "PI19";
704 function = "uart2";
705 };
706
707 /omit-if-no-ref/
708 uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
709 pins = "PI16", "PI17";
710 function = "uart2";
711 };
712
713 /omit-if-no-ref/
714 uart3_pg_pins: uart3-pg-pins {
715 pins = "PG6", "PG7";
716 function = "uart3";
717 };
718
719 /omit-if-no-ref/
720 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
721 pins = "PG8", "PG9";
722 function = "uart3";
723 };
724
725 /omit-if-no-ref/
726 uart4_pg_pins: uart4-pg-pins {
727 pins = "PG10", "PG11";
728 function = "uart4";
729 };
730
731 /omit-if-no-ref/
732 uart5_ph_pins: uart5-ph-pins {
733 pins = "PH6", "PH7";
734 function = "uart5";
735 };
736
737 /omit-if-no-ref/
738 uart7_pi_pins: uart7-pi-pins {
739 pins = "PI20", "PI21";
740 function = "uart7";
741 };
742 };
743
744 timer@1c20c00 {
745 compatible = "allwinner,sun4i-a10-timer";
746 reg = <0x01c20c00 0x90>;
747 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&osc24M>;
754 };
755
756 wdt: watchdog@1c20c90 {
757 compatible = "allwinner,sun4i-a10-wdt";
758 reg = <0x01c20c90 0x10>;
759 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&osc24M>;
761 };
762
763 ir0: ir@1c21800 {
764 compatible = "allwinner,sun8i-r40-ir",
765 "allwinner,sun6i-a31-ir";
766 reg = <0x01c21800 0x400>;
767 pinctrl-0 = <&ir0_pins>;
768 pinctrl-names = "default";
769 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
770 clock-names = "apb", "ir";
771 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
772 resets = <&ccu RST_BUS_IR0>;
773 status = "disabled";
774 };
775
776 ir1: ir@1c21c00 {
777 compatible = "allwinner,sun8i-r40-ir",
778 "allwinner,sun6i-a31-ir";
779 reg = <0x01c21c00 0x400>;
780 pinctrl-0 = <&ir1_pins>;
781 pinctrl-names = "default";
782 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
783 clock-names = "apb", "ir";
784 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
785 resets = <&ccu RST_BUS_IR1>;
786 status = "disabled";
787 };
788
789 i2s0: i2s@1c22000 {
790 #sound-dai-cells = <0>;
791 compatible = "allwinner,sun8i-r40-i2s",
792 "allwinner,sun8i-h3-i2s";
793 reg = <0x01c22000 0x400>;
794 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
796 clock-names = "apb", "mod";
797 resets = <&ccu RST_BUS_I2S0>;
798 dmas = <&dma 3>, <&dma 3>;
799 dma-names = "rx", "tx";
800 };
801
802 i2s1: i2s@1c22400 {
803 #sound-dai-cells = <0>;
804 compatible = "allwinner,sun8i-r40-i2s",
805 "allwinner,sun8i-h3-i2s";
806 reg = <0x01c22400 0x400>;
807 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
809 clock-names = "apb", "mod";
810 resets = <&ccu RST_BUS_I2S1>;
811 dmas = <&dma 4>, <&dma 4>;
812 dma-names = "rx", "tx";
813 };
814
815 i2s2: i2s@1c22800 {
816 #sound-dai-cells = <0>;
817 compatible = "allwinner,sun8i-r40-i2s",
818 "allwinner,sun8i-h3-i2s";
819 reg = <0x01c22800 0x400>;
820 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
822 clock-names = "apb", "mod";
823 resets = <&ccu RST_BUS_I2S2>;
824 dmas = <&dma 6>, <&dma 6>;
825 dma-names = "rx", "tx";
826 };
827
828 ths: thermal-sensor@1c24c00 {
829 compatible = "allwinner,sun8i-r40-ths";
830 reg = <0x01c24c00 0x100>;
831 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
832 clock-names = "bus", "mod";
833 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
834 resets = <&ccu RST_BUS_THS>;
835 /* TODO: add nvmem-cells for calibration */
836 #thermal-sensor-cells = <1>;
837 };
838
839 uart0: serial@1c28000 {
840 compatible = "snps,dw-apb-uart";
841 reg = <0x01c28000 0x400>;
842 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
843 reg-shift = <2>;
844 reg-io-width = <4>;
845 clocks = <&ccu CLK_BUS_UART0>;
846 resets = <&ccu RST_BUS_UART0>;
847 status = "disabled";
848 };
849
850 uart1: serial@1c28400 {
851 compatible = "snps,dw-apb-uart";
852 reg = <0x01c28400 0x400>;
853 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
854 reg-shift = <2>;
855 reg-io-width = <4>;
856 clocks = <&ccu CLK_BUS_UART1>;
857 resets = <&ccu RST_BUS_UART1>;
858 status = "disabled";
859 };
860
861 uart2: serial@1c28800 {
862 compatible = "snps,dw-apb-uart";
863 reg = <0x01c28800 0x400>;
864 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
865 reg-shift = <2>;
866 reg-io-width = <4>;
867 clocks = <&ccu CLK_BUS_UART2>;
868 resets = <&ccu RST_BUS_UART2>;
869 status = "disabled";
870 };
871
872 uart3: serial@1c28c00 {
873 compatible = "snps,dw-apb-uart";
874 reg = <0x01c28c00 0x400>;
875 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
876 reg-shift = <2>;
877 reg-io-width = <4>;
878 clocks = <&ccu CLK_BUS_UART3>;
879 resets = <&ccu RST_BUS_UART3>;
880 status = "disabled";
881 };
882
883 uart4: serial@1c29000 {
884 compatible = "snps,dw-apb-uart";
885 reg = <0x01c29000 0x400>;
886 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
887 reg-shift = <2>;
888 reg-io-width = <4>;
889 clocks = <&ccu CLK_BUS_UART4>;
890 resets = <&ccu RST_BUS_UART4>;
891 status = "disabled";
892 };
893
894 uart5: serial@1c29400 {
895 compatible = "snps,dw-apb-uart";
896 reg = <0x01c29400 0x400>;
897 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
898 reg-shift = <2>;
899 reg-io-width = <4>;
900 clocks = <&ccu CLK_BUS_UART5>;
901 resets = <&ccu RST_BUS_UART5>;
902 status = "disabled";
903 };
904
905 uart6: serial@1c29800 {
906 compatible = "snps,dw-apb-uart";
907 reg = <0x01c29800 0x400>;
908 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
909 reg-shift = <2>;
910 reg-io-width = <4>;
911 clocks = <&ccu CLK_BUS_UART6>;
912 resets = <&ccu RST_BUS_UART6>;
913 status = "disabled";
914 };
915
916 uart7: serial@1c29c00 {
917 compatible = "snps,dw-apb-uart";
918 reg = <0x01c29c00 0x400>;
919 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
920 reg-shift = <2>;
921 reg-io-width = <4>;
922 clocks = <&ccu CLK_BUS_UART7>;
923 resets = <&ccu RST_BUS_UART7>;
924 status = "disabled";
925 };
926
927 i2c0: i2c@1c2ac00 {
928 compatible = "allwinner,sun6i-a31-i2c";
929 reg = <0x01c2ac00 0x400>;
930 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&ccu CLK_BUS_I2C0>;
932 resets = <&ccu RST_BUS_I2C0>;
933 pinctrl-0 = <&i2c0_pins>;
934 pinctrl-names = "default";
935 status = "disabled";
936 #address-cells = <1>;
937 #size-cells = <0>;
938 };
939
940 i2c1: i2c@1c2b000 {
941 compatible = "allwinner,sun6i-a31-i2c";
942 reg = <0x01c2b000 0x400>;
943 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&ccu CLK_BUS_I2C1>;
945 resets = <&ccu RST_BUS_I2C1>;
946 pinctrl-0 = <&i2c1_pins>;
947 pinctrl-names = "default";
948 status = "disabled";
949 #address-cells = <1>;
950 #size-cells = <0>;
951 };
952
953 i2c2: i2c@1c2b400 {
954 compatible = "allwinner,sun6i-a31-i2c";
955 reg = <0x01c2b400 0x400>;
956 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&ccu CLK_BUS_I2C2>;
958 resets = <&ccu RST_BUS_I2C2>;
959 pinctrl-0 = <&i2c2_pins>;
960 pinctrl-names = "default";
961 status = "disabled";
962 #address-cells = <1>;
963 #size-cells = <0>;
964 };
965
966 i2c3: i2c@1c2b800 {
967 compatible = "allwinner,sun6i-a31-i2c";
968 reg = <0x01c2b800 0x400>;
969 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&ccu CLK_BUS_I2C3>;
971 resets = <&ccu RST_BUS_I2C3>;
972 pinctrl-0 = <&i2c3_pins>;
973 pinctrl-names = "default";
974 status = "disabled";
975 #address-cells = <1>;
976 #size-cells = <0>;
977 };
978
979 can0: can@1c2bc00 {
980 compatible = "allwinner,sun8i-r40-can";
981 reg = <0x01c2bc00 0x400>;
982 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&ccu CLK_BUS_CAN>;
984 resets = <&ccu RST_BUS_CAN>;
985 status = "disabled";
986 };
987
988 i2c4: i2c@1c2c000 {
989 compatible = "allwinner,sun6i-a31-i2c";
990 reg = <0x01c2c000 0x400>;
991 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&ccu CLK_BUS_I2C4>;
993 resets = <&ccu RST_BUS_I2C4>;
994 pinctrl-0 = <&i2c4_pins>;
995 pinctrl-names = "default";
996 status = "disabled";
997 #address-cells = <1>;
998 #size-cells = <0>;
999 };
1000
1001 mali: gpu@1c40000 {
1002 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
1003 reg = <0x01c40000 0x10000>;
1004 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1010 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1011 interrupt-names = "gp",
1012 "gpmmu",
1013 "pp0",
1014 "ppmmu0",
1015 "pp1",
1016 "ppmmu1",
1017 "pmu";
1018 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1019 clock-names = "bus", "core";
1020 resets = <&ccu RST_BUS_GPU>;
1021 };
1022
1023 gmac: ethernet@1c50000 {
1024 compatible = "allwinner,sun8i-r40-gmac";
1025 syscon = <&ccu>;
1026 reg = <0x01c50000 0x10000>;
1027 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1028 interrupt-names = "macirq";
1029 resets = <&ccu RST_BUS_GMAC>;
1030 reset-names = "stmmaceth";
1031 clocks = <&ccu CLK_BUS_GMAC>;
1032 clock-names = "stmmaceth";
1033 status = "disabled";
1034
1035 gmac_mdio: mdio {
1036 compatible = "snps,dwmac-mdio";
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039 };
1040 };
1041
1042 mbus: dram-controller@1c62000 {
1043 compatible = "allwinner,sun8i-r40-mbus";
1044 reg = <0x01c62000 0x1000>;
1045 clocks = <&ccu 155>;
1046 #address-cells = <1>;
1047 #size-cells = <1>;
1048 dma-ranges = <0x00000000 0x40000000 0x80000000>;
1049 #interconnect-cells = <1>;
1050 };
1051
1052 tcon_top: tcon-top@1c70000 {
1053 compatible = "allwinner,sun8i-r40-tcon-top";
1054 reg = <0x01c70000 0x1000>;
1055 clocks = <&ccu CLK_BUS_TCON_TOP>,
1056 <&ccu CLK_TCON_TV0>,
1057 <&ccu CLK_TVE0>,
1058 <&ccu CLK_TCON_TV1>,
1059 <&ccu CLK_TVE1>,
1060 <&ccu CLK_DSI_DPHY>;
1061 clock-names = "bus",
1062 "tcon-tv0",
1063 "tve0",
1064 "tcon-tv1",
1065 "tve1",
1066 "dsi";
1067 clock-output-names = "tcon-top-tv0",
1068 "tcon-top-tv1",
1069 "tcon-top-dsi";
1070 resets = <&ccu RST_BUS_TCON_TOP>;
1071 #clock-cells = <1>;
1072
1073 ports {
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1076
1077 tcon_top_mixer0_in: port@0 {
1078 reg = <0>;
1079
1080 tcon_top_mixer0_in_mixer0: endpoint {
1081 remote-endpoint = <&mixer0_out_tcon_top>;
1082 };
1083 };
1084
1085 tcon_top_mixer0_out: port@1 {
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1088 reg = <1>;
1089
1090 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
1091 reg = <0>;
1092 };
1093
1094 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
1095 reg = <1>;
1096 };
1097
1098 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
1099 reg = <2>;
1100 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
1101 };
1102
1103 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
1104 reg = <3>;
1105 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
1106 };
1107 };
1108
1109 tcon_top_mixer1_in: port@2 {
1110 #address-cells = <1>;
1111 #size-cells = <0>;
1112 reg = <2>;
1113
1114 tcon_top_mixer1_in_mixer1: endpoint@1 {
1115 reg = <1>;
1116 remote-endpoint = <&mixer1_out_tcon_top>;
1117 };
1118 };
1119
1120 tcon_top_mixer1_out: port@3 {
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 reg = <3>;
1124
1125 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1126 reg = <0>;
1127 };
1128
1129 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
1130 reg = <1>;
1131 };
1132
1133 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
1134 reg = <2>;
1135 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
1136 };
1137
1138 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
1139 reg = <3>;
1140 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
1141 };
1142 };
1143
1144 tcon_top_hdmi_in: port@4 {
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 reg = <4>;
1148
1149 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
1150 reg = <0>;
1151 remote-endpoint = <&tcon_tv0_out_tcon_top>;
1152 };
1153
1154 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
1155 reg = <1>;
1156 remote-endpoint = <&tcon_tv1_out_tcon_top>;
1157 };
1158 };
1159
1160 tcon_top_hdmi_out: port@5 {
1161 reg = <5>;
1162
1163 tcon_top_hdmi_out_hdmi: endpoint {
1164 remote-endpoint = <&hdmi_in_tcon_top>;
1165 };
1166 };
1167 };
1168 };
1169
1170 tcon_tv0: lcd-controller@1c73000 {
1171 compatible = "allwinner,sun8i-r40-tcon-tv";
1172 reg = <0x01c73000 0x1000>;
1173 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1174 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
1175 clock-names = "ahb", "tcon-ch1";
1176 resets = <&ccu RST_BUS_TCON_TV0>;
1177 reset-names = "lcd";
1178 status = "disabled";
1179
1180 ports {
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1183
1184 tcon_tv0_in: port@0 {
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1187 reg = <0>;
1188
1189 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1190 reg = <0>;
1191 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
1192 };
1193
1194 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
1195 reg = <1>;
1196 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
1197 };
1198 };
1199
1200 tcon_tv0_out: port@1 {
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1203 reg = <1>;
1204
1205 tcon_tv0_out_tcon_top: endpoint@1 {
1206 reg = <1>;
1207 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
1208 };
1209 };
1210 };
1211 };
1212
1213 tcon_tv1: lcd-controller@1c74000 {
1214 compatible = "allwinner,sun8i-r40-tcon-tv";
1215 reg = <0x01c74000 0x1000>;
1216 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1217 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
1218 clock-names = "ahb", "tcon-ch1";
1219 resets = <&ccu RST_BUS_TCON_TV1>;
1220 reset-names = "lcd";
1221 status = "disabled";
1222
1223 ports {
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226
1227 tcon_tv1_in: port@0 {
1228 #address-cells = <1>;
1229 #size-cells = <0>;
1230 reg = <0>;
1231
1232 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1233 reg = <0>;
1234 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
1235 };
1236
1237 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
1238 reg = <1>;
1239 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
1240 };
1241 };
1242
1243 tcon_tv1_out: port@1 {
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1246 reg = <1>;
1247
1248 tcon_tv1_out_tcon_top: endpoint@1 {
1249 reg = <1>;
1250 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
1251 };
1252 };
1253 };
1254 };
1255
1256 gic: interrupt-controller@1c81000 {
1257 compatible = "arm,gic-400";
1258 reg = <0x01c81000 0x1000>,
1259 <0x01c82000 0x2000>,
1260 <0x01c84000 0x2000>,
1261 <0x01c86000 0x2000>;
1262 interrupt-controller;
1263 #interrupt-cells = <3>;
1264 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1265 };
1266
1267 hdmi: hdmi@1ee0000 {
1268 compatible = "allwinner,sun8i-r40-dw-hdmi",
1269 "allwinner,sun8i-a83t-dw-hdmi";
1270 reg = <0x01ee0000 0x10000>;
1271 reg-io-width = <1>;
1272 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
1274 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1275 clock-names = "iahb", "isfr", "tmds", "cec";
1276 resets = <&ccu RST_BUS_HDMI1>;
1277 reset-names = "ctrl";
1278 phys = <&hdmi_phy>;
1279 phy-names = "phy";
1280 status = "disabled";
1281
1282 ports {
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285
1286 hdmi_in: port@0 {
1287 reg = <0>;
1288
1289 hdmi_in_tcon_top: endpoint {
1290 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
1291 };
1292 };
1293
1294 hdmi_out: port@1 {
1295 reg = <1>;
1296 };
1297 };
1298 };
1299
1300 hdmi_phy: hdmi-phy@1ef0000 {
1301 compatible = "allwinner,sun8i-r40-hdmi-phy";
1302 reg = <0x01ef0000 0x10000>;
1303 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1304 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1305 clock-names = "bus", "mod", "pll-0", "pll-1";
1306 resets = <&ccu RST_BUS_HDMI0>;
1307 reset-names = "phy";
1308 #phy-cells = <0>;
1309 };
1310 };
1311
1312 pmu {
1313 compatible = "arm,cortex-a7-pmu";
1314 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1315 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1318 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1319 };
1320
1321 timer {
1322 compatible = "arm,armv7-timer";
1323 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1324 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1325 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1326 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1327 };
1328 };
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