1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014 Carlo Caione <carlo@caione.org>
4 */
5
6 #include "meson.dtsi"
7
8 / {
9 model = "Amlogic Meson6 SoC";
10 compatible = "amlogic,meson6";
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu@200 {
17 device_type = "cpu";
18 compatible = "arm,cortex-a9";
19 next-level-cache = <&L2>;
20 reg = <0x200>;
21 };
22
23 cpu@201 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a9";
26 next-level-cache = <&L2>;
27 reg = <0x201>;
28 };
29 };
30
31 apb2: bus@d0000000 {
32 compatible = "simple-bus";
33 reg = <0xd0000000 0x40000>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges = <0x0 0xd0000000 0x40000>;
37 };
38
39 clk81: clk@0 {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <200000000>;
43 };
44 }; /* end of / */
45
46 &efuse {
47 status = "disabled";
48 };
49
50 &timer_abcde {
51 clocks = <&xtal>, <&clk81>;
52 clock-names = "xtal", "pclk";
53 };
54
55 &uart_AO {
56 clocks = <&xtal>, <&clk81>, <&clk81>;
57 clock-names = "xtal", "pclk", "baud";
58 };
59
60 &uart_A {
61 clocks = <&xtal>, <&clk81>, <&clk81>;
62 clock-names = "xtal", "pclk", "baud";
63 };
64
65 &uart_B {
66 clocks = <&xtal>, <&clk81>, <&clk81>;
67 clock-names = "xtal", "pclk", "baud";
68 };
69
70 &uart_C {
71 clocks = <&xtal>, <&clk81>, <&clk81>;
72 clock-names = "xtal", "pclk", "baud";
73 };
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