1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HiSilicon Ltd. Hi3620 SoC
4 *
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
7 *
8 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
9 */
10
11 #include <dt-bindings/clock/hi3620-clock.h>
12
13 / {
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 serial0 = &uart0;
19 serial1 = &uart1;
20 serial2 = &uart2;
21 serial3 = &uart3;
22 serial4 = &uart4;
23 };
24
25 pclk: clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35 enable-method = "hisilicon,hi3620-smp";
36
37 cpu@0 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a9";
40 reg = <0x0>;
41 next-level-cache = <&L2>;
42 };
43
44 cpu@1 {
45 compatible = "arm,cortex-a9";
46 device_type = "cpu";
47 reg = <1>;
48 next-level-cache = <&L2>;
49 };
50
51 cpu@2 {
52 compatible = "arm,cortex-a9";
53 device_type = "cpu";
54 reg = <2>;
55 next-level-cache = <&L2>;
56 };
57
58 cpu@3 {
59 compatible = "arm,cortex-a9";
60 device_type = "cpu";
61 reg = <3>;
62 next-level-cache = <&L2>;
63 };
64 };
65
66 amba-bus {
67
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
72 ranges = <0 0xfc000000 0x2000000>;
73
74 L2: cache-controller {
75 compatible = "arm,pl310-cache";
76 reg = <0x100000 0x100000>;
77 interrupts = <0 15 4>;
78 cache-unified;
79 cache-level = <2>;
80 };
81
82 gic: interrupt-controller@1000 {
83 compatible = "arm,cortex-a9-gic";
84 #interrupt-cells = <3>;
85 #address-cells = <0>;
86 interrupt-controller;
87 /* gic dist base, gic cpu base */
88 reg = <0x1000 0x1000>, <0x100 0x100>;
89 };
90
91 sysctrl: system-controller@802000 {
92 compatible = "hisilicon,sysctrl", "syscon";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x802000 0x1000>;
96 reg = <0x802000 0x1000>;
97
98 smp-offset = <0x31c>;
99 resume-offset = <0x308>;
100 reboot-offset = <0x4>;
101
102 clock: clock@0 {
103 compatible = "hisilicon,hi3620-clock";
104 reg = <0 0x10000>;
105 #clock-cells = <1>;
106 };
107 };
108
109 dual_timer0: dual_timer@800000 {
110 compatible = "arm,sp804", "arm,primecell";
111 reg = <0x800000 0x1000>;
112 /* timer00 & timer01 */
113 interrupts = <0 0 4>, <0 1 4>;
114 clocks = <&clock HI3620_TIMER0_MUX>,
115 <&clock HI3620_TIMER1_MUX>,
116 <&clock HI3620_TIMER0_MUX>;
117 clock-names = "timer0clk", "timer1clk", "apb_pclk";
118 status = "disabled";
119 };
120
121 dual_timer1: dual_timer@801000 {
122 compatible = "arm,sp804", "arm,primecell";
123 reg = <0x801000 0x1000>;
124 /* timer10 & timer11 */
125 interrupts = <0 2 4>, <0 3 4>;
126 clocks = <&clock HI3620_TIMER2_MUX>,
127 <&clock HI3620_TIMER3_MUX>,
128 <&clock HI3620_TIMER2_MUX>;
129 clock-names = "timer0clk", "timer1clk", "apb_pclk";
130 status = "disabled";
131 };
132
133 dual_timer2: dual_timer@a01000 {
134 compatible = "arm,sp804", "arm,primecell";
135 reg = <0xa01000 0x1000>;
136 /* timer20 & timer21 */
137 interrupts = <0 4 4>, <0 5 4>;
138 clocks = <&clock HI3620_TIMER4_MUX>,
139 <&clock HI3620_TIMER5_MUX>,
140 <&clock HI3620_TIMER4_MUX>;
141 clock-names = "timer0lck", "timer1clk", "apb_pclk";
142 status = "disabled";
143 };
144
145 dual_timer3: dual_timer@a02000 {
146 compatible = "arm,sp804", "arm,primecell";
147 reg = <0xa02000 0x1000>;
148 /* timer30 & timer31 */
149 interrupts = <0 6 4>, <0 7 4>;
150 clocks = <&clock HI3620_TIMER6_MUX>,
151 <&clock HI3620_TIMER7_MUX>,
152 <&clock HI3620_TIMER6_MUX>;
153 clock-names = "timer0clk", "timer1clk", "apb_pclk";
154 status = "disabled";
155 };
156
157 dual_timer4: dual_timer@a03000 {
158 compatible = "arm,sp804", "arm,primecell";
159 reg = <0xa03000 0x1000>;
160 /* timer40 & timer41 */
161 interrupts = <0 96 4>, <0 97 4>;
162 clocks = <&clock HI3620_TIMER8_MUX>,
163 <&clock HI3620_TIMER9_MUX>,
164 <&clock HI3620_TIMER8_MUX>;
165 clock-names = "timer0clk", "timer1clk", "apb_pclk";
166 status = "disabled";
167 };
168
169 timer5: timer@600 {
170 compatible = "arm,cortex-a9-twd-timer";
171 reg = <0x600 0x20>;
172 interrupts = <1 13 0xf01>;
173 };
174
175 uart0: serial@b00000 {
176 compatible = "arm,pl011", "arm,primecell";
177 reg = <0xb00000 0x1000>;
178 interrupts = <0 20 4>;
179 clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>;
180 clock-names = "uartclk", "apb_pclk";
181 status = "disabled";
182 };
183
184 uart1: serial@b01000 {
185 compatible = "arm,pl011", "arm,primecell";
186 reg = <0xb01000 0x1000>;
187 interrupts = <0 21 4>;
188 clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>;
189 clock-names = "uartclk", "apb_pclk";
190 status = "disabled";
191 };
192
193 uart2: serial@b02000 {
194 compatible = "arm,pl011", "arm,primecell";
195 reg = <0xb02000 0x1000>;
196 interrupts = <0 22 4>;
197 clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>;
198 clock-names = "uartclk", "apb_pclk";
199 status = "disabled";
200 };
201
202 uart3: serial@b03000 {
203 compatible = "arm,pl011", "arm,primecell";
204 reg = <0xb03000 0x1000>;
205 interrupts = <0 23 4>;
206 clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>;
207 clock-names = "uartclk", "apb_pclk";
208 status = "disabled";
209 };
210
211 uart4: serial@b04000 {
212 compatible = "arm,pl011", "arm,primecell";
213 reg = <0xb04000 0x1000>;
214 interrupts = <0 24 4>;
215 clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>;
216 clock-names = "uartclk", "apb_pclk";
217 status = "disabled";
218 };
219
220 gpio0: gpio@806000 {
221 compatible = "arm,pl061", "arm,primecell";
222 reg = <0x806000 0x1000>;
223 interrupts = <0 64 0x4>;
224 gpio-controller;
225 #gpio-cells = <2>;
226 gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
227 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 clocks = <&clock HI3620_GPIOCLK0>;
231 clock-names = "apb_pclk";
232 };
233
234 gpio1: gpio@807000 {
235 compatible = "arm,pl061", "arm,primecell";
236 reg = <0x807000 0x1000>;
237 interrupts = <0 65 0x4>;
238 gpio-controller;
239 #gpio-cells = <2>;
240 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
241 &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
242 &pmx0 6 5 1 &pmx0 7 6 1>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
245 clocks = <&clock HI3620_GPIOCLK1>;
246 clock-names = "apb_pclk";
247 };
248
249 gpio2: gpio@808000 {
250 compatible = "arm,pl061", "arm,primecell";
251 reg = <0x808000 0x1000>;
252 interrupts = <0 66 0x4>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
256 &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
257 &pmx0 6 3 1 &pmx0 7 3 1>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
260 clocks = <&clock HI3620_GPIOCLK2>;
261 clock-names = "apb_pclk";
262 };
263
264 gpio3: gpio@809000 {
265 compatible = "arm,pl061", "arm,primecell";
266 reg = <0x809000 0x1000>;
267 interrupts = <0 67 0x4>;
268 gpio-controller;
269 #gpio-cells = <2>;
270 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
271 &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
272 &pmx0 6 11 1 &pmx0 7 11 1>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 clocks = <&clock HI3620_GPIOCLK3>;
276 clock-names = "apb_pclk";
277 };
278
279 gpio4: gpio@80a000 {
280 compatible = "arm,pl061", "arm,primecell";
281 reg = <0x80a000 0x1000>;
282 interrupts = <0 68 0x4>;
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
286 &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
287 &pmx0 6 13 1 &pmx0 7 13 1>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 clocks = <&clock HI3620_GPIOCLK4>;
291 clock-names = "apb_pclk";
292 };
293
294 gpio5: gpio@80b000 {
295 compatible = "arm,pl061", "arm,primecell";
296 reg = <0x80b000 0x1000>;
297 interrupts = <0 69 0x4>;
298 gpio-controller;
299 #gpio-cells = <2>;
300 gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
301 &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
302 &pmx0 6 16 1 &pmx0 7 16 1>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 clocks = <&clock HI3620_GPIOCLK5>;
306 clock-names = "apb_pclk";
307 };
308
309 gpio6: gpio@80c000 {
310 compatible = "arm,pl061", "arm,primecell";
311 reg = <0x80c000 0x1000>;
312 interrupts = <0 70 0x4>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
316 &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
317 &pmx0 6 18 1 &pmx0 7 19 1>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 clocks = <&clock HI3620_GPIOCLK6>;
321 clock-names = "apb_pclk";
322 };
323
324 gpio7: gpio@80d000 {
325 compatible = "arm,pl061", "arm,primecell";
326 reg = <0x80d000 0x1000>;
327 interrupts = <0 71 0x4>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
331 &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
332 &pmx0 6 25 1 &pmx0 7 26 1>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
335 clocks = <&clock HI3620_GPIOCLK7>;
336 clock-names = "apb_pclk";
337 };
338
339 gpio8: gpio@80e000 {
340 compatible = "arm,pl061", "arm,primecell";
341 reg = <0x80e000 0x1000>;
342 interrupts = <0 72 0x4>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
346 &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
347 &pmx0 6 33 1 &pmx0 7 34 1>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 clocks = <&clock HI3620_GPIOCLK8>;
351 clock-names = "apb_pclk";
352 };
353
354 gpio9: gpio@80f000 {
355 compatible = "arm,pl061", "arm,primecell";
356 reg = <0x80f000 0x1000>;
357 interrupts = <0 73 0x4>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
361 &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
362 &pmx0 6 41 1>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
365 clocks = <&clock HI3620_GPIOCLK9>;
366 clock-names = "apb_pclk";
367 };
368
369 gpio10: gpio@810000 {
370 compatible = "arm,pl061", "arm,primecell";
371 reg = <0x810000 0x1000>;
372 interrupts = <0 74 0x4>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
376 &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 clocks = <&clock HI3620_GPIOCLK10>;
380 clock-names = "apb_pclk";
381 };
382
383 gpio11: gpio@811000 {
384 compatible = "arm,pl061", "arm,primecell";
385 reg = <0x811000 0x1000>;
386 interrupts = <0 75 0x4>;
387 gpio-controller;
388 #gpio-cells = <2>;
389 gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
390 &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
391 &pmx0 6 49 1 &pmx0 7 49 1>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 clocks = <&clock HI3620_GPIOCLK11>;
395 clock-names = "apb_pclk";
396 };
397
398 gpio12: gpio@812000 {
399 compatible = "arm,pl061", "arm,primecell";
400 reg = <0x812000 0x1000>;
401 interrupts = <0 76 0x4>;
402 gpio-controller;
403 #gpio-cells = <2>;
404 gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
405 &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
406 &pmx0 6 51 1 &pmx0 7 52 1>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 clocks = <&clock HI3620_GPIOCLK12>;
410 clock-names = "apb_pclk";
411 };
412
413 gpio13: gpio@813000 {
414 compatible = "arm,pl061", "arm,primecell";
415 reg = <0x813000 0x1000>;
416 interrupts = <0 77 0x4>;
417 gpio-controller;
418 #gpio-cells = <2>;
419 gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
420 &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
421 &pmx0 6 55 1 &pmx0 7 56 1>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 clocks = <&clock HI3620_GPIOCLK13>;
425 clock-names = "apb_pclk";
426 };
427
428 gpio14: gpio@814000 {
429 compatible = "arm,pl061", "arm,primecell";
430 reg = <0x814000 0x1000>;
431 interrupts = <0 78 0x4>;
432 gpio-controller;
433 #gpio-cells = <2>;
434 gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
435 &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
436 &pmx0 6 60 1 &pmx0 7 61 1>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 clocks = <&clock HI3620_GPIOCLK14>;
440 clock-names = "apb_pclk";
441 };
442
443 gpio15: gpio@815000 {
444 compatible = "arm,pl061", "arm,primecell";
445 reg = <0x815000 0x1000>;
446 interrupts = <0 79 0x4>;
447 gpio-controller;
448 #gpio-cells = <2>;
449 gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
450 &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
451 &pmx0 6 64 1 &pmx0 7 65 1>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 clocks = <&clock HI3620_GPIOCLK15>;
455 clock-names = "apb_pclk";
456 };
457
458 gpio16: gpio@816000 {
459 compatible = "arm,pl061", "arm,primecell";
460 reg = <0x816000 0x1000>;
461 interrupts = <0 80 0x4>;
462 gpio-controller;
463 #gpio-cells = <2>;
464 gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
465 &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
466 &pmx0 6 72 1 &pmx0 7 73 1>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
469 clocks = <&clock HI3620_GPIOCLK16>;
470 clock-names = "apb_pclk";
471 };
472
473 gpio17: gpio@817000 {
474 compatible = "arm,pl061", "arm,primecell";
475 reg = <0x817000 0x1000>;
476 interrupts = <0 81 0x4>;
477 gpio-controller;
478 #gpio-cells = <2>;
479 gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
480 &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
481 &pmx0 6 80 1 &pmx0 7 81 1>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 clocks = <&clock HI3620_GPIOCLK17>;
485 clock-names = "apb_pclk";
486 };
487
488 gpio18: gpio@818000 {
489 compatible = "arm,pl061", "arm,primecell";
490 reg = <0x818000 0x1000>;
491 interrupts = <0 82 0x4>;
492 gpio-controller;
493 #gpio-cells = <2>;
494 gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
495 &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
496 &pmx0 6 86 1 &pmx0 7 87 1>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 clocks = <&clock HI3620_GPIOCLK18>;
500 clock-names = "apb_pclk";
501 };
502
503 gpio19: gpio@819000 {
504 compatible = "arm,pl061", "arm,primecell";
505 reg = <0x819000 0x1000>;
506 interrupts = <0 83 0x4>;
507 gpio-controller;
508 #gpio-cells = <2>;
509 gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
510 &pmx0 3 88 1>;
511 interrupt-controller;
512 #interrupt-cells = <2>;
513 clocks = <&clock HI3620_GPIOCLK19>;
514 clock-names = "apb_pclk";
515 };
516
517 gpio20: gpio@81a000 {
518 compatible = "arm,pl061", "arm,primecell";
519 reg = <0x81a000 0x1000>;
520 interrupts = <0 84 0x4>;
521 gpio-controller;
522 #gpio-cells = <2>;
523 gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
524 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 clocks = <&clock HI3620_GPIOCLK20>;
528 clock-names = "apb_pclk";
529 };
530
531 gpio21: gpio@81b000 {
532 compatible = "arm,pl061", "arm,primecell";
533 reg = <0x81b000 0x1000>;
534 interrupts = <0 85 0x4>;
535 gpio-controller;
536 #gpio-cells = <2>;
537 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
540 clocks = <&clock HI3620_GPIOCLK21>;
541 clock-names = "apb_pclk";
542 };
543
544 pmx0: pinmux@803000 {
545 compatible = "pinctrl-single";
546 reg = <0x803000 0x188>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #pinctrl-cells = <1>;
550 #gpio-range-cells = <3>;
551
552 pinctrl-single,register-width = <32>;
553 pinctrl-single,function-mask = <7>;
554 /* pin base, nr pins & gpio function */
555 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
556 &range 12 1 0 &range 13 29 1
557 &range 43 1 0 &range 44 49 1
558 &range 94 1 1 &range 96 2 1>;
559
560 range: gpio-range {
561 #pinctrl-single,gpio-range-cells = <3>;
562 };
563 };
564
565 pmx1: pinmux@803800 {
566 compatible = "pinconf-single";
567 reg = <0x803800 0x2dc>;
568 #address-cells = <1>;
569 #size-cells = <0>;
570 #pinctrl-cells = <1>;
571
572 pinctrl-single,register-width = <32>;
573 };
574 };
575 };
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