1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3 #include "armada-385-clearfog-gtr.dtsi"
4
5 / {
6 model = "SolidRun Clearfog GTR L8";
7 compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
8 "marvell,armada380";
9
10 /* CON25 */
11 sfp1: sfp-1 {
12 compatible = "sff,sfp";
13 pinctrl-0 = <&cf_gtr_sfp1_pins>;
14 pinctrl-names = "default";
15 i2c-bus = <&i2c0>;
16 mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
17 tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
18 };
19 };
20
21 &mdio {
22 switch0: ethernet-switch@4 {
23 compatible = "marvell,mv88e6190";
24 reg = <4>;
25 pinctrl-names = "default";
26 pinctrl-0 = <&cf_gtr_switch_reset_pins>;
27 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
28
29 ethernet-ports {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 ethernet-port@1 {
34 reg = <1>;
35 label = "lan1";
36 phy-handle = <&switch0phy0>;
37 };
38
39 ethernet-port@2 {
40 reg = <2>;
41 label = "lan2";
42 phy-handle = <&switch0phy1>;
43 };
44
45 ethernet-port@3 {
46 reg = <3>;
47 label = "lan3";
48 phy-handle = <&switch0phy2>;
49 };
50
51 ethernet-port@4 {
52 reg = <4>;
53 label = "lan4";
54 phy-handle = <&switch0phy3>;
55 };
56
57 ethernet-port@5 {
58 reg = <5>;
59 label = "lan5";
60 phy-handle = <&switch0phy4>;
61 };
62
63 ethernet-port@6 {
64 reg = <6>;
65 label = "lan6";
66 phy-handle = <&switch0phy5>;
67 };
68
69 ethernet-port@7 {
70 reg = <7>;
71 label = "lan7";
72 phy-handle = <&switch0phy6>;
73 };
74
75 ethernet-port@8 {
76 reg = <8>;
77 label = "lan8";
78 phy-handle = <&switch0phy7>;
79 };
80
81 ethernet-port@9 {
82 reg = <9>;
83 label = "lan-sfp";
84 phy-mode = "sgmii";
85 sfp = <&sfp1>;
86 managed = "in-band-status";
87 };
88
89 ethernet-port@10 {
90 reg = <10>;
91 phy-mode = "2500base-x";
92 ethernet = <ð1>;
93
94 fixed-link {
95 speed = <2500>;
96 full-duplex;
97 };
98 };
99
100 };
101
102 mdio {
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 switch0phy0: ethernet-phy@1 {
107 reg = <0x1>;
108 };
109
110 switch0phy1: ethernet-phy@2 {
111 reg = <0x2>;
112 };
113
114 switch0phy2: ethernet-phy@3 {
115 reg = <0x3>;
116 };
117
118 switch0phy3: ethernet-phy@4 {
119 reg = <0x4>;
120 };
121
122 switch0phy4: ethernet-phy@5 {
123 reg = <0x5>;
124 };
125
126 switch0phy5: ethernet-phy@6 {
127 reg = <0x6>;
128 };
129
130 switch0phy6: ethernet-phy@7 {
131 reg = <0x7>;
132 };
133
134 switch0phy7: ethernet-phy@8 {
135 reg = <0x8>;
136 };
137 };
138
139 };
140 };
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