1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
4 *
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
6 */
7
8 /*
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
11 1. 6141 switch (2.5Gbps capable)
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
13 3. USB 3.0 Host
14 4. mini PCIe CON2 - PCIe2
15 5. SFP connector, or optionally SGMII Ethernet 1512 PHY
16
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
21
22 Pin mapping -
23 0,1 - console UART
24 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
25 front panel and PSE controller
26 4,5 - MDC/MDIO
27 6..17 - RGMII
28 18 - Topaz switch reset (active low)
29 19 - 1512 phy reset
30 20 - 1512 phy reset (eth2, optional)
31 21,28,37,38,39,40 - SD0
32 22 - USB 3.0 current limiter enable (active high)
33 24 - SFP TX fault (input active high)
34 25 - SFP present (input active low)
35 26,27 - I2C1 - connected to SFP
36 29 - Fan PWM
37 30 - CON4 mini PCIe wifi disable
38 31 - CON3 mini PCIe wifi disable
39 32 - Fuse programming power toggle (1.8v)
40 33 - CON4 mini PCIe reset
41 34 - CON2 mini PCIe wifi disable
42 35 - CON3 mini PCIe reset
43 36 - Rear button (GPIO active low)
44 41 - CON1 front panel connector
45 42 - Front LED1, or front panel CON1
46 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
47 44 - CON2 mini PCIe reset
48 45 - TPM PIRQ signal, or front panel CON1
49 46 - SFP TX disable
50 47 - Control isolation of boot sensitive SAR signals
51 48 - PSE reset
52 49 - PSE OSS signal
53 50 - PSE interrupt
54 52 - Front LED2, or front panel
55 53 - Front button
56 54 - SFP LOS (input active high)
57 55 - Fan sense
58 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
59 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
60 */
61
62 /dts-v1/;
63 #include <dt-bindings/input/input.h>
64 #include <dt-bindings/gpio/gpio.h>
65 #include <dt-bindings/leds/common.h>
66 #include "armada-385.dtsi"
67
68 / {
69 compatible = "marvell,armada385", "marvell,armada380";
70
71 aliases {
72 /* So that mvebu u-boot can update the MAC addresses */
73 ethernet1 = ð0;
74 ethernet2 = ð1;
75 ethernet3 = ð2;
76 i2c0 = &i2c0;
77 i2c1 = &i2c1;
78 };
79
80 chosen {
81 stdout-path = "serial0:115200n8";
82 };
83
84 memory {
85 device_type = "memory";
86 reg = <0x00000000 0x10000000>; /* 256 MB */
87 };
88
89 reg_3p3v: regulator-3p3v {
90 compatible = "regulator-fixed";
91 regulator-name = "3P3V";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 regulator-always-on;
95 };
96
97 reg_5p0v: regulator-5p0v {
98 compatible = "regulator-fixed";
99 regulator-name = "5P0V";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-always-on;
103 };
104
105 v_usb3_con: regulator-v-usb3-con {
106 compatible = "regulator-fixed";
107 gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
110 regulator-max-microvolt = <5000000>;
111 regulator-min-microvolt = <5000000>;
112 regulator-name = "v_usb3_con";
113 vin-supply = <®_5p0v>;
114 regulator-boot-on;
115 regulator-always-on;
116 };
117
118 soc {
119 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
120 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
121 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
122 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
123 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
124
125 internal-regs {
126
127 rtc@a3800 {
128 status = "okay";
129 };
130
131 i2c@11000 { /* ROM, temp sensor and front panel */
132 pinctrl-0 = <&i2c0_pins>;
133 pinctrl-names = "default";
134 status = "okay";
135 };
136
137 i2c@11100 { /* SFP (CON5/CON6) */
138 pinctrl-0 = <&cf_gtr_i2c1_pins>;
139 pinctrl-names = "default";
140 status = "okay";
141 };
142
143 pinctrl@18000 {
144 cf_gtr_fan_pwm: cf-gtr-fan-pwm {
145 marvell,pins = "mpp23";
146 marvell,function = "gpio";
147 };
148
149 cf_gtr_front_button_pins: cf-gtr-front-button-pins {
150 marvell,pins = "mpp53";
151 marvell,function = "gpio";
152 };
153
154 cf_gtr_i2c1_pins: i2c1-pins {
155 /* SFP */
156 marvell,pins = "mpp26", "mpp27";
157 marvell,function = "i2c1";
158 };
159
160 cf_gtr_isolation_pins: cf-gtr-isolation-pins {
161 marvell,pins = "mpp47";
162 marvell,function = "gpio";
163 };
164
165 cf_gtr_led_pins: led-pins {
166 marvell,pins = "mpp42", "mpp52";
167 marvell,function = "gpio";
168 };
169
170 cf_gtr_lte_disable_pins: lte-disable-pins {
171 marvell,pins = "mpp34";
172 marvell,function = "gpio";
173 };
174
175 cf_gtr_pci_pins: pci-pins {
176 // pci reset
177 marvell,pins = "mpp33", "mpp35", "mpp44";
178 marvell,function = "gpio";
179 };
180
181 cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
182 marvell,pins = "mpp48";
183 marvell,function = "gpio";
184 };
185
186 cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
187 marvell,pins = "mpp36";
188 marvell,function = "gpio";
189 };
190
191 cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
192 marvell,pins = "mpp21", "mpp28",
193 "mpp37", "mpp38",
194 "mpp39", "mpp40";
195 marvell,function = "sd0";
196 };
197
198 cf_gtr_sfp0_pins: sfp0-pins {
199 /* sfp modabs, txdisable */
200 marvell,pins = "mpp25", "mpp46";
201 marvell,function = "gpio";
202 };
203
204 cf_gtr_sfp1_pins: sfp1-pins {
205 /* sfp modabs, txdisable */
206 marvell,pins = "mpp24", "mpp54";
207 marvell,function = "gpio";
208 };
209
210 cf_gtr_spi1_cs_pins: spi1-cs-pins {
211 marvell,pins = "mpp59";
212 marvell,function = "spi1";
213 };
214
215 cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
216 marvell,pins = "mpp18";
217 marvell,function = "gpio";
218 };
219
220 cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
221 marvell,pins = "mpp22";
222 marvell,function = "gpio";
223 };
224
225 cf_gtr_wifi_disable_pins: wifi-disable-pins {
226 marvell,pins = "mpp30", "mpp31";
227 marvell,function = "gpio";
228 };
229 };
230
231 sdhci@d8000 {
232 bus-width = <4>;
233 no-1-8-v;
234 non-removable;
235 pinctrl-0 = <&cf_gtr_sdhci_pins>;
236 pinctrl-names = "default";
237 status = "okay";
238 vmmc = <®_3p3v>;
239 wp-inverted;
240 };
241
242 usb@58000 {
243 status = "okay";
244 };
245
246 usb3@f0000 {
247 status = "okay";
248 };
249
250 usb3@f8000 {
251 vbus-supply = <&v_usb3_con>;
252 status = "okay";
253 };
254 };
255
256 pcie {
257 pinctrl-0 = <&cf_gtr_pci_pins>;
258 pinctrl-names = "default";
259 status = "okay";
260 /*
261 * The PCIe units are accessible through
262 * the mini-PCIe connectors on the board.
263 */
264 /* CON3 - serdes 0 */
265 pcie@1,0 {
266 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
267 status = "okay";
268 };
269
270 /* CON4 - serdes 2 */
271 pcie@2,0 {
272 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
273 status = "okay";
274 };
275
276 /* CON2 - serdes 4 */
277 pcie@3,0 {
278 reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
279 status = "okay";
280 };
281 };
282 };
283
284 /* CON5 */
285 sfp0: sfp-0 {
286 compatible = "sff,sfp";
287 pinctrl-0 = <&cf_gtr_sfp0_pins>;
288 pinctrl-names = "default";
289 i2c-bus = <&i2c1>;
290 mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
291 tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
292 };
293
294 gpio-keys {
295 compatible = "gpio-keys";
296 pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
297 pinctrl-names = "default";
298
299 button-0 {
300 label = "Rear Button";
301 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
302 linux,can-disable;
303 linux,code = <BTN_0>;
304 };
305
306 button-1 {
307 label = "Front Button";
308 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
309 linux,can-disable;
310 linux,code = <BTN_1>;
311 };
312 };
313
314 gpio-leds {
315 compatible = "gpio-leds";
316 pinctrl-0 = <&cf_gtr_led_pins>;
317 pinctrl-names = "default";
318
319 led1 {
320 function = LED_FUNCTION_CPU;
321 color = <LED_COLOR_ID_GREEN>;
322 gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
323 };
324
325 led2 {
326 function = LED_FUNCTION_HEARTBEAT;
327 color = <LED_COLOR_ID_GREEN>;
328 gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
329 };
330 };
331 };
332
333 &bm {
334 status = "okay";
335 };
336
337 &bm_bppi {
338 status = "okay";
339 };
340
341 ð0 {
342 /* ethernet@70000 */
343 pinctrl-0 = <&ge0_rgmii_pins>;
344 pinctrl-names = "default";
345 phy = <&phy_dedicated>;
346 phy-mode = "rgmii-id";
347 buffer-manager = <&bm>;
348 bm,pool-long = <0>;
349 bm,pool-short = <1>;
350 status = "okay";
351 };
352
353 ð1 {
354 /* ethernet@30000 */
355 bm,pool-long = <2>;
356 bm,pool-short = <1>;
357 buffer-manager = <&bm>;
358 phys = <&comphy1 1>;
359 phy-mode = "2500base-x";
360 status = "okay";
361
362 fixed-link {
363 speed = <2500>;
364 full-duplex;
365 };
366 };
367
368 ð2 {
369 /* ethernet@34000 */
370 bm,pool-long = <3>;
371 bm,pool-short = <1>;
372 buffer-manager = <&bm>;
373 managed = "in-band-status";
374 phys = <&comphy5 1>;
375 phy-mode = "sgmii";
376 sfp = <&sfp0>;
377 status = "okay";
378 };
379
380 &mdio {
381 pinctrl-names = "default";
382 pinctrl-0 = <&mdio_pins>;
383 status = "okay";
384
385 phy_dedicated: ethernet-phy@0 {
386 /*
387 * Annoyingly, the marvell phy driver configures the LED
388 * register, rather than preserving reset-loaded setting.
389 * We undo that rubbish here.
390 */
391 marvell,reg-init = <3 16 0 0x1017>;
392 reg = <0>;
393 };
394 };
395
396 &uart0 {
397 pinctrl-0 = <&uart0_pins>;
398 pinctrl-names = "default";
399 status = "okay";
400 };
401
402 &spi1 {
403 /*
404 * CS0: W25Q32 flash
405 */
406 pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
407 pinctrl-names = "default";
408 status = "okay";
409
410 flash@0 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "w25q32", "jedec,spi-nor";
414 reg = <0>; /* Chip select 0 */
415 spi-max-frequency = <3000000>;
416 status = "okay";
417 };
418 };
419
420 &i2c0 {
421 pinctrl-0 = <&i2c0_pins>;
422 pinctrl-names = "default";
423 status = "okay";
424
425 /* U26 temperature sensor placed near SoC */
426 temp1: temperature-sensor@4c {
427 compatible = "ti,tmp75c";
428 reg = <0x4c>;
429 };
430
431 /* U27 temperature sensor placed near RTC battery */
432 temp2: temperature-sensor@4d {
433 compatible = "ti,tmp75c";
434 reg = <0x4d>;
435 };
436
437 /* 2Kb eeprom */
438 eeprom@53 {
439 compatible = "atmel,24c02";
440 reg = <0x53>;
441 };
442 };
443
444 &ahci0 {
445 status = "okay";
446 };
447
448 &ahci1 {
449 status = "okay";
450 };
451
452 &gpio0 {
453 pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
454 pinctrl-names = "default";
455
456 wifi-disable {
457 gpio-hog;
458 gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
459 output-low;
460 line-name = "wifi-disable";
461 };
462 };
463
464 &gpio1 {
465 pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;
466 pinctrl-names = "default";
467
468 lte-disable {
469 gpio-hog;
470 gpios = <2 GPIO_ACTIVE_LOW>;
471 output-low;
472 line-name = "lte-disable";
473 };
474
475 /*
476 * This signal, when asserted, isolates Armada 38x sample at reset pins
477 * from control of external devices. Should be de-asserted after reset.
478 */
479 sar-isolation {
480 gpio-hog;
481 gpios = <15 GPIO_ACTIVE_LOW>;
482 output-low;
483 line-name = "sar-isolation";
484 };
485
486 poe-reset {
487 gpio-hog;
488 gpios = <16 GPIO_ACTIVE_LOW>;
489 output-low;
490 line-name = "poe-reset";
491 };
492 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.