1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell 98dx3236 family SoC
4 *
5 * Copyright (C) 2016 Allied Telesis Labs
6 *
7 * Contains definitions specific to the 98dx3236 SoC that are not
8 * common to all Armada XP SoCs.
9 */
10
11 #include "armada-370-xp.dtsi"
12
13 / {
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 model = "Marvell 98DX3236 SoC";
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
19
20 aliases {
21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7";
34 reg = <0>;
35 clocks = <&cpuclk 0>;
36 clock-latency = <1000000>;
37 };
38 };
39
40 soc {
41 compatible = "marvell,armadaxp-mbus", "simple-bus";
42
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
48
49 bootrom {
50 compatible = "marvell,bootrom";
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
52 };
53
54 /*
55 * 98DX3236 has 1 x1 PCIe unit Gen2.0
56 */
57 pciec: pcie@82000000 {
58 compatible = "marvell,armada-xp-pcie";
59 status = "disabled";
60 device_type = "pci";
61
62 #address-cells = <3>;
63 #size-cells = <2>;
64
65 msi-parent = <&mpic>;
66 bus-range = <0x00 0xff>;
67
68 ranges =
69 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
70 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
71 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
72
73 pcie1: pcie@1,0 {
74 device_type = "pci";
75 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
76 reg = <0x0800 0 0 0 0>;
77 #address-cells = <3>;
78 #size-cells = <2>;
79 interrupt-names = "intx";
80 interrupts-extended = <&mpic 58>;
81 #interrupt-cells = <1>;
82 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
83 0x81000000 0 0 0x81000000 0x1 0 1 0>;
84 bus-range = <0x00 0xff>;
85 interrupt-map-mask = <0 0 0 7>;
86 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
87 <0 0 0 2 &pcie1_intc 1>,
88 <0 0 0 3 &pcie1_intc 2>,
89 <0 0 0 4 &pcie1_intc 3>;
90 marvell,pcie-port = <0>;
91 marvell,pcie-lane = <0>;
92 clocks = <&gateclk 5>;
93 status = "disabled";
94
95 pcie1_intc: interrupt-controller {
96 interrupt-controller;
97 #interrupt-cells = <1>;
98 };
99 };
100 };
101
102 internal-regs {
103 sdramc: sdramc@1400 {
104 compatible = "marvell,armada-xp-sdram-controller";
105 reg = <0x1400 0x500>;
106 };
107
108 L2: l2-cache@8000 {
109 compatible = "marvell,aurora-system-cache";
110 reg = <0x08000 0x1000>;
111 cache-id-part = <0x100>;
112 cache-level = <2>;
113 cache-unified;
114 wt-override;
115 };
116
117 gpio0: gpio@18100 {
118 compatible = "marvell,orion-gpio";
119 reg = <0x18100 0x40>;
120 ngpios = <32>;
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 interrupts = <82>, <83>, <84>, <85>;
126 };
127
128 /* does not exist */
129 gpio1: gpio@18140 {
130 compatible = "marvell,orion-gpio";
131 reg = <0x18140 0x40>;
132 status = "disabled";
133 };
134
135 gpio2: gpio@18180 { /* rework some properties */
136 compatible = "marvell,orion-gpio";
137 reg = <0x18180 0x40>;
138 ngpios = <1>; /* only gpio #32 */
139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <2>;
143 interrupts = <87>;
144 };
145
146 systemc: system-controller@18200 {
147 compatible = "marvell,armada-370-xp-system-controller";
148 reg = <0x18200 0x500>;
149 };
150
151 gateclk: clock-gating-control@18220 {
152 compatible = "marvell,mv98dx3236-gating-clock";
153 reg = <0x18220 0x4>;
154 clocks = <&coreclk 0>;
155 #clock-cells = <1>;
156 };
157
158 cpuclk: clock-complex@18700 {
159 #clock-cells = <1>;
160 compatible = "marvell,mv98dx3236-cpu-clock";
161 reg = <0x18700 0x24>, <0x1c054 0x10>;
162 clocks = <&coreclk 1>;
163 };
164
165 corediv-clock@18740 {
166 status = "disabled";
167 };
168
169 cpu-config@21000 {
170 compatible = "marvell,armada-xp-cpu-config";
171 reg = <0x21000 0x8>;
172 };
173
174 ethernet@70000 {
175 compatible = "marvell,armada-xp-neta";
176 };
177
178 ethernet@74000 {
179 compatible = "marvell,armada-xp-neta";
180 };
181
182 xor1: xor@f0800 {
183 compatible = "marvell,orion-xor";
184 reg = <0xf0800 0x100
185 0xf0a00 0x100>;
186 clocks = <&gateclk 22>;
187 status = "okay";
188
189 xor10 {
190 interrupts = <51>;
191 dmacap,memcpy;
192 dmacap,xor;
193 };
194 xor11 {
195 interrupts = <52>;
196 dmacap,memcpy;
197 dmacap,xor;
198 dmacap,memset;
199 };
200 };
201
202 nand_controller: nand-controller@d0000 {
203 clocks = <&dfx_coredivclk 0>;
204 };
205
206 xor0: xor@f0900 {
207 compatible = "marvell,orion-xor";
208 reg = <0xF0900 0x100
209 0xF0B00 0x100>;
210 clocks = <&gateclk 28>;
211 status = "okay";
212
213 xor00 {
214 interrupts = <94>;
215 dmacap,memcpy;
216 dmacap,xor;
217 };
218 xor01 {
219 interrupts = <95>;
220 dmacap,memcpy;
221 dmacap,xor;
222 dmacap,memset;
223 };
224 };
225 };
226
227 dfx: dfx-server@ac000000 {
228 compatible = "marvell,dfx-server", "simple-bus";
229 #address-cells = <1>;
230 #size-cells = <1>;
231 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
232 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
233
234 coreclk: mvebu-sar@f8204 {
235 compatible = "marvell,mv98dx3236-core-clock";
236 reg = <0xf8204 0x4>;
237 #clock-cells = <1>;
238 };
239
240 dfx_coredivclk: corediv-clock@f8268 {
241 compatible = "marvell,mv98dx3236-corediv-clock";
242 reg = <0xf8268 0xc>;
243 #clock-cells = <1>;
244 clocks = <&mainpll>;
245 clock-output-names = "nand";
246 };
247 };
248
249 switch: switch@a8000000 {
250 compatible = "simple-bus";
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
254
255 pp0: packet-processor@0 {
256 compatible = "marvell,prestera-98dx3236", "marvell,prestera";
257 reg = <0 0x4000000>;
258 interrupts = <33>, <34>, <35>;
259 dfx = <&dfx>;
260 };
261 };
262 };
263
264 clocks {
265 /* 25 MHz reference crystal */
266 refclk: oscillator {
267 compatible = "fixed-clock";
268 #clock-cells = <0>;
269 clock-frequency = <25000000>;
270 };
271 };
272 };
273
274 &i2c0 {
275 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
276 reg = <0x11000 0x100>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c0_pins>;
279 };
280
281 &mpic {
282 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
283 };
284
285 &rtc {
286 status = "disabled";
287 };
288
289 &timer {
290 compatible = "marvell,armada-xp-timer";
291 clocks = <&coreclk 2>, <&refclk>;
292 clock-names = "nbclk", "fixed";
293 };
294
295 &watchdog {
296 compatible = "marvell,armada-xp-wdt";
297 clocks = <&coreclk 2>, <&refclk>;
298 clock-names = "nbclk", "fixed";
299 interrupts = <93>, <38>;
300 };
301
302 &cpurst {
303 reg = <0x20800 0x20>;
304 };
305
306 &usb0 {
307 clocks = <&gateclk 18>;
308 };
309
310 &usb1 {
311 clocks = <&gateclk 19>;
312 };
313
314 &pinctrl {
315 compatible = "marvell,98dx3236-pinctrl";
316
317 nand_pins: nand-pins {
318 marvell,pins = "mpp20", "mpp21", "mpp22",
319 "mpp23", "mpp24", "mpp25",
320 "mpp26", "mpp27", "mpp28",
321 "mpp29", "mpp30";
322 marvell,function = "dev";
323 };
324
325 nand_rb: nand-rb {
326 marvell,pins = "mpp19";
327 marvell,function = "nand";
328 };
329
330 spi0_pins: spi0-pins {
331 marvell,pins = "mpp0", "mpp1",
332 "mpp2", "mpp3";
333 marvell,function = "spi0";
334 };
335
336 i2c0_pins: i2c-pins-0 {
337 marvell,pins = "mpp14", "mpp15";
338 marvell,function = "i2c0";
339 };
340 };
341
342 &spi0 {
343 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
344 pinctrl-0 = <&spi0_pins>;
345 pinctrl-names = "default";
346 };
347
348 &sdio {
349 status = "disabled";
350 };
351
352 &uart0 {
353 compatible = "marvell,armada-38x-uart";
354 };
355
356 &uart1 {
357 compatible = "marvell,armada-38x-uart";
358 };
359
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