1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Joe.C <yingjoe.chen@mediatek.com>
5 *
6 */
7
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
13
14 / {
15 #address-cells = <2>;
16 #size-cells = <2>;
17 compatible = "mediatek,mt8135";
18 interrupt-parent = <&sysirq>;
19
20 cpu-map {
21 cluster0 {
22 core0 {
23 cpu = <&cpu0>;
24 };
25 core1 {
26 cpu = <&cpu1>;
27 };
28 };
29
30 cluster1 {
31 core0 {
32 cpu = <&cpu2>;
33 };
34 core1 {
35 cpu = <&cpu3>;
36 };
37 };
38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 enable-method = "mediatek,mt81xx-tz-smp";
44
45 cpu0: cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a7";
48 reg = <0x000>;
49 };
50
51 cpu1: cpu@1 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0x001>;
55 };
56
57 cpu2: cpu@100 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a15";
60 reg = <0x100>;
61 };
62
63 cpu3: cpu@101 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a15";
66 reg = <0x101>;
67 };
68 };
69
70 reserved-memory {
71 #address-cells = <2>;
72 #size-cells = <2>;
73 ranges;
74
75 trustzone-bootinfo@80002000 {
76 compatible = "mediatek,trustzone-bootinfo";
77 reg = <0 0x80002000 0 0x1000>;
78 };
79 };
80
81 clocks {
82 #address-cells = <2>;
83 #size-cells = <2>;
84 compatible = "simple-bus";
85 ranges;
86
87 system_clk: dummy13m {
88 compatible = "fixed-clock";
89 clock-frequency = <13000000>;
90 #clock-cells = <0>;
91 };
92
93 rtc_clk: dummy32k {
94 compatible = "fixed-clock";
95 clock-frequency = <32000>;
96 #clock-cells = <0>;
97 };
98
99 clk26m: clk26m {
100 compatible = "fixed-clock";
101 #clock-cells = <0>;
102 clock-frequency = <26000000>;
103 };
104 };
105
106 timer {
107 compatible = "arm,armv7-timer";
108 interrupt-parent = <&gic>;
109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
110 IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
112 IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
114 IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
116 IRQ_TYPE_LEVEL_LOW)>;
117 clock-frequency = <13000000>;
118 arm,cpu-registers-not-fw-configured;
119 };
120
121 soc {
122 #address-cells = <2>;
123 #size-cells = <2>;
124 compatible = "simple-bus";
125 ranges;
126
127 topckgen: topckgen@10000000 {
128 compatible = "mediatek,mt8135-topckgen";
129 reg = <0 0x10000000 0 0x1000>;
130 #clock-cells = <1>;
131 };
132
133 infracfg: infracfg@10001000 {
134 #reset-cells = <1>;
135 #clock-cells = <1>;
136 compatible = "mediatek,mt8135-infracfg", "syscon";
137 reg = <0 0x10001000 0 0x1000>;
138 };
139
140 pericfg: pericfg@10003000 {
141 #reset-cells = <1>;
142 #clock-cells = <1>;
143 compatible = "mediatek,mt8135-pericfg", "syscon";
144 reg = <0 0x10003000 0 0x1000>;
145 };
146
147 /*
148 * Pinctrl access register at 0x10005000 and 0x1020c000 through
149 * regmap. Register 0x1000b000 is used by EINT.
150 */
151 pio: pinctrl@10005000 {
152 compatible = "mediatek,mt8135-pinctrl";
153 reg = <0 0x1000b000 0 0x1000>;
154 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
159 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
162 };
163
164 syscfg_pctl_a: syscfg_pctl_a@10005000 {
165 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
166 reg = <0 0x10005000 0 0x1000>;
167 };
168
169 timer: timer@10008000 {
170 compatible = "mediatek,mt8135-timer",
171 "mediatek,mt6577-timer";
172 reg = <0 0x10008000 0 0x80>;
173 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
174 clocks = <&system_clk>, <&rtc_clk>;
175 clock-names = "system-clk", "rtc-clk";
176 };
177
178 pwrap: pwrap@1000f000 {
179 compatible = "mediatek,mt8135-pwrap";
180 reg = <0 0x1000f000 0 0x1000>,
181 <0 0x11017000 0 0x1000>;
182 reg-names = "pwrap", "pwrap-bridge";
183 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
184 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
185 <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
186 reset-names = "pwrap", "pwrap-bridge";
187 clocks = <&clk26m>, <&clk26m>;
188 clock-names = "spi", "wrap";
189 };
190
191 sysirq: interrupt-controller@10200030 {
192 compatible = "mediatek,mt8135-sysirq",
193 "mediatek,mt6577-sysirq";
194 interrupt-controller;
195 #interrupt-cells = <3>;
196 interrupt-parent = <&gic>;
197 reg = <0 0x10200030 0 0x1c>;
198 };
199
200 apmixedsys: apmixedsys@10209000 {
201 compatible = "mediatek,mt8135-apmixedsys";
202 reg = <0 0x10209000 0 0x1000>;
203 #clock-cells = <1>;
204 };
205
206 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
207 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
208 reg = <0 0x1020c000 0 0x1000>;
209 };
210
211 gic: interrupt-controller@10211000 {
212 compatible = "arm,cortex-a15-gic";
213 interrupt-controller;
214 #interrupt-cells = <3>;
215 interrupt-parent = <&gic>;
216 reg = <0 0x10211000 0 0x1000>,
217 <0 0x10212000 0 0x2000>,
218 <0 0x10214000 0 0x2000>,
219 <0 0x10216000 0 0x2000>;
220 };
221
222 uart0: serial@11006000 {
223 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
224 reg = <0 0x11006000 0 0x400>;
225 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
226 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
227 clock-names = "baud", "bus";
228 status = "disabled";
229 };
230
231 uart1: serial@11007000 {
232 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
233 reg = <0 0x11007000 0 0x400>;
234 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
235 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
236 clock-names = "baud", "bus";
237 status = "disabled";
238 };
239
240 uart2: serial@11008000 {
241 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
242 reg = <0 0x11008000 0 0x400>;
243 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
244 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
245 clock-names = "baud", "bus";
246 status = "disabled";
247 };
248
249 uart3: serial@11009000 {
250 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
251 reg = <0 0x11009000 0 0x400>;
252 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
253 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
254 clock-names = "baud", "bus";
255 status = "disabled";
256 };
257
258 };
259 };
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