1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra20.dtsi"
3
4 / {
5 model = "Avionic Design Tamonten SOM";
6 compatible = "ad,tamonten", "nvidia,tegra20";
7
8 aliases {
9 rtc0 = "/i2c@7000d000/tps6586x@34";
10 rtc1 = "/rtc@7000e000";
11 serial0 = &uartd;
12 };
13
14 chosen {
15 stdout-path = "serial0:115200n8";
16 };
17
18 memory@0 {
19 reg = <0x00000000 0x20000000>;
20 };
21
22 host1x@50000000 {
23 hdmi@54280000 {
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
26
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
29 GPIO_ACTIVE_HIGH>;
30 };
31 };
32
33 pinmux@70000014 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
36
37 state_default: pinmux {
38 ata {
39 nvidia,pins = "ata";
40 nvidia,function = "ide";
41 };
42 atb {
43 nvidia,pins = "atb", "gma", "gme";
44 nvidia,function = "sdio4";
45 };
46 atc {
47 nvidia,pins = "atc";
48 nvidia,function = "nand";
49 };
50 atd {
51 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
52 "spia", "spib", "spic";
53 nvidia,function = "gmi";
54 };
55 cdev1 {
56 nvidia,pins = "cdev1";
57 nvidia,function = "plla_out";
58 };
59 cdev2 {
60 nvidia,pins = "cdev2";
61 nvidia,function = "pllp_out4";
62 };
63 crtp {
64 nvidia,pins = "crtp";
65 nvidia,function = "crt";
66 };
67 csus {
68 nvidia,pins = "csus";
69 nvidia,function = "vi_sensor_clk";
70 };
71 dap1 {
72 nvidia,pins = "dap1";
73 nvidia,function = "dap1";
74 };
75 dap2 {
76 nvidia,pins = "dap2";
77 nvidia,function = "dap2";
78 };
79 dap3 {
80 nvidia,pins = "dap3";
81 nvidia,function = "dap3";
82 };
83 dap4 {
84 nvidia,pins = "dap4";
85 nvidia,function = "dap4";
86 };
87 dta {
88 nvidia,pins = "dta", "dtd";
89 nvidia,function = "sdio2";
90 };
91 dtb {
92 nvidia,pins = "dtb", "dtc", "dte";
93 nvidia,function = "rsvd1";
94 };
95 dtf {
96 nvidia,pins = "dtf";
97 nvidia,function = "i2c3";
98 };
99 gmc {
100 nvidia,pins = "gmc";
101 nvidia,function = "uartd";
102 };
103 gpu7 {
104 nvidia,pins = "gpu7";
105 nvidia,function = "rtck";
106 };
107 gpv {
108 nvidia,pins = "gpv", "slxa", "slxk";
109 nvidia,function = "pcie";
110 };
111 hdint {
112 nvidia,pins = "hdint";
113 nvidia,function = "hdmi";
114 };
115 i2cp {
116 nvidia,pins = "i2cp";
117 nvidia,function = "i2cp";
118 };
119 irrx {
120 nvidia,pins = "irrx", "irtx";
121 nvidia,function = "uarta";
122 };
123 kbca {
124 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
125 "kbce", "kbcf";
126 nvidia,function = "kbc";
127 };
128 lcsn {
129 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
130 "ld3", "ld4", "ld5", "ld6", "ld7",
131 "ld8", "ld9", "ld10", "ld11", "ld12",
132 "ld13", "ld14", "ld15", "ld16", "ld17",
133 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
134 "lhs", "lm0", "lm1", "lpp", "lpw0",
135 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
136 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
137 "lvs";
138 nvidia,function = "displaya";
139 };
140 owc {
141 nvidia,pins = "owc", "spdi", "spdo", "uac";
142 nvidia,function = "rsvd2";
143 };
144 pmc {
145 nvidia,pins = "pmc";
146 nvidia,function = "pwr_on";
147 };
148 rm {
149 nvidia,pins = "rm";
150 nvidia,function = "i2c1";
151 };
152 sdb {
153 nvidia,pins = "sdb", "sdc", "sdd";
154 nvidia,function = "pwm";
155 };
156 sdio1 {
157 nvidia,pins = "sdio1";
158 nvidia,function = "sdio1";
159 };
160 slxc {
161 nvidia,pins = "slxc", "slxd";
162 nvidia,function = "spdif";
163 };
164 spid {
165 nvidia,pins = "spid", "spie", "spif";
166 nvidia,function = "spi1";
167 };
168 spig {
169 nvidia,pins = "spig", "spih";
170 nvidia,function = "spi2_alt";
171 };
172 uaa {
173 nvidia,pins = "uaa", "uab", "uda";
174 nvidia,function = "ulpi";
175 };
176 uad {
177 nvidia,pins = "uad";
178 nvidia,function = "irda";
179 };
180 uca {
181 nvidia,pins = "uca", "ucb";
182 nvidia,function = "uartc";
183 };
184 conf_ata {
185 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
186 "cdev1", "cdev2", "dap1", "dtb", "dtf",
187 "gma", "gmb", "gmc", "gmd", "gme", "gpu7",
188 "gpv", "i2cp", "irrx", "irtx", "pta",
189 "rm", "slxa", "slxk", "spia", "spib",
190 "uac";
191 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
192 nvidia,tristate = <TEGRA_PIN_DISABLE>;
193 };
194 conf_ck32 {
195 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
196 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 };
199 conf_csus {
200 nvidia,pins = "csus", "spid", "spif";
201 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
202 nvidia,tristate = <TEGRA_PIN_ENABLE>;
203 };
204 conf_crtp {
205 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
206 "dtc", "dte", "gpu", "sdio1",
207 "slxc", "slxd", "spdi", "spdo", "spig",
208 "uda";
209 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210 nvidia,tristate = <TEGRA_PIN_ENABLE>;
211 };
212 conf_ddc {
213 nvidia,pins = "ddc", "dta", "dtd", "kbca",
214 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
215 "sdc", "uad", "uca";
216 nvidia,pull = <TEGRA_PIN_PULL_UP>;
217 nvidia,tristate = <TEGRA_PIN_DISABLE>;
218 };
219 conf_hdint {
220 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
221 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
222 "lvp0", "owc", "sdb";
223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
224 };
225 conf_sdd {
226 nvidia,pins = "sdd", "spic", "spie", "spih",
227 "uaa", "uab", "ucb";
228 nvidia,pull = <TEGRA_PIN_PULL_UP>;
229 nvidia,tristate = <TEGRA_PIN_ENABLE>;
230 };
231 conf_lc {
232 nvidia,pins = "lc", "ls";
233 nvidia,pull = <TEGRA_PIN_PULL_UP>;
234 };
235 conf_ld0 {
236 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
237 "ld5", "ld6", "ld7", "ld8", "ld9",
238 "ld10", "ld11", "ld12", "ld13", "ld14",
239 "ld15", "ld16", "ld17", "ldi", "lhp0",
240 "lhp1", "lhp2", "lhs", "lm0", "lpp",
241 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
242 "lvs", "pmc";
243 nvidia,tristate = <TEGRA_PIN_DISABLE>;
244 };
245 conf_ld17_0 {
246 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
247 "ld23_22";
248 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
249 };
250 };
251
252 state_i2cmux_ddc: pinmux-i2cmux-ddc {
253 ddc {
254 nvidia,pins = "ddc";
255 nvidia,function = "i2c2";
256 };
257 pta {
258 nvidia,pins = "pta";
259 nvidia,function = "rsvd4";
260 };
261 };
262
263 state_i2cmux_idle: pinmux-i2cmux-idle {
264 ddc {
265 nvidia,pins = "ddc";
266 nvidia,function = "rsvd4";
267 };
268 pta {
269 nvidia,pins = "pta";
270 nvidia,function = "rsvd4";
271 };
272 };
273
274 state_i2cmux_pta: pinmux-i2cmux-pta {
275 ddc {
276 nvidia,pins = "ddc";
277 nvidia,function = "rsvd4";
278 };
279 pta {
280 nvidia,pins = "pta";
281 nvidia,function = "i2c2";
282 };
283 };
284 };
285
286 i2s@70002800 {
287 status = "okay";
288 };
289
290 serial@70006300 {
291 /delete-property/ dmas;
292 /delete-property/ dma-names;
293 status = "okay";
294 };
295
296 i2c@7000c000 {
297 clock-frequency = <400000>;
298 status = "okay";
299 };
300
301 i2c@7000c400 {
302 clock-frequency = <100000>;
303 status = "okay";
304 };
305
306 i2c@7000d000 {
307 clock-frequency = <400000>;
308 status = "okay";
309
310 pmic: tps6586x@34 {
311 compatible = "ti,tps6586x";
312 reg = <0x34>;
313 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
314
315 ti,system-power-controller;
316
317 #gpio-cells = <2>;
318 gpio-controller;
319
320 /* vdd_5v0_reg must be provided by the base board */
321 sys-supply = <&vdd_5v0_reg>;
322 vin-sm0-supply = <&sys_reg>;
323 vin-sm1-supply = <&sys_reg>;
324 vin-sm2-supply = <&sys_reg>;
325 vinldo01-supply = <&sm2_reg>;
326 vinldo23-supply = <&sm2_reg>;
327 vinldo4-supply = <&sm2_reg>;
328 vinldo678-supply = <&sm2_reg>;
329 vinldo9-supply = <&sm2_reg>;
330
331 regulators {
332 sys_reg: sys {
333 regulator-name = "vdd_sys";
334 regulator-always-on;
335 };
336
337 vdd_core: sm0 {
338 regulator-name = "vdd_sys_sm0,vdd_core";
339 regulator-min-microvolt = <1200000>;
340 regulator-max-microvolt = <1200000>;
341 regulator-always-on;
342 };
343
344 sm1 {
345 regulator-name = "vdd_sys_sm1,vdd_cpu";
346 regulator-min-microvolt = <1000000>;
347 regulator-max-microvolt = <1000000>;
348 regulator-always-on;
349 };
350
351 sm2_reg: sm2 {
352 regulator-name = "vdd_sys_sm2,vin_ldo*";
353 regulator-min-microvolt = <3700000>;
354 regulator-max-microvolt = <3700000>;
355 regulator-always-on;
356 };
357
358 pci_clk_reg: ldo0 {
359 regulator-name = "vdd_ldo0,vddio_pex_clk";
360 regulator-min-microvolt = <3300000>;
361 regulator-max-microvolt = <3300000>;
362 };
363
364 ldo1 {
365 regulator-name = "vdd_ldo1,avdd_pll*";
366 regulator-min-microvolt = <1100000>;
367 regulator-max-microvolt = <1100000>;
368 regulator-always-on;
369 };
370
371 ldo2 {
372 regulator-name = "vdd_ldo2,vdd_rtc";
373 regulator-min-microvolt = <1200000>;
374 regulator-max-microvolt = <1200000>;
375 };
376
377 ldo3 {
378 regulator-name = "vdd_ldo3,avdd_usb*";
379 regulator-min-microvolt = <3300000>;
380 regulator-max-microvolt = <3300000>;
381 regulator-always-on;
382 };
383
384 ldo4 {
385 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
386 regulator-min-microvolt = <1800000>;
387 regulator-max-microvolt = <1800000>;
388 regulator-always-on;
389 };
390
391 ldo5 {
392 regulator-name = "vdd_ldo5,vcore_mmc";
393 regulator-min-microvolt = <2850000>;
394 regulator-max-microvolt = <2850000>;
395 };
396
397 ldo6 {
398 regulator-name = "vdd_ldo6,avdd_vdac";
399 /*
400 * According to the Tegra 2 Automotive
401 * DataSheet, a typical value for this
402 * would be 2.8V, but the PMIC only
403 * supports 2.85V.
404 */
405 regulator-min-microvolt = <2850000>;
406 regulator-max-microvolt = <2850000>;
407 };
408
409 hdmi_vdd_reg: ldo7 {
410 regulator-name = "vdd_ldo7,avdd_hdmi";
411 regulator-min-microvolt = <3300000>;
412 regulator-max-microvolt = <3300000>;
413 };
414
415 hdmi_pll_reg: ldo8 {
416 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
417 regulator-min-microvolt = <1800000>;
418 regulator-max-microvolt = <1800000>;
419 };
420
421 ldo9 {
422 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
423 /*
424 * According to the Tegra 2 Automotive
425 * DataSheet, a typical value for this
426 * would be 2.8V, but the PMIC only
427 * supports 2.85V.
428 */
429 regulator-min-microvolt = <2850000>;
430 regulator-max-microvolt = <2850000>;
431 regulator-always-on;
432 };
433
434 ldo_rtc {
435 regulator-name = "vdd_rtc_out";
436 regulator-min-microvolt = <3300000>;
437 regulator-max-microvolt = <3300000>;
438 regulator-always-on;
439 };
440 };
441 };
442
443 temperature-sensor@4c {
444 compatible = "onnn,nct1008";
445 reg = <0x4c>;
446 };
447 };
448
449 pmc@7000e400 {
450 nvidia,invert-interrupt;
451 nvidia,suspend-mode = <1>;
452 nvidia,cpu-pwr-good-time = <5000>;
453 nvidia,cpu-pwr-off-time = <5000>;
454 nvidia,core-pwr-good-time = <3845 3845>;
455 nvidia,core-pwr-off-time = <3875>;
456 nvidia,sys-clock-req-active-high;
457 core-supply = <&vdd_core>;
458 };
459
460 pcie@80003000 {
461 avdd-pex-supply = <&pci_vdd_reg>;
462 vdd-pex-supply = <&pci_vdd_reg>;
463 avdd-pex-pll-supply = <&pci_vdd_reg>;
464 avdd-plle-supply = <&pci_vdd_reg>;
465 vddio-pex-clk-supply = <&pci_clk_reg>;
466 };
467
468 usb@c5008000 {
469 status = "okay";
470 };
471
472 usb-phy@c5008000 {
473 status = "okay";
474 };
475
476 mmc@c8000600 {
477 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
478 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
479 bus-width = <4>;
480 status = "okay";
481 };
482
483 clk32k_in: clock-32k {
484 compatible = "fixed-clock";
485 clock-frequency = <32768>;
486 #clock-cells = <0>;
487 };
488
489 i2cmux {
490 compatible = "i2c-mux-pinctrl";
491 #address-cells = <1>;
492 #size-cells = <0>;
493
494 i2c-parent = <&{/i2c@7000c400}>;
495
496 pinctrl-names = "ddc", "pta", "idle";
497 pinctrl-0 = <&state_i2cmux_ddc>;
498 pinctrl-1 = <&state_i2cmux_pta>;
499 pinctrl-2 = <&state_i2cmux_idle>;
500
501 hdmi_ddc: i2c@0 {
502 reg = <0>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 };
506
507 i2c@1 {
508 reg = <1>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 };
512 };
513
514 pci_vdd_reg: regulator-1v05 {
515 compatible = "regulator-fixed";
516 regulator-name = "vdd_1v05";
517 regulator-min-microvolt = <1050000>;
518 regulator-max-microvolt = <1050000>;
519 gpio = <&pmic 2 0>;
520 enable-active-high;
521 };
522 };
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