1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
4 */
5
6 /dts-v1/;
7 #include "imx51.dtsi"
8
9 / {
10 model = "Digi ConnectCore CC(W)-MX51";
11 compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
12
13 memory@90000000 {
14 device_type = "memory";
15 reg = <0x90000000 0x08000000>;
16 };
17 };
18
19 &ecspi1 {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_ecspi1>;
22 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
23 status = "okay";
24
25 pmic: mc13892@0 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_mc13892>;
28 compatible = "fsl,mc13892";
29 spi-max-frequency = <16000000>;
30 spi-cs-high;
31 reg = <0>;
32 interrupt-parent = <&gpio1>;
33 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
34
35 regulators {
36 sw1_reg: sw1 {
37 regulator-min-microvolt = <1050000>;
38 regulator-max-microvolt = <1100000>;
39 regulator-boot-on;
40 regulator-always-on;
41 };
42
43 sw2_reg: sw2 {
44 regulator-min-microvolt = <1175000>;
45 regulator-max-microvolt = <1275000>;
46 regulator-boot-on;
47 regulator-always-on;
48 };
49
50 sw3_reg: sw3 {
51 regulator-min-microvolt = <1150000>;
52 regulator-max-microvolt = <1350000>;
53 regulator-boot-on;
54 regulator-always-on;
55 };
56
57 swbst_reg: swbst { };
58
59 viohi_reg: viohi {
60 regulator-always-on;
61 };
62
63 vpll_reg: vpll {
64 regulator-min-microvolt = <1800000>;
65 regulator-max-microvolt = <1800000>;
66 regulator-always-on;
67 };
68
69 vdig_reg: vdig {
70 regulator-min-microvolt = <1250000>;
71 regulator-max-microvolt = <1250000>;
72 regulator-always-on;
73 };
74
75 vsd_reg: vsd {
76 regulator-min-microvolt = <3150000>;
77 regulator-max-microvolt = <3150000>;
78 regulator-always-on;
79 };
80
81 vusb2_reg: vusb2 {
82 regulator-min-microvolt = <2600000>;
83 regulator-max-microvolt = <2600000>;
84 regulator-always-on;
85 };
86
87 vvideo_reg: vvideo {
88 regulator-min-microvolt = <2775000>;
89 regulator-max-microvolt = <2775000>;
90 regulator-always-on;
91 };
92
93 vaudio_reg: vaudio {
94 regulator-min-microvolt = <3000000>;
95 regulator-max-microvolt = <3000000>;
96 regulator-always-on;
97 };
98
99 vcam_reg: vcam {
100 regulator-min-microvolt = <2750000>;
101 regulator-max-microvolt = <2750000>;
102 regulator-always-on;
103 };
104
105 vgen3_reg: vgen3 {
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 regulator-always-on;
109 };
110
111 vusb_reg: vusb {
112 regulator-always-on;
113 };
114
115 gpo2_reg: gpo2 { };
116
117 gpo3_reg: gpo3 { };
118
119 gpo4_reg: gpo4 { };
120
121 pwgt2spi_reg: pwgt2spi {
122 regulator-always-on;
123 };
124 };
125 };
126 };
127
128 &esdhc1 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_esdhc1>;
131 max-frequency = <50000000>;
132 bus-width = <1>;
133 };
134
135 &esdhc2 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_esdhc2>;
138 cap-sdio-irq;
139 wakeup-source;
140 keep-power-in-suspend;
141 max-frequency = <50000000>;
142 no-1-8-v;
143 non-removable;
144 vmmc-supply = <&gpo4_reg>;
145 status = "okay";
146 };
147
148 &fec {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_fec>;
151 phy-mode = "mii";
152 phy-supply = <&gpo3_reg>;
153 /* Pins shared with LCD2, keep status disabled */
154 };
155
156 &i2c2 {
157 pinctrl-names = "default", "gpio";
158 pinctrl-0 = <&pinctrl_i2c2>;
159 pinctrl-1 = <&pinctrl_i2c2_gpio>;
160 clock-frequency = <400000>;
161 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
162 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
163 status = "okay";
164
165 mma7455l@1d {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_mma7455l>;
168 compatible = "fsl,mma7455l";
169 reg = <0x1d>;
170 interrupt-parent = <&gpio1>;
171 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
172 };
173 };
174
175 &nfc {
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_nfc>;
178 nand-bus-width = <8>;
179 nand-ecc-mode = "hw";
180 nand-on-flash-bbt;
181 status = "okay";
182 };
183
184 &usbotg {
185 phy_type = "utmi_wide";
186 disable-over-current;
187 vbus-supply = <&swbst_reg>;
188 /* Device role is not known, keep status disabled */
189 };
190
191 &weim {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_weim>;
194 status = "okay";
195
196 lan9221: ethernet@5,0 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_lan9221>;
199 compatible = "smsc,lan9221", "smsc,lan9115";
200 reg = <5 0x00000000 0x1000>;
201 fsl,weim-cs-timing = <
202 0x00420081 0x00000000
203 0x32260000 0x00000000
204 0x72080f00 0x00000000
205 >;
206 clocks = <&clks IMX5_CLK_DUMMY>;
207 interrupt-parent = <&gpio1>;
208 interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
209 phy-mode = "mii";
210 reg-io-width = <2>;
211 smsc,irq-push-pull;
212 vdd33a-supply = <&gpo2_reg>;
213 vddvario-supply = <&gpo2_reg>;
214 };
215 };
216
217 &iomuxc {
218 imx51-digi-connectcore-som {
219 pinctrl_ecspi1: ecspi1grp {
220 fsl,pins = <
221 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
222 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
223 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
224 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
225 >;
226 };
227
228 pinctrl_esdhc1: esdhc1grp {
229 fsl,pins = <
230 MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5
231 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
232 MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5
233 >;
234 };
235
236 pinctrl_esdhc2: esdhc2grp {
237 fsl,pins = <
238 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
239 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
240 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
241 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
242 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
243 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
244 >;
245 };
246
247 pinctrl_fec: fecgrp {
248 fsl,pins = <
249 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
250 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
251 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
252 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
253 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
254 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
255 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
256 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
257 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
258 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
259 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
260 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
261 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
262 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
263 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
264 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
265 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
266 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
267 >;
268 };
269
270 pinctrl_i2c2: i2c2grp {
271 fsl,pins = <
272 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
273 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
274 >;
275 };
276
277 pinctrl_i2c2_gpio: i2c2gpiogrp {
278 fsl,pins = <
279 MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed
280 MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed
281 >;
282 };
283
284 pinctrl_nfc: nfcgrp {
285 fsl,pins = <
286 MX51_PAD_NANDF_D0__NANDF_D0 0x80000000
287 MX51_PAD_NANDF_D1__NANDF_D1 0x80000000
288 MX51_PAD_NANDF_D2__NANDF_D2 0x80000000
289 MX51_PAD_NANDF_D3__NANDF_D3 0x80000000
290 MX51_PAD_NANDF_D4__NANDF_D4 0x80000000
291 MX51_PAD_NANDF_D5__NANDF_D5 0x80000000
292 MX51_PAD_NANDF_D6__NANDF_D6 0x80000000
293 MX51_PAD_NANDF_D7__NANDF_D7 0x80000000
294 MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000
295 MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000
296 MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000
297 MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000
298 MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000
299 MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000
300 MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000
301 >;
302 };
303
304 pinctrl_lan9221: lan9221grp {
305 fsl,pins = <
306 MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */
307 >;
308 };
309
310 pinctrl_mc13892: mc13892grp {
311 fsl,pins = <
312 MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */
313 >;
314 };
315
316 pinctrl_mma7455l: mma7455lgrp {
317 fsl,pins = <
318 MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */
319 MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */
320 >;
321 };
322
323 pinctrl_weim: weimgrp {
324 fsl,pins = <
325 MX51_PAD_EIM_DA0__EIM_DA0 0x80000000
326 MX51_PAD_EIM_DA1__EIM_DA1 0x80000000
327 MX51_PAD_EIM_DA2__EIM_DA2 0x80000000
328 MX51_PAD_EIM_DA3__EIM_DA3 0x80000000
329 MX51_PAD_EIM_DA4__EIM_DA4 0x80000000
330 MX51_PAD_EIM_DA5__EIM_DA5 0x80000000
331 MX51_PAD_EIM_DA6__EIM_DA6 0x80000000
332 MX51_PAD_EIM_DA7__EIM_DA7 0x80000000
333 MX51_PAD_EIM_DA8__EIM_DA8 0x80000000
334 MX51_PAD_EIM_DA9__EIM_DA9 0x80000000
335 MX51_PAD_EIM_DA10__EIM_DA10 0x80000000
336 MX51_PAD_EIM_DA11__EIM_DA11 0x80000000
337 MX51_PAD_EIM_DA12__EIM_DA12 0x80000000
338 MX51_PAD_EIM_DA13__EIM_DA13 0x80000000
339 MX51_PAD_EIM_DA14__EIM_DA14 0x80000000
340 MX51_PAD_EIM_DA15__EIM_DA15 0x80000000
341 MX51_PAD_EIM_A16__EIM_A16 0x80000000
342 MX51_PAD_EIM_A17__EIM_A17 0x80000000
343 MX51_PAD_EIM_A18__EIM_A18 0x80000000
344 MX51_PAD_EIM_A19__EIM_A19 0x80000000
345 MX51_PAD_EIM_A20__EIM_A20 0x80000000
346 MX51_PAD_EIM_A21__EIM_A21 0x80000000
347 MX51_PAD_EIM_A22__EIM_A22 0x80000000
348 MX51_PAD_EIM_A23__EIM_A23 0x80000000
349 MX51_PAD_EIM_A24__EIM_A24 0x80000000
350 MX51_PAD_EIM_A25__EIM_A25 0x80000000
351 MX51_PAD_EIM_A26__EIM_A26 0x80000000
352 MX51_PAD_EIM_A27__EIM_A27 0x80000000
353 MX51_PAD_EIM_D16__EIM_D16 0x80000000
354 MX51_PAD_EIM_D17__EIM_D17 0x80000000
355 MX51_PAD_EIM_D18__EIM_D18 0x80000000
356 MX51_PAD_EIM_D19__EIM_D19 0x80000000
357 MX51_PAD_EIM_D20__EIM_D20 0x80000000
358 MX51_PAD_EIM_D21__EIM_D21 0x80000000
359 MX51_PAD_EIM_D22__EIM_D22 0x80000000
360 MX51_PAD_EIM_D23__EIM_D23 0x80000000
361 MX51_PAD_EIM_D24__EIM_D24 0x80000000
362 MX51_PAD_EIM_D25__EIM_D25 0x80000000
363 MX51_PAD_EIM_D26__EIM_D26 0x80000000
364 MX51_PAD_EIM_D27__EIM_D27 0x80000000
365 MX51_PAD_EIM_D28__EIM_D28 0x80000000
366 MX51_PAD_EIM_D29__EIM_D29 0x80000000
367 MX51_PAD_EIM_D30__EIM_D30 0x80000000
368 MX51_PAD_EIM_D31__EIM_D31 0x80000000
369 MX51_PAD_EIM_OE__EIM_OE 0x80000000
370 MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000
371 MX51_PAD_EIM_LBA__EIM_LBA 0x80000000
372 MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */
373 >;
374 };
375 };
376 };
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