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Linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6q-prtwd2.dts

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  * Copyright (c) 2018 Protonic Holland
  4  */
  5 
  6 /dts-v1/;
  7 #include "imx6q.dtsi"
  8 #include "imx6qdl-prti6q.dtsi"
  9 #include <dt-bindings/leds/common.h>
 10 
 11 / {
 12         model = "Protonic WD2 board";
 13         compatible = "prt,prtwd2", "fsl,imx6q";
 14 
 15         memory@10000000 {
 16                 device_type = "memory";
 17                 reg = <0x10000000 0x20000000>;
 18         };
 19 
 20         memory@80000000 {
 21                 device_type = "memory";
 22                 reg = <0x80000000 0x20000000>;
 23         };
 24 
 25         clk50m_phy: phy-clock {
 26                 compatible = "fixed-clock";
 27                 #clock-cells = <0>;
 28                 clock-frequency = <50000000>;
 29                 clock-output-names = "enet_ref_pad";
 30         };
 31 
 32         usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq {
 33                 compatible = "mmc-pwrseq-simple";
 34                 pinctrl-names = "default";
 35                 pinctrl-0 = <&pinctrl_wifi_npd>;
 36                 reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
 37         };
 38 
 39         /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */
 40         i2c {
 41                 compatible = "i2c-gpio";
 42                 pinctrl-names = "default";
 43                 pinctrl-0 = <&pinctrl_i2c4>;
 44                 sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
 45                 scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 46                 i2c-gpio,delay-us = <20>;       /* ~10 kHz */
 47                 i2c-gpio,scl-output-only;
 48                 #address-cells = <1>;
 49                 #size-cells = <0>;
 50         };
 51 };
 52 
 53 &can1 {
 54         pinctrl-names = "default";
 55         pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
 56         status = "okay";
 57 };
 58 
 59 &clks {
 60         clocks = <&clk50m_phy>;
 61         clock-names = "enet_ref_pad";
 62         assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
 63         assigned-clock-parents = <&clk50m_phy>;
 64 };
 65 
 66 &fec {
 67         pinctrl-names = "default";
 68         pinctrl-0 = <&pinctrl_enet>;
 69         phy-mode = "rmii";
 70         status = "okay";
 71 
 72         fixed-link {
 73                 speed = <100>;
 74                 pause;
 75                 full-duplex;
 76         };
 77 };
 78 
 79 &i2c3 {
 80         adc@49 {
 81                 compatible = "ti,ads1015";
 82                 reg = <0x49>;
 83                 #address-cells = <1>;
 84                 #size-cells = <0>;
 85 
 86                 /* V in */
 87                 channel@4 {
 88                         reg = <4>;
 89                         ti,gain = <1>;
 90                         ti,datarate = <3>;
 91                 };
 92 
 93                 /* I charge */
 94                 channel@5 {
 95                         reg = <5>;
 96                         ti,gain = <1>;
 97                         ti,datarate = <3>;
 98                 };
 99 
100                 /* V bus  */
101                 channel@6 {
102                         reg = <6>;
103                         ti,gain = <1>;
104                         ti,datarate = <3>;
105                 };
106 
107                 /* nc */
108                 channel@7 {
109                         reg = <7>;
110                         ti,gain = <1>;
111                         ti,datarate = <3>;
112                 };
113         };
114 };
115 
116 &usdhc2 {
117         pinctrl-names = "default";
118         pinctrl-0 = <&pinctrl_usdhc2>;
119         no-1-8-v;
120         non-removable;
121         mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
122         #address-cells = <1>;
123         #size-cells = <0>;
124         status = "okay";
125 
126         wifi@1 {
127                 compatible = "brcm,bcm4329-fmac";
128                 reg = <1>;
129         };
130 };
131 
132 &iomuxc {
133         pinctrl-names = "default";
134         pinctrl-0 = <&pinctrl_usb_eth_chg>;
135 
136         pinctrl_can1phy: can1phy {
137                 fsl,pins = <
138                         /* CAN1_SR */
139                         MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
140                 >;
141         };
142 
143         pinctrl_enet: enetgrp {
144                 fsl,pins = <
145                         /* MX6QDL_ENET_PINGRP4 */
146                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
147                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
148                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x130b0
149                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
150                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
151                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
152                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
153 
154                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b0b0
155                         /* Phy reset */
156                         MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22        0x1b0b0
157                         /* nINTRP */
158                         MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x1b0b0
159                 >;
160         };
161 
162         pinctrl_i2c4: i2c4grp {
163                 fsl,pins = <
164                         MX6QDL_PAD_ENET_MDIO__GPIO1_IO22        0x1f8b0
165                         MX6QDL_PAD_ENET_MDC__GPIO1_IO31         0x1f8b0
166                 >;
167         };
168 
169         pinctrl_usb_eth_chg: usbethchggrp {
170                 fsl,pins = <
171                         /* USB charging control */
172                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x130b0
173                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x130b0
174                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x130b0
175                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x130b0
176                         >;
177         };
178 
179         pinctrl_usdhc2: usdhc2grp {
180                 fsl,pins = <
181                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
182                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
183                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
184                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
185                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
186                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
187                 >;
188         };
189 
190         pinctrl_wifi_npd: wifinpd {
191                 fsl,pins = <
192                         /* WL_REG_ON */
193                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x13069
194                 >;
195         };
196 };

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