1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/sound/fsl-imx-audmux.h>
10
11 / {
12 /* these are used by bootloader for disabling nodes */
13 aliases {
14 led0 = &led0;
15 led1 = &led1;
16 led2 = &led2;
17 nand = &gpmi;
18 ssi0 = &ssi1;
19 usb0 = &usbh1;
20 usb1 = &usbotg;
21 };
22
23 chosen {
24 bootargs = "console=ttymxc1,115200";
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm4 0 5000000 0>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <7>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36
37 user-pb {
38 label = "user_pb";
39 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
40 linux,code = <BTN_0>;
41 };
42
43 user-pb1x {
44 label = "user_pb1x";
45 linux,code = <BTN_1>;
46 interrupt-parent = <&gsc>;
47 interrupts = <0>;
48 };
49
50 key-erased {
51 label = "key-erased";
52 linux,code = <BTN_2>;
53 interrupt-parent = <&gsc>;
54 interrupts = <1>;
55 };
56
57 eeprom-wp {
58 label = "eeprom_wp";
59 linux,code = <BTN_3>;
60 interrupt-parent = <&gsc>;
61 interrupts = <2>;
62 };
63
64 tamper {
65 label = "tamper";
66 linux,code = <BTN_4>;
67 interrupt-parent = <&gsc>;
68 interrupts = <5>;
69 };
70
71 switch-hold {
72 label = "switch_hold";
73 linux,code = <BTN_5>;
74 interrupt-parent = <&gsc>;
75 interrupts = <7>;
76 };
77 };
78
79 leds {
80 compatible = "gpio-leds";
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_gpio_leds>;
83
84 led0: led-user1 {
85 label = "user1";
86 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
87 default-state = "on";
88 linux,default-trigger = "heartbeat";
89 };
90
91 led1: led-user2 {
92 label = "user2";
93 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
94 default-state = "off";
95 };
96
97 led2: led-user3 {
98 label = "user3";
99 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
100 default-state = "off";
101 };
102 };
103
104 memory@10000000 {
105 device_type = "memory";
106 reg = <0x10000000 0x40000000>;
107 };
108
109 pps {
110 compatible = "pps-gpio";
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_pps>;
113 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
114 status = "okay";
115 };
116
117 reg_1p0v: regulator-1p0v {
118 compatible = "regulator-fixed";
119 regulator-name = "1P0V";
120 regulator-min-microvolt = <1000000>;
121 regulator-max-microvolt = <1000000>;
122 regulator-always-on;
123 };
124
125 reg_3p3v: regulator-3p3v {
126 compatible = "regulator-fixed";
127 regulator-name = "3P3V";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 regulator-always-on;
131 };
132
133 reg_can1_stby: regulator-can1-stby {
134 compatible = "regulator-fixed";
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_reg_can1>;
137 regulator-name = "can1_stby";
138 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
139 regulator-min-microvolt = <3300000>;
140 regulator-max-microvolt = <3300000>;
141 };
142
143 reg_usb_h1_vbus: regulator-usb-h1-vbus {
144 compatible = "regulator-fixed";
145 regulator-name = "usb_h1_vbus";
146 regulator-min-microvolt = <5000000>;
147 regulator-max-microvolt = <5000000>;
148 regulator-always-on;
149 };
150
151 reg_usb_otg_vbus: regulator-usb-otg-vbus {
152 compatible = "regulator-fixed";
153 regulator-name = "usb_otg_vbus";
154 regulator-min-microvolt = <5000000>;
155 regulator-max-microvolt = <5000000>;
156 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
157 enable-active-high;
158 };
159
160 sound-analog {
161 compatible = "fsl,imx6q-ventana-sgtl5000",
162 "fsl,imx-audio-sgtl5000";
163 model = "sgtl5000-audio";
164 ssi-controller = <&ssi1>;
165 audio-codec = <&sgtl5000>;
166 audio-routing =
167 "MIC_IN", "Mic Jack",
168 "Mic Jack", "Mic Bias",
169 "Headphone Jack", "HP_OUT";
170 mux-int-port = <1>;
171 mux-ext-port = <4>;
172 };
173 };
174
175 &audmux {
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
178 status = "okay";
179
180 mux-ssi2 {
181 fsl,audmux-port = <1>;
182 fsl,port-config = <
183 (IMX_AUDMUX_V2_PTCR_TFSDIR |
184 IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
185 IMX_AUDMUX_V2_PTCR_TCLKDIR |
186 IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
187 IMX_AUDMUX_V2_PTCR_SYN)
188 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
189 >;
190 };
191
192 mux-aud5 {
193 fsl,audmux-port = <4>;
194 fsl,port-config = <
195 IMX_AUDMUX_V2_PTCR_SYN
196 IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
197 };
198 };
199
200 &can1 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_flexcan1>;
203 xceiver-supply = <®_can1_stby>;
204 status = "okay";
205 };
206
207 &clks {
208 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
209 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
210 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
211 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
212 };
213
214 &ecspi2 {
215 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_ecspi2>;
218 status = "okay";
219 };
220
221 &fec {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_enet>;
224 phy-mode = "rgmii-id";
225 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
226 status = "okay";
227 };
228
229 &gpmi {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_gpmi_nand>;
232 status = "okay";
233 };
234
235 &hdmi {
236 ddc-i2c-bus = <&i2c3>;
237 status = "okay";
238 };
239
240 &i2c1 {
241 clock-frequency = <100000>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c1>;
244 status = "okay";
245
246 gsc: gsc@20 {
247 compatible = "gw,gsc";
248 reg = <0x20>;
249 interrupt-parent = <&gpio1>;
250 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
251 interrupt-controller;
252 #interrupt-cells = <1>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255
256 adc {
257 compatible = "gw,gsc-adc";
258 #address-cells = <1>;
259 #size-cells = <0>;
260
261 channel@0 {
262 gw,mode = <0>;
263 reg = <0x00>;
264 label = "temp";
265 };
266
267 channel@2 {
268 gw,mode = <1>;
269 reg = <0x02>;
270 label = "vdd_vin";
271 };
272
273 channel@5 {
274 gw,mode = <1>;
275 reg = <0x05>;
276 label = "vdd_3p3";
277 };
278
279 channel@8 {
280 gw,mode = <1>;
281 reg = <0x08>;
282 label = "vdd_bat";
283 };
284
285 channel@b {
286 gw,mode = <1>;
287 reg = <0x0b>;
288 label = "vdd_5p0";
289 };
290
291 channel@e {
292 gw,mode = <1>;
293 reg = <0xe>;
294 label = "vdd_arm";
295 };
296
297 channel@11 {
298 gw,mode = <1>;
299 reg = <0x11>;
300 label = "vdd_soc";
301 };
302
303 channel@14 {
304 gw,mode = <1>;
305 reg = <0x14>;
306 label = "vdd_3p0";
307 };
308
309 channel@17 {
310 gw,mode = <1>;
311 reg = <0x17>;
312 label = "vdd_1p5";
313 };
314
315 channel@1d {
316 gw,mode = <1>;
317 reg = <0x1d>;
318 label = "vdd_1p8";
319 };
320
321 channel@20 {
322 gw,mode = <1>;
323 reg = <0x20>;
324 label = "vdd_1p0";
325 };
326
327 channel@23 {
328 gw,mode = <1>;
329 reg = <0x23>;
330 label = "vdd_2p5";
331 };
332
333 channel@26 {
334 gw,mode = <1>;
335 reg = <0x26>;
336 label = "vdd_gps";
337 };
338 };
339
340 fan-controller@2c {
341 compatible = "gw,gsc-fan";
342 reg = <0x2c>;
343 };
344 };
345
346 gsc_gpio: gpio@23 {
347 compatible = "nxp,pca9555";
348 reg = <0x23>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-parent = <&gsc>;
352 interrupts = <4>;
353 };
354
355 eeprom1: eeprom@50 {
356 compatible = "atmel,24c02";
357 reg = <0x50>;
358 pagesize = <16>;
359 };
360
361 eeprom2: eeprom@51 {
362 compatible = "atmel,24c02";
363 reg = <0x51>;
364 pagesize = <16>;
365 };
366
367 eeprom3: eeprom@52 {
368 compatible = "atmel,24c02";
369 reg = <0x52>;
370 pagesize = <16>;
371 };
372
373 eeprom4: eeprom@53 {
374 compatible = "atmel,24c02";
375 reg = <0x53>;
376 pagesize = <16>;
377 };
378
379 rtc: ds1672@68 {
380 compatible = "dallas,ds1672";
381 reg = <0x68>;
382 };
383 };
384
385 &i2c2 {
386 clock-frequency = <100000>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_i2c2>;
389 status = "okay";
390
391 pmic: pmic@8 {
392 compatible = "fsl,pfuze100";
393 reg = <0x08>;
394
395 regulators {
396 sw1a_reg: sw1ab {
397 regulator-min-microvolt = <300000>;
398 regulator-max-microvolt = <1875000>;
399 regulator-boot-on;
400 regulator-always-on;
401 regulator-ramp-delay = <6250>;
402 };
403
404 sw1c_reg: sw1c {
405 regulator-min-microvolt = <300000>;
406 regulator-max-microvolt = <1875000>;
407 regulator-boot-on;
408 regulator-always-on;
409 regulator-ramp-delay = <6250>;
410 };
411
412 sw2_reg: sw2 {
413 regulator-min-microvolt = <800000>;
414 regulator-max-microvolt = <3950000>;
415 regulator-boot-on;
416 regulator-always-on;
417 };
418
419 sw3a_reg: sw3a {
420 regulator-min-microvolt = <400000>;
421 regulator-max-microvolt = <1975000>;
422 regulator-boot-on;
423 regulator-always-on;
424 };
425
426 sw3b_reg: sw3b {
427 regulator-min-microvolt = <400000>;
428 regulator-max-microvolt = <1975000>;
429 regulator-boot-on;
430 regulator-always-on;
431 };
432
433 sw4_reg: sw4 {
434 regulator-min-microvolt = <800000>;
435 regulator-max-microvolt = <3300000>;
436 };
437
438 swbst_reg: swbst {
439 regulator-min-microvolt = <5000000>;
440 regulator-max-microvolt = <5150000>;
441 regulator-boot-on;
442 regulator-always-on;
443 };
444
445 snvs_reg: vsnvs {
446 regulator-min-microvolt = <1000000>;
447 regulator-max-microvolt = <3000000>;
448 regulator-boot-on;
449 regulator-always-on;
450 };
451
452 vref_reg: vrefddr {
453 regulator-boot-on;
454 regulator-always-on;
455 };
456
457 vgen1_reg: vgen1 {
458 regulator-min-microvolt = <800000>;
459 regulator-max-microvolt = <1550000>;
460 };
461
462 vgen2_reg: vgen2 {
463 regulator-min-microvolt = <800000>;
464 regulator-max-microvolt = <1550000>;
465 };
466
467 vgen3_reg: vgen3 {
468 regulator-min-microvolt = <1800000>;
469 regulator-max-microvolt = <3300000>;
470 };
471
472 vgen4_reg: vgen4 {
473 regulator-min-microvolt = <1800000>;
474 regulator-max-microvolt = <3300000>;
475 regulator-always-on;
476 };
477
478 vgen5_reg: vgen5 {
479 regulator-min-microvolt = <1800000>;
480 regulator-max-microvolt = <3300000>;
481 regulator-always-on;
482 };
483
484 vgen6_reg: vgen6 {
485 regulator-min-microvolt = <1800000>;
486 regulator-max-microvolt = <3300000>;
487 regulator-always-on;
488 };
489 };
490 };
491 };
492
493 &i2c3 {
494 clock-frequency = <100000>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_i2c3>;
497 status = "okay";
498
499 sgtl5000: audio-codec@a {
500 compatible = "fsl,sgtl5000";
501 reg = <0x0a>;
502 #sound-dai-cells = <0>;
503 clocks = <&clks IMX6QDL_CLK_CKO>;
504 VDDA-supply = <&sw4_reg>;
505 VDDIO-supply = <®_3p3v>;
506 };
507
508 touchscreen: egalax_ts@4 {
509 compatible = "eeti,egalax_ts";
510 reg = <0x04>;
511 interrupt-parent = <&gpio7>;
512 interrupts = <12 2>;
513 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
514 };
515
516 accel@1e {
517 compatible = "nxp,fxos8700";
518 reg = <0x1e>;
519 };
520 };
521
522 &ldb {
523 status = "okay";
524
525 lvds-channel@0 {
526 fsl,data-mapping = "spwg";
527 fsl,data-width = <18>;
528 status = "okay";
529
530 display-timings {
531 native-mode = <&timing0>;
532 timing0: timing-hsd100pxn1 {
533 clock-frequency = <65000000>;
534 hactive = <1024>;
535 vactive = <768>;
536 hback-porch = <220>;
537 hfront-porch = <40>;
538 vback-porch = <21>;
539 vfront-porch = <7>;
540 hsync-len = <60>;
541 vsync-len = <10>;
542 };
543 };
544 };
545 };
546
547 &pcie {
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_pcie>;
550 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
551 status = "okay";
552 };
553
554 &pwm1 {
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
557 status = "disabled";
558 };
559
560 &pwm2 {
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
563 status = "disabled";
564 };
565
566 &pwm3 {
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
569 status = "disabled";
570 };
571
572 &pwm4 {
573 pinctrl-names = "default", "state_dio";
574 pinctrl-0 = <&pinctrl_pwm4_backlight>;
575 pinctrl-1 = <&pinctrl_pwm4_dio>;
576 status = "okay";
577 };
578
579 &ssi1 {
580 status = "okay";
581 };
582
583 &ssi2 {
584 status = "okay";
585 };
586
587 &uart1 {
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_uart1>;
590 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
591 status = "okay";
592 };
593
594 &uart2 {
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_uart2>;
597 status = "okay";
598 };
599
600 &uart5 {
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_uart5>;
603 status = "okay";
604 };
605
606 &usbotg {
607 vbus-supply = <®_usb_otg_vbus>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&pinctrl_usbotg>;
610 disable-over-current;
611 status = "okay";
612 };
613
614 &usbh1 {
615 vbus-supply = <®_usb_h1_vbus>;
616 status = "okay";
617 };
618
619 &usdhc3 {
620 pinctrl-names = "default", "state_100mhz", "state_200mhz";
621 pinctrl-0 = <&pinctrl_usdhc3>;
622 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
623 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
624 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
625 vmmc-supply = <®_3p3v>;
626 no-1-8-v; /* firmware will remove if board revision supports */
627 status = "okay";
628 };
629
630 &wdog1 {
631 status = "disabled";
632 };
633
634 &wdog2 {
635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_wdog>;
637 fsl,ext-reset-output;
638 status = "okay";
639 };
640
641 &iomuxc {
642 pinctrl_audmux: audmuxgrp {
643 fsl,pins = <
644 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
645 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
646 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
647 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
648 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
649 MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
650 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
651 MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
652 >;
653 };
654
655 pinctrl_enet: enetgrp {
656 fsl,pins = <
657 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
658 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
659 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
660 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
661 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
662 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
663 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
664 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
665 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
666 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
667 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
668 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
669 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
670 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
671 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
672 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
673 >;
674 };
675
676 pinctrl_ecspi2: escpi2grp {
677 fsl,pins = <
678 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
679 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
680 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
681 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
682 >;
683 };
684
685 pinctrl_flexcan1: flexcan1grp {
686 fsl,pins = <
687 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
688 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
689 >;
690 };
691
692 pinctrl_gpio_leds: gpioledsgrp {
693 fsl,pins = <
694 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
695 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
696 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
697 >;
698 };
699
700 pinctrl_gpmi_nand: gpminandgrp {
701 fsl,pins = <
702 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
703 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
704 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
705 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
706 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
707 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
708 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
709 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
710 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
711 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
712 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
713 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
714 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
715 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
716 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
717 >;
718 };
719
720 pinctrl_i2c1: i2c1grp {
721 fsl,pins = <
722 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
723 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
724 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
725 >;
726 };
727
728 pinctrl_i2c2: i2c2grp {
729 fsl,pins = <
730 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
731 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
732 >;
733 };
734
735 pinctrl_i2c3: i2c3grp {
736 fsl,pins = <
737 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
738 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
739 >;
740 };
741
742 pinctrl_pcie: pciegrp {
743 fsl,pins = <
744 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
745 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
746 >;
747 };
748
749 pinctrl_pps: ppsgrp {
750 fsl,pins = <
751 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
752 >;
753 };
754
755 pinctrl_pwm1: pwm1grp {
756 fsl,pins = <
757 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
758 >;
759 };
760
761 pinctrl_pwm2: pwm2grp {
762 fsl,pins = <
763 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
764 >;
765 };
766
767 pinctrl_pwm3: pwm3grp {
768 fsl,pins = <
769 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
770 >;
771 };
772
773 pinctrl_pwm4_backlight: pwm4grpbacklight {
774 fsl,pins = <
775 /* LVDS_PWM J6.5 */
776 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
777 >;
778 };
779
780 pinctrl_pwm4_dio: pwm4grpdio {
781 fsl,pins = <
782 /* DIO3 J16.4 */
783 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
784 >;
785 };
786
787 pinctrl_reg_can1: regcan1grp {
788 fsl,pins = <
789 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
790 >;
791 };
792
793 pinctrl_uart1: uart1grp {
794 fsl,pins = <
795 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
796 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
797 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
798 >;
799 };
800
801 pinctrl_uart2: uart2grp {
802 fsl,pins = <
803 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
804 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
805 >;
806 };
807
808 pinctrl_uart5: uart5grp {
809 fsl,pins = <
810 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
811 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
812 >;
813 };
814
815 pinctrl_usbotg: usbotggrp {
816 fsl,pins = <
817 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
818 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
819 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059
820 >;
821 };
822
823 pinctrl_usdhc3: usdhc3grp {
824 fsl,pins = <
825 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
826 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
827 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
828 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
829 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
830 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
831 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
832 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
833 >;
834 };
835
836 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
837 fsl,pins = <
838 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
839 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
840 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
841 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
842 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
843 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
844 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
845 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
846 >;
847 };
848
849 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
850 fsl,pins = <
851 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
852 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
853 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
854 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
855 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
856 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
857 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
858 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
859 >;
860 };
861
862 pinctrl_wdog: wdoggrp {
863 fsl,pins = <
864 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
865 >;
866 };
867 };
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