1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9
10 / {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 nand = &gpmi;
16 usb0 = &usbh1;
17 usb1 = &usbotg;
18 };
19
20 chosen {
21 stdout-path = &uart2;
22 };
23
24 gpio-keys {
25 compatible = "gpio-keys";
26
27 user-pb {
28 label = "user_pb";
29 gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>;
30 linux,code = <BTN_0>;
31 };
32
33 user-pb1x {
34 label = "user_pb1x";
35 linux,code = <BTN_1>;
36 interrupt-parent = <&gsc>;
37 interrupts = <0>;
38 };
39
40 key-erased {
41 label = "key-erased";
42 linux,code = <BTN_2>;
43 interrupt-parent = <&gsc>;
44 interrupts = <1>;
45 };
46
47 eeprom-wp {
48 label = "eeprom_wp";
49 linux,code = <BTN_3>;
50 interrupt-parent = <&gsc>;
51 interrupts = <2>;
52 };
53
54 tamper {
55 label = "tamper";
56 linux,code = <BTN_4>;
57 interrupt-parent = <&gsc>;
58 interrupts = <5>;
59 };
60
61 switch-hold {
62 label = "switch_hold";
63 linux,code = <BTN_5>;
64 interrupt-parent = <&gsc>;
65 interrupts = <7>;
66 };
67 };
68
69 leds {
70 compatible = "gpio-leds";
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_gpio_leds>;
73
74 led0: led-user1 {
75 label = "user1";
76 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
77 default-state = "on";
78 linux,default-trigger = "heartbeat";
79 };
80
81 led1: led-user2 {
82 label = "user2";
83 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
84 default-state = "off";
85 };
86 };
87
88 memory@10000000 {
89 device_type = "memory";
90 reg = <0x10000000 0x20000000>;
91 };
92
93 pps {
94 compatible = "pps-gpio";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_pps>;
97 gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
98 status = "okay";
99 };
100
101 reg_3p3v: regulator-3p3v {
102 compatible = "regulator-fixed";
103 regulator-name = "3P3V";
104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>;
106 regulator-always-on;
107 };
108
109 reg_5p0v: regulator-5p0v {
110 compatible = "regulator-fixed";
111 regulator-name = "5P0V";
112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>;
114 regulator-always-on;
115 };
116 };
117
118 &fec {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_enet>;
121 phy-mode = "rgmii-id";
122 status = "okay";
123 };
124
125 &gpmi {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_gpmi_nand>;
128 status = "okay";
129 };
130
131 &i2c1 {
132 clock-frequency = <100000>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_i2c1>;
135 status = "okay";
136
137 gsc: gsc@20 {
138 compatible = "gw,gsc";
139 reg = <0x20>;
140 interrupt-parent = <&gpio1>;
141 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
142 interrupt-controller;
143 #interrupt-cells = <1>;
144 #size-cells = <0>;
145
146 adc {
147 compatible = "gw,gsc-adc";
148 #address-cells = <1>;
149 #size-cells = <0>;
150
151 channel@6 {
152 gw,mode = <0>;
153 reg = <0x06>;
154 label = "temp";
155 };
156
157 channel@8 {
158 gw,mode = <3>;
159 reg = <0x08>;
160 label = "vdd_bat";
161 };
162
163 channel@82 {
164 gw,mode = <2>;
165 reg = <0x82>;
166 label = "vdd_vin";
167 gw,voltage-divider-ohms = <22100 1000>;
168 gw,voltage-offset-microvolt = <800000>;
169 };
170
171 channel@84 {
172 gw,mode = <2>;
173 reg = <0x84>;
174 label = "vdd_5p0";
175 gw,voltage-divider-ohms = <22100 10000>;
176 };
177
178 channel@86 {
179 gw,mode = <2>;
180 reg = <0x86>;
181 label = "vdd_3p3";
182 gw,voltage-divider-ohms = <10000 10000>;
183 };
184
185 channel@88 {
186 gw,mode = <2>;
187 reg = <0x88>;
188 label = "vdd_2p5";
189 gw,voltage-divider-ohms = <10000 10000>;
190 };
191
192 channel@8c {
193 gw,mode = <2>;
194 reg = <0x8c>;
195 label = "vdd_arm";
196 };
197
198 channel@8e {
199 gw,mode = <2>;
200 reg = <0x8e>;
201 label = "vdd_soc";
202 };
203
204 channel@90 {
205 gw,mode = <2>;
206 reg = <0x90>;
207 label = "vdd_1p5";
208 };
209
210 channel@92 {
211 gw,mode = <2>;
212 reg = <0x92>;
213 label = "vdd_1p0";
214 };
215
216 channel@98 {
217 gw,mode = <2>;
218 reg = <0x98>;
219 label = "vdd_3p0";
220 };
221
222 channel@9a {
223 gw,mode = <2>;
224 reg = <0x9a>;
225 label = "vdd_an1";
226 gw,voltage-divider-ohms = <10000 10000>;
227 };
228
229 channel@a2 {
230 gw,mode = <2>;
231 reg = <0xa2>;
232 label = "vdd_gsc";
233 gw,voltage-divider-ohms = <10000 10000>;
234 };
235 };
236 };
237
238 gsc_gpio: gpio@23 {
239 compatible = "nxp,pca9555";
240 reg = <0x23>;
241 gpio-controller;
242 #gpio-cells = <2>;
243 interrupt-parent = <&gsc>;
244 interrupts = <4>;
245 };
246
247 eeprom@50 {
248 compatible = "atmel,24c02";
249 reg = <0x50>;
250 pagesize = <16>;
251 };
252
253 eeprom@51 {
254 compatible = "atmel,24c02";
255 reg = <0x51>;
256 pagesize = <16>;
257 };
258
259 eeprom@52 {
260 compatible = "atmel,24c02";
261 reg = <0x52>;
262 pagesize = <16>;
263 };
264
265 eeprom@53 {
266 compatible = "atmel,24c02";
267 reg = <0x53>;
268 pagesize = <16>;
269 };
270
271 rtc@68 {
272 compatible = "dallas,ds1672";
273 reg = <0x68>;
274 };
275 };
276
277 &i2c2 {
278 clock-frequency = <100000>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_i2c2>;
281 status = "okay";
282 };
283
284 &i2c3 {
285 clock-frequency = <100000>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_i2c3>;
288 status = "okay";
289 };
290
291 &pcie {
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_pcie>;
294 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
295 status = "okay";
296 };
297
298 &pwm2 {
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
301 status = "disabled";
302 };
303
304 &pwm3 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
307 status = "disabled";
308 };
309
310 &pwm4 {
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
313 status = "disabled";
314 };
315
316 &uart1 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_uart1>;
319 status = "okay";
320 };
321
322 &uart2 {
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_uart2>;
325 status = "okay";
326 };
327
328 &uart3 {
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_uart3>;
331 status = "okay";
332 };
333
334 &uart5 {
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_uart5>;
337 status = "okay";
338 };
339
340 &usbotg {
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_usbotg>;
343 disable-over-current;
344 status = "okay";
345 };
346
347 &usbh1 {
348 status = "okay";
349 };
350
351 &wdog1 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_wdog>;
354 fsl,ext-reset-output;
355 };
356
357 &iomuxc {
358 pinctrl_enet: enetgrp {
359 fsl,pins = <
360 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
361 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
362 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
363 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
364 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
365 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
366 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
367 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
368 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
369 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
370 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
371 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
372 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
373 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
374 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
375 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
376 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
377 >;
378 };
379
380 pinctrl_gpio_leds: gpioledsgrp {
381 fsl,pins = <
382 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
383 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
384 >;
385 };
386
387 pinctrl_gpmi_nand: gpminandgrp {
388 fsl,pins = <
389 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
390 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
391 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
392 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
393 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
394 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
395 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
396 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
397 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
398 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
399 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
400 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
401 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
402 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
403 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
404 >;
405 };
406
407 pinctrl_i2c1: i2c1grp {
408 fsl,pins = <
409 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
410 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
411 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
412 >;
413 };
414
415 pinctrl_i2c2: i2c2grp {
416 fsl,pins = <
417 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
418 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
419 >;
420 };
421
422 pinctrl_i2c3: i2c3grp {
423 fsl,pins = <
424 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
425 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
426 >;
427 };
428
429 pinctrl_pcie: pciegrp {
430 fsl,pins = <
431 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
432 >;
433 };
434
435 pinctrl_pps: ppsgrp {
436 fsl,pins = <
437 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1
438 >;
439 };
440
441 pinctrl_pwm2: pwm2grp {
442 fsl,pins = <
443 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
444 >;
445 };
446
447 pinctrl_pwm3: pwm3grp {
448 fsl,pins = <
449 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
450 >;
451 };
452
453 pinctrl_pwm4: pwm4grp {
454 fsl,pins = <
455 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
456 >;
457 };
458
459 pinctrl_uart1: uart1grp {
460 fsl,pins = <
461 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
462 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
463 >;
464 };
465
466 pinctrl_uart2: uart2grp {
467 fsl,pins = <
468 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
469 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
470 >;
471 };
472
473 pinctrl_uart3: uart3grp {
474 fsl,pins = <
475 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
476 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
477 >;
478 };
479
480 pinctrl_uart5: uart5grp {
481 fsl,pins = <
482 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
483 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
484 >;
485 };
486
487 pinctrl_usbotg: usbotggrp {
488 fsl,pins = <
489 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
490 >;
491 };
492
493 pinctrl_wdog: wdoggrp {
494 fsl,pins = <
495 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
496 >;
497 };
498 };
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