1 // SPDX-License-Identifier: GPL-2.0 OR X11
2 /*
3 * Copyright (C) 2016 Amarula Solutions B.V.
4 * Copyright (C) 2016 Engicam S.r.l.
5 */
6
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/sound/fsl-imx-audmux.h>
10
11 / {
12 memory@10000000 {
13 device_type = "memory";
14 reg = <0x10000000 0x80000000>;
15 };
16
17 chosen {
18 stdout-path = &uart4;
19 };
20
21 backlight_lvds: backlight-lvds {
22 compatible = "pwm-backlight";
23 pwms = <&pwm3 0 100000 0>;
24 brightness-levels = <0 4 8 16 32 64 128 255>;
25 default-brightness-level = <7>;
26 };
27
28 reg_1p8v: regulator-1p8v {
29 compatible = "regulator-fixed";
30 regulator-name = "1P8V";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
33 regulator-boot-on;
34 regulator-always-on;
35 };
36
37 reg_2p5v: regulator-2p5v {
38 compatible = "regulator-fixed";
39 regulator-name = "2P5V";
40 regulator-min-microvolt = <2500000>;
41 regulator-max-microvolt = <2500000>;
42 regulator-boot-on;
43 regulator-always-on;
44 };
45
46 reg_3p3v: regulator-3p3v {
47 compatible = "regulator-fixed";
48 regulator-name = "3P3V";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 regulator-boot-on;
52 regulator-always-on;
53 };
54
55 reg_usb_h1_vbus: regulator-usb-h1-vbus {
56 compatible = "regulator-fixed";
57 regulator-name = "usb_h1_vbus";
58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>;
60 regulator-boot-on;
61 regulator-always-on;
62 };
63
64 reg_usb_otg_vbus: regulator-usb-otg-vbus {
65 compatible = "regulator-fixed";
66 regulator-name = "usb_otg_vbus";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
69 regulator-boot-on;
70 regulator-always-on;
71 };
72
73 rmii_clk: clock-rmii-clk {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <25000000>; /* 25MHz for example */
77 };
78
79 sound {
80 compatible = "simple-audio-card";
81 simple-audio-card,name = "imx6qdl-icore-sgtl5000";
82 simple-audio-card,format = "i2s";
83 simple-audio-card,bitclock-master = <&dailink_master>;
84 simple-audio-card,frame-master = <&dailink_master>;
85 simple-audio-card,widgets =
86 "Microphone", "Mic Jack",
87 "Headphone", "Headphone Jack",
88 "Line", "Line In Jack",
89 "Speaker", "Line Out Jack",
90 "Speaker", "Ext Spk";
91 simple-audio-card,routing =
92 "MIC_IN", "Mic Jack",
93 "Mic Jack", "Mic Bias",
94 "Headphone Jack", "HP_OUT";
95
96 simple-audio-card,cpu {
97 sound-dai = <&ssi1>;
98 };
99
100 dailink_master: simple-audio-card,codec {
101 sound-dai = <&sgtl5000>;
102 };
103 };
104 };
105
106 &audmux {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_audmux>;
109 status = "okay";
110
111
112 mux-ssi1 {
113 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
114 fsl,port-config = <
115 (IMX_AUDMUX_V2_PTCR_TFSDIR |
116 IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
117 IMX_AUDMUX_V2_PTCR_TCLKDIR |
118 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
119 IMX_AUDMUX_V2_PTCR_SYN)
120 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
121 >;
122 };
123
124 mux-aud4 {
125 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
126 fsl,port-config = <
127 IMX_AUDMUX_V2_PTCR_SYN
128 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
129 >;
130 };
131 };
132
133 &can1 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_flexcan1>;
136 xceiver-supply = <®_3p3v>;
137 };
138
139 &can2 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_flexcan2>;
142 xceiver-supply = <®_3p3v>;
143 };
144
145 &clks {
146 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
147 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
148 };
149
150 &fec {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_enet>;
153 clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
154 phy-mode = "rmii";
155 phy-handle = <ð_phy>;
156 status = "okay";
157
158 mdio {
159 #address-cells = <1>;
160 #size-cells = <0>;
161
162 eth_phy: ethernet-phy@0 {
163 compatible = "ethernet-phy-ieee802.3-c22";
164 reg = <0>;
165 reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
166 reset-assert-us = <4000>;
167 reset-deassert-us = <4000>;
168 };
169 };
170 };
171
172 &gpmi {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_gpmi_nand>;
175 nand-on-flash-bbt;
176 status = "okay";
177 };
178
179 &i2c1 {
180 clock-frequency = <100000>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_i2c1>;
183 status = "okay";
184 };
185
186 &i2c2 {
187 clock-frequency = <100000>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_i2c2>;
190 status = "okay";
191 };
192
193 &i2c3 {
194 clock-frequency = <100000>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_i2c3>;
197 status = "okay";
198
199 ov5640: camera@3c {
200 compatible = "ovti,ov5640";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_ov5640>;
203 reg = <0x3c>;
204 clocks = <&clks IMX6QDL_CLK_CKO>;
205 clock-names = "xclk";
206 DOVDD-supply = <®_1p8v>;
207 AVDD-supply = <®_3p3v>;
208 DVDD-supply = <®_3p3v>;
209 powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
210 reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
211 status = "disabled";
212
213 port {
214 ov5640_to_mipi_csi2: endpoint {
215 remote-endpoint = <&mipi_csi2_in>;
216 clock-lanes = <0>;
217 data-lanes = <1 2>;
218 };
219 };
220 };
221
222 sgtl5000: codec@a {
223 #sound-dai-cells = <0>;
224 compatible = "fsl,sgtl5000";
225 reg = <0x0a>;
226 clocks = <&clks IMX6QDL_CLK_CKO>;
227 VDDA-supply = <®_2p5v>;
228 VDDIO-supply = <®_3p3v>;
229 VDDD-supply = <®_1p8v>;
230 };
231 };
232
233 &mipi_csi {
234 status = "disabled";
235
236 port@0 {
237 reg = <0>;
238
239 mipi_csi2_in: endpoint {
240 remote-endpoint = <&ov5640_to_mipi_csi2>;
241 clock-lanes = <0>;
242 data-lanes = <1 2>;
243 };
244 };
245 };
246
247 &pwm3 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_pwm3>;
250 status = "okay";
251 };
252
253 &ssi1 {
254 fsl,mode = "i2s-slave";
255 status = "okay";
256 };
257
258 &uart4 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_uart4>;
261 status = "okay";
262 };
263
264 &usbh1 {
265 vbus-supply = <®_usb_h1_vbus>;
266 disable-over-current;
267 status = "okay";
268 };
269
270 &usbotg {
271 vbus-supply = <®_usb_otg_vbus>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_usbotg>;
274 disable-over-current;
275 status = "okay";
276 };
277
278 &usdhc1 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_usdhc1>;
281 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
282 no-1-8-v;
283 status = "okay";
284 };
285
286 &usdhc3 {
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_usdhc3>;
289 no-1-8-v;
290 non-removable;
291 status = "disabled";
292 };
293
294 &iomuxc {
295 pinctrl_audmux: audmuxgrp {
296 fsl,pins = <
297 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
298 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
299 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
300 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
301 >;
302 };
303
304 pinctrl_enet: enetgrp {
305 fsl,pins = <
306 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
307 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
308 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
309 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
310 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
311 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
312 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
313 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
314 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
315 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
316 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
317 >;
318 };
319
320 pinctrl_flexcan1: flexcan1grp {
321 fsl,pins = <
322 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
323 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
324 >;
325 };
326
327 pinctrl_flexcan2: flexcan2grp {
328 fsl,pins = <
329 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
330 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
331 >;
332 };
333
334 pinctrl_gpmi_nand: gpminandgrp {
335 fsl,pins = <
336 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
337 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
338 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
339 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
340 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
341 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
342 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
343 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
344 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
345 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
346 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
347 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
348 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
349 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
350 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
351 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
352 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
353 >;
354 };
355
356 pinctrl_i2c1: i2c1grp {
357 fsl,pins = <
358 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
359 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
360 >;
361 };
362
363 pinctrl_i2c2: i2c2grp {
364 fsl,pins = <
365 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
366 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
367 >;
368 };
369
370 pinctrl_i2c3: i2c3grp {
371 fsl,pins = <
372 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
373 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
374 >;
375 };
376
377 pinctrl_ov5640: ov5640grp {
378 fsl,pins = <
379 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0
380 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
381 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
382 >;
383 };
384
385 pinctrl_uart4: uart4grp {
386 fsl,pins = <
387 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
388 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
389 >;
390 };
391
392 pinctrl_pwm3: pwm3grp {
393 fsl,pins = <
394 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
395 >;
396 };
397
398 pinctrl_usbotg: usbotggrp {
399 fsl,pins = <
400 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
401 >;
402 };
403
404 pinctrl_usdhc1: usdhc1grp {
405 fsl,pins = <
406 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
407 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
408 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
409 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
410 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
411 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
412 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
413 >;
414 };
415
416 pinctrl_usdhc3: usdhc3grp {
417 fsl,pins = <
418 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
419 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
420 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
421 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
422 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
423 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
424 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
425 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
426 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
427 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
428 >;
429 };
430 };
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