1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/regulator/dlg,da9063-regulator.h>
9
10 / {
11 aliases {
12 rtc1 = &da9062_rtc;
13 rtc2 = &snvs_rtc;
14 };
15
16 /*
17 * Set the minimum memory size here and
18 * let the bootloader set the real size.
19 */
20 memory@10000000 {
21 device_type = "memory";
22 reg = <0x10000000 0x8000000>;
23 };
24
25 gpio_leds_som: somleds {
26 compatible = "gpio-leds";
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_gpioleds_som>;
29
30 som-led-green {
31 label = "phycore:green";
32 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
33 linux,default-trigger = "heartbeat";
34 };
35 };
36 };
37
38 &ecspi1 {
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_ecspi1>;
41 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
42 status = "okay";
43
44 m25p80: flash@0 {
45 compatible = "jedec,spi-nor";
46 spi-max-frequency = <20000000>;
47 reg = <0>;
48 status = "disabled";
49 };
50 };
51
52 &fec {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_enet>;
55 phy-handle = <ðphy>;
56 phy-mode = "rgmii";
57 phy-supply = <&vdd_eth_io>;
58 phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
59 status = "disabled";
60
61 mdio {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 ethphy: ethernet-phy@3 {
66 reg = <3>;
67 txc-skew-ps = <1680>;
68 rxc-skew-ps = <1860>;
69 };
70 };
71 };
72
73 &gpmi {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_gpmi_nand>;
76 nand-on-flash-bbt;
77 status = "disabled";
78 };
79
80 &i2c3 {
81 pinctrl-names = "default", "gpio";
82 pinctrl-0 = <&pinctrl_i2c3>;
83 pinctrl-1 = <&pinctrl_i2c3_gpio>;
84 scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
85 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
86 clock-frequency = <400000>;
87 status = "okay";
88
89 eeprom@50 {
90 compatible = "st,24c32", "atmel,24c32";
91 pagesize = <32>;
92 reg = <0x50>;
93 };
94
95 pmic: pmic@58 {
96 compatible = "dlg,da9062";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_pmic>;
99 reg = <0x58>;
100 interrupt-parent = <&gpio1>;
101 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
104 gpio-controller;
105 #gpio-cells = <2>;
106
107 da9062_rtc: rtc {
108 compatible = "dlg,da9062-rtc";
109 };
110
111 da9062_onkey: onkey {
112 compatible = "dlg,da9062-onkey";
113 };
114
115 watchdog {
116 compatible = "dlg,da9062-watchdog";
117 dlg,use-sw-pm;
118 };
119
120 thermal {
121 compatible = "dlg,da9062-thermal";
122 status = "disabled";
123 };
124
125 gpio {
126 compatible = "dlg,da9062-gpio";
127 status = "disabled";
128 };
129
130 regulators {
131 vdd_arm: buck1 {
132 regulator-name = "vdd_arm";
133 regulator-min-microvolt = <925000>;
134 regulator-max-microvolt = <1380000>;
135 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
136 regulator-always-on;
137 };
138
139 vdd_soc: buck2 {
140 regulator-name = "vdd_soc";
141 regulator-min-microvolt = <1150000>;
142 regulator-max-microvolt = <1380000>;
143 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
144 regulator-always-on;
145 };
146
147 vdd_ddr3_1p5: buck3 {
148 regulator-name = "vdd_ddr3";
149 regulator-min-microvolt = <1500000>;
150 regulator-max-microvolt = <1500000>;
151 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
152 regulator-always-on;
153 };
154
155 vdd_eth_1p2: buck4 {
156 regulator-name = "vdd_eth";
157 regulator-min-microvolt = <1200000>;
158 regulator-max-microvolt = <1200000>;
159 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
160 regulator-always-on;
161 };
162
163 vdd_snvs: ldo1 {
164 regulator-name = "vdd_snvs";
165 regulator-min-microvolt = <3000000>;
166 regulator-max-microvolt = <3000000>;
167 regulator-always-on;
168 };
169
170 vdd_high: ldo2 {
171 regulator-name = "vdd_high";
172 regulator-min-microvolt = <3000000>;
173 regulator-max-microvolt = <3000000>;
174 regulator-always-on;
175 };
176
177 vdd_eth_io: ldo3 {
178 regulator-name = "vdd_eth_io";
179 regulator-min-microvolt = <2500000>;
180 regulator-max-microvolt = <2500000>;
181 };
182
183 vdd_emmc_1p8: ldo4 {
184 regulator-name = "vdd_emmc";
185 regulator-min-microvolt = <1800000>;
186 regulator-max-microvolt = <1800000>;
187 };
188 };
189 };
190 };
191
192 ®_arm {
193 vin-supply = <&vdd_arm>;
194 };
195
196 ®_pu {
197 vin-supply = <&vdd_soc>;
198 };
199
200 ®_soc {
201 vin-supply = <&vdd_soc>;
202 };
203
204 &snvs_poweroff {
205 status = "okay";
206 };
207
208 &usdhc4 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_usdhc4>;
211 bus-width = <8>;
212 non-removable;
213 status = "disabled";
214 };
215
216 &iomuxc {
217 pinctrl_enet: enetgrp {
218 fsl,pins = <
219 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
220 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
221 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
222 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
223 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
224 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
225 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
226 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
227 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
228 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
229 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
230 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
231 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
232 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
233 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
234 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
235 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
236 >;
237 };
238
239 pinctrl_gpioleds_som: gpioledssomgrp {
240 fsl,pins = <
241 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
242 >;
243 };
244
245 pinctrl_gpmi_nand: gpminandgrp {
246 fsl,pins = <
247 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
248 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
249 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
250 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
251 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
252 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
253 MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
254 MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
255 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
256 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
257 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
258 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
259 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
260 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
261 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
262 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
263 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
264 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
265 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
266 >;
267 };
268
269 pinctrl_i2c3: i2c3grp {
270 fsl,pins = <
271 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
272 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
273 >;
274 };
275
276 pinctrl_i2c3_gpio: i2c3gpiogrp {
277 fsl,pins = <
278 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
279 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
280 >;
281 };
282
283 pinctrl_ecspi1: ecspi1grp {
284 fsl,pins = <
285 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
286 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
287 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
288 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
289 >;
290 };
291
292 pinctrl_pmic: pmicgrp {
293 fsl,pins = <
294 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
295 >;
296 };
297
298 pinctrl_usdhc4: usdhc4grp {
299 fsl,pins = <
300 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
301 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
302 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
303 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
304 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
305 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
306 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
307 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
308 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
309 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
310 >;
311 };
312 };
313
314 &wdog1 {
315 /*
316 * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also
317 * used for reboot, does not reset all external PMIC voltages on reset.
318 */
319 status = "disabled";
320 };
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