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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6qdl-tx6.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
  3  *
  4  * This file is dual-licensed: you can use it either under the terms
  5  * of the GPL or the X11 license, at your option. Note that this dual
  6  * licensing only applies to this file, and not this project as a
  7  * whole.
  8  *
  9  *  a) This file is free software; you can redistribute it and/or
 10  *     modify it under the terms of the GNU General Public License
 11  *     version 2 as published by the Free Software Foundation.
 12  *
 13  *     This file is distributed in the hope that it will be useful,
 14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  *     GNU General Public License for more details.
 17  *
 18  * Or, alternatively,
 19  *
 20  *  b) Permission is hereby granted, free of charge, to any person
 21  *     obtaining a copy of this software and associated documentation
 22  *     files (the "Software"), to deal in the Software without
 23  *     restriction, including without limitation the rights to use,
 24  *     copy, modify, merge, publish, distribute, sublicense, and/or
 25  *     sell copies of the Software, and to permit persons to whom the
 26  *     Software is furnished to do so, subject to the following
 27  *     conditions:
 28  *
 29  *     The above copyright notice and this permission notice shall be
 30  *     included in all copies or substantial portions of the Software.
 31  *
 32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 39  *     OTHER DEALINGS IN THE SOFTWARE.
 40  */
 41 
 42 #include <dt-bindings/gpio/gpio.h>
 43 #include <dt-bindings/input/input.h>
 44 #include <dt-bindings/interrupt-controller/irq.h>
 45 #include <dt-bindings/pwm/pwm.h>
 46 #include <dt-bindings/sound/fsl-imx-audmux.h>
 47 
 48 / {
 49         aliases {
 50                 can0 = &can2;
 51                 can1 = &can1;
 52                 ethernet0 = &fec;
 53                 lcdif-23bit-pins-a = &pinctrl_disp0_1;
 54                 lcdif-24bit-pins-a = &pinctrl_disp0_2;
 55                 pwm0 = &pwm1;
 56                 pwm1 = &pwm2;
 57                 reg-can-xcvr = &reg_can_xcvr;
 58                 stk5led = &user_led;
 59                 usbotg = &usbotg;
 60                 sdhc0 = &usdhc1;
 61                 sdhc1 = &usdhc2;
 62         };
 63 
 64         memory@10000000 {
 65                 device_type = "memory";
 66                 reg = <0x10000000 0>; /* will be filled by U-Boot */
 67         };
 68 
 69         clocks {
 70                 #address-cells = <1>;
 71                 #size-cells = <0>;
 72 
 73                 mclk: clock@0 {
 74                         compatible = "fixed-clock";
 75                         reg = <0>;
 76                         #clock-cells = <0>;
 77                         clock-frequency = <26000000>;
 78                 };
 79         };
 80 
 81         gpio-keys {
 82                 compatible = "gpio-keys";
 83 
 84                 power {
 85                         label = "Power Button";
 86                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 87                         linux,code = <KEY_POWER>;
 88                         wakeup-source;
 89                 };
 90         };
 91 
 92         leds {
 93                 compatible = "gpio-leds";
 94 
 95                 user_led: led-user {
 96                         label = "Heartbeat";
 97                         pinctrl-names = "default";
 98                         pinctrl-0 = <&pinctrl_user_led>;
 99                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
100                         linux,default-trigger = "heartbeat";
101                 };
102         };
103 
104         reg_3v3_etn: regulator-3v3-etn {
105                 compatible = "regulator-fixed";
106                 regulator-name = "3V3_ETN";
107                 regulator-min-microvolt = <3300000>;
108                 regulator-max-microvolt = <3300000>;
109                 pinctrl-names = "default";
110                 pinctrl-0 = <&pinctrl_etnphy_power>;
111                 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
112                 enable-active-high;
113         };
114 
115         reg_2v5: regulator-2v5 {
116                 compatible = "regulator-fixed";
117                 regulator-name = "2V5";
118                 regulator-min-microvolt = <2500000>;
119                 regulator-max-microvolt = <2500000>;
120                 regulator-always-on;
121         };
122 
123         reg_3v3: regulator-3v3 {
124                 compatible = "regulator-fixed";
125                 regulator-name = "3V3";
126                 regulator-min-microvolt = <3300000>;
127                 regulator-max-microvolt = <3300000>;
128                 regulator-always-on;
129         };
130 
131         reg_can_xcvr: regulator-can-xcvr {
132                 compatible = "regulator-fixed";
133                 regulator-name = "CAN XCVR";
134                 regulator-min-microvolt = <3300000>;
135                 regulator-max-microvolt = <3300000>;
136                 pinctrl-names = "default";
137                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
138                 gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
139         };
140 
141         reg_lcd0_pwr: regulator-lcd0-pwr {
142                 compatible = "regulator-fixed";
143                 regulator-name = "LCD0 POWER";
144                 regulator-min-microvolt = <3300000>;
145                 regulator-max-microvolt = <3300000>;
146                 pinctrl-names = "default";
147                 pinctrl-0 = <&pinctrl_lcd0_pwr>;
148                 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
149                 enable-active-high;
150                 status = "disabled";
151         };
152 
153         reg_lcd1_pwr: regulator-lcd1-pwr {
154                 compatible = "regulator-fixed";
155                 regulator-name = "LCD1 POWER";
156                 regulator-min-microvolt = <3300000>;
157                 regulator-max-microvolt = <3300000>;
158                 pinctrl-names = "default";
159                 pinctrl-0 = <&pinctrl_lcd1_pwr>;
160                 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
161                 enable-active-high;
162                 status = "disabled";
163         };
164 
165         reg_usbh1_vbus: regulator-usbh1-vbus {
166                 compatible = "regulator-fixed";
167                 regulator-name = "usbh1_vbus";
168                 regulator-min-microvolt = <5000000>;
169                 regulator-max-microvolt = <5000000>;
170                 pinctrl-names = "default";
171                 pinctrl-0 = <&pinctrl_usbh1_vbus>;
172                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
173                 enable-active-high;
174         };
175 
176         reg_usbotg_vbus: regulator-usbotg-vbus {
177                 compatible = "regulator-fixed";
178                 regulator-name = "usbotg_vbus";
179                 regulator-min-microvolt = <5000000>;
180                 regulator-max-microvolt = <5000000>;
181                 pinctrl-names = "default";
182                 pinctrl-0 = <&pinctrl_usbotg_vbus>;
183                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
184                 enable-active-high;
185         };
186 
187         sound {
188                 compatible = "karo,imx6qdl-tx6-sgtl5000",
189                              "simple-audio-card";
190                 simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio";
191                 pinctrl-names = "default";
192                 pinctrl-0 = <&pinctrl_audmux>;
193                 simple-audio-card,format = "i2s";
194                 simple-audio-card,bitclock-master = <&codec_dai>;
195                 simple-audio-card,frame-master = <&codec_dai>;
196                 simple-audio-card,widgets =
197                         "Microphone", "Mic Jack",
198                         "Line", "Line In",
199                         "Line", "Line Out",
200                         "Headphone", "Headphone Jack";
201                 simple-audio-card,routing =
202                         "MIC_IN", "Mic Jack",
203                         "Mic Jack", "Mic Bias",
204                         "Headphone Jack", "HP_OUT";
205 
206                 cpu_dai: simple-audio-card,cpu {
207                         sound-dai = <&ssi1>;
208                 };
209 
210                 codec_dai: simple-audio-card,codec {
211                         sound-dai = <&sgtl5000>;
212                 };
213         };
214 };
215 
216 &audmux {
217         status = "okay";
218 
219         mux-ssi1 {
220                 fsl,audmux-port = <0>;
221                 fsl,port-config = <
222                         (IMX_AUDMUX_V2_PTCR_SYN |
223                         IMX_AUDMUX_V2_PTCR_TFSEL(4) |
224                         IMX_AUDMUX_V2_PTCR_TCSEL(4) |
225                         IMX_AUDMUX_V2_PTCR_TFSDIR |
226                         IMX_AUDMUX_V2_PTCR_TCLKDIR)
227                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
228                 >;
229         };
230 
231         mux-pins5 {
232                 fsl,audmux-port = <4>;
233                 fsl,port-config = <
234                         IMX_AUDMUX_V2_PTCR_SYN
235                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
236                 >;
237         };
238 };
239 
240 &can1 {
241         pinctrl-names = "default";
242         pinctrl-0 = <&pinctrl_flexcan1>;
243         xceiver-supply = <&reg_can_xcvr>;
244         status = "okay";
245 };
246 
247 &can2 {
248         pinctrl-names = "default";
249         pinctrl-0 = <&pinctrl_flexcan2>;
250         xceiver-supply = <&reg_can_xcvr>;
251         status = "okay";
252 };
253 
254 &ecspi1 {
255         pinctrl-names = "default";
256         pinctrl-0 = <&pinctrl_ecspi1>;
257         cs-gpios = <
258                 &gpio2 30 GPIO_ACTIVE_HIGH
259                 &gpio3 19 GPIO_ACTIVE_HIGH
260         >;
261         status = "disabled";
262 };
263 
264 &fec {
265         pinctrl-names = "default";
266         pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
267         phy-mode = "rmii";
268         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
269         phy-reset-post-delay = <10>;
270         phy-handle = <&etnphy>;
271         phy-supply = <&reg_3v3_etn>;
272         status = "okay";
273 
274         mdio {
275                 #address-cells = <1>;
276                 #size-cells = <0>;
277 
278                 etnphy: ethernet-phy@0 {
279                         compatible = "ethernet-phy-ieee802.3-c22";
280                         reg = <0>;
281                         pinctrl-names = "default";
282                         pinctrl-0 = <&pinctrl_etnphy_int>;
283                         interrupt-parent = <&gpio7>;
284                         interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
285                 };
286         };
287 };
288 
289 &gpmi {
290         pinctrl-names = "default";
291         pinctrl-0 = <&pinctrl_gpmi_nand>;
292         nand-on-flash-bbt;
293         fsl,no-blockmark-swap;
294         status = "okay";
295 };
296 
297 &i2c1 {
298         pinctrl-names = "default", "gpio";
299         pinctrl-0 = <&pinctrl_i2c1>;
300         pinctrl-1 = <&pinctrl_i2c1_gpio>;
301         scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
302         sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
303         clock-frequency = <400000>;
304         status = "okay";
305 
306         ds1339: rtc@68 {
307                 compatible = "dallas,ds1339";
308                 reg = <0x68>;
309                 trickle-resistor-ohms = <250>;
310                 trickle-diode-disable;
311         };
312 };
313 
314 &i2c3 {
315         pinctrl-names = "default", "gpio";
316         pinctrl-0 = <&pinctrl_i2c3>;
317         pinctrl-1 = <&pinctrl_i2c3_gpio>;
318         scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
319         sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
320         clock-frequency = <400000>;
321         status = "okay";
322 
323         sgtl5000: sgtl5000@a {
324                 compatible = "fsl,sgtl5000";
325                 #sound-dai-cells = <0>;
326                 reg = <0x0a>;
327                 VDDA-supply = <&reg_2v5>;
328                 VDDIO-supply = <&reg_3v3>;
329                 clocks = <&mclk>;
330         };
331 
332         polytouch: edt-ft5x06@38 {
333                 compatible = "edt,edt-ft5x06";
334                 reg = <0x38>;
335                 pinctrl-names = "default";
336                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
337                 interrupt-parent = <&gpio6>;
338                 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
339                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
340                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
341                 wakeup-source;
342         };
343 
344         touchscreen: tsc2007@48 {
345                 compatible = "ti,tsc2007";
346                 reg = <0x48>;
347                 pinctrl-names = "default";
348                 pinctrl-0 = <&pinctrl_tsc2007>;
349                 interrupt-parent = <&gpio3>;
350                 interrupts = <26 0>;
351                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
352                 ti,x-plate-ohms = <660>;
353                 wakeup-source;
354         };
355 };
356 
357 &iomuxc {
358         pinctrl-names = "default";
359         pinctrl-0 = <&pinctrl_hog>;
360 
361         pinctrl_hog: hoggrp {
362                 fsl,pins = <
363                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
364                 >;
365         };
366 
367         pinctrl_audmux: audmuxgrp {
368                 fsl,pins = <
369                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
370                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
371                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
372                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
373                 >;
374         };
375 
376         pinctrl_disp0_1: disp0-1-grp {
377                 fsl,pins = <
378                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
379                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
380                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
381                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
382                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
383                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
384                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
385                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
386                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
387                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
388                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
389                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
390                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
391                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
392                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
393                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
394                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
395                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
396                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
397                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
398                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
399                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
400                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
401                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
402                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
403                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
404                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
405                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
406                 >;
407         };
408 
409         pinctrl_disp0_2: disp0-2-grp {
410                 fsl,pins = <
411                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
412                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
413                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
414                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
415                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
416                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
417                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
418                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
419                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
420                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
421                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
422                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
423                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
424                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
425                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
426                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
427                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
428                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
429                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
430                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
431                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
432                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
433                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
434                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
435                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
436                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
437                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
438                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
439                 >;
440         };
441 
442         pinctrl_ecspi1: ecspi1grp {
443                 fsl,pins = <
444                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
445                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
446                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
447                         MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
448                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
449                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
450                 >;
451         };
452 
453         pinctrl_edt_ft5x06: edt-ft5x06grp {
454                 fsl,pins = <
455                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
456                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
457                         MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
458                 >;
459         };
460 
461         pinctrl_enet: enetgrp {
462                 fsl,pins = <
463                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
464                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
465                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
466                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
467                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
468                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
469                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
470                 >;
471         };
472 
473         pinctrl_enet_mdio: enet-mdiogrp {
474                 fsl,pins = <
475                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
476                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
477                 >;
478         };
479 
480         pinctrl_etnphy_int: etnphy-intgrp {
481                 fsl,pins = <
482                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
483                 >;
484         };
485 
486         pinctrl_etnphy_power: etnphy-pwrgrp {
487                 fsl,pins = <
488                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
489                 >;
490         };
491 
492         pinctrl_etnphy_rst: etnphy-rstgrp {
493                 fsl,pins = <
494                         MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
495                 >;
496         };
497 
498         pinctrl_flexcan1: flexcan1grp {
499                 fsl,pins = <
500                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
501                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
502                 >;
503         };
504 
505         pinctrl_flexcan2: flexcan2grp {
506                 fsl,pins = <
507                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
508                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
509                 >;
510         };
511 
512         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
513                 fsl,pins = <
514                         MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
515                 >;
516         };
517 
518         pinctrl_gpmi_nand: gpminandgrp {
519                 fsl,pins = <
520                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
521                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
522                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
523                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
524                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
525                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
526                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
527                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
528                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
529                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
530                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
531                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
532                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
533                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
534                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
535                 >;
536         };
537 
538         pinctrl_i2c1: i2c1grp {
539                 fsl,pins = <
540                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
541                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
542                 >;
543         };
544 
545         pinctrl_i2c1_gpio: i2c1-gpiogrp {
546                 fsl,pins = <
547                         MX6QDL_PAD_EIM_D21__GPIO3_IO21          0x4001b8b1
548                         MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x4001b8b1
549                 >;
550         };
551 
552         pinctrl_i2c3: i2c3grp {
553                 fsl,pins = <
554                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
555                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
556                 >;
557         };
558 
559         pinctrl_i2c3_gpio: i2c3-gpiogrp {
560                 fsl,pins = <
561                         MX6QDL_PAD_GPIO_3__GPIO1_IO03           0x4001b8b1
562                         MX6QDL_PAD_GPIO_6__GPIO1_IO06           0x4001b8b1
563                 >;
564         };
565 
566         pinctrl_kpp: kppgrp {
567                 fsl,pins = <
568                         MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
569                         MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
570                         MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
571                         MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
572                         MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
573                         MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
574                         MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
575                         MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
576                 >;
577         };
578 
579         pinctrl_lcd0_pwr: lcd0-pwrgrp {
580                 fsl,pins = <
581                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
582                 >;
583         };
584 
585         pinctrl_lcd1_pwr: lcd-pwrgrp {
586                 fsl,pins = <
587                         MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
588                 >;
589         };
590 
591         pinctrl_pwm1: pwm1grp {
592                 fsl,pins = <
593                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
594                 >;
595         };
596 
597         pinctrl_pwm2: pwm2grp {
598                 fsl,pins = <
599                         MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
600                 >;
601         };
602 
603         pinctrl_tsc2007: tsc2007grp {
604                 fsl,pins = <
605                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
606                 >;
607         };
608 
609         pinctrl_uart1: uart1grp {
610                 fsl,pins = <
611                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
612                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
613                 >;
614         };
615 
616         pinctrl_uart1_rtscts: uart1_rtsctsgrp {
617                 fsl,pins = <
618                         MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
619                         MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
620                 >;
621         };
622 
623         pinctrl_uart2: uart2grp {
624                 fsl,pins = <
625                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
626                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
627                 >;
628         };
629 
630         pinctrl_uart2_rtscts: uart2_rtsctsgrp {
631                 fsl,pins = <
632                         MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
633                         MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
634                 >;
635         };
636 
637         pinctrl_uart3: uart3grp {
638                 fsl,pins = <
639                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
640                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
641                 >;
642         };
643 
644         pinctrl_uart3_rtscts: uart3_rtsctsgrp {
645                 fsl,pins = <
646                         MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
647                         MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
648                 >;
649         };
650 
651         pinctrl_usbh1_vbus: usbh1-vbusgrp {
652                 fsl,pins = <
653                         MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
654                 >;
655         };
656 
657         pinctrl_usbotg: usbotggrp {
658                 fsl,pins = <
659                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
660                 >;
661         };
662 
663         pinctrl_usbotg_vbus: usbotg-vbusgrp {
664                 fsl,pins = <
665                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
666                 >;
667         };
668 
669         pinctrl_usdhc1: usdhc1grp {
670                 fsl,pins = <
671                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
672                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
673                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
674                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
675                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
676                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
677                         MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
678                 >;
679         };
680 
681         pinctrl_usdhc2: usdhc2grp {
682                 fsl,pins = <
683                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
684                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
685                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
686                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
687                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
688                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
689                         MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
690                 >;
691         };
692 
693         pinctrl_user_led: user-ledgrp {
694                 fsl,pins = <
695                         MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
696                 >;
697         };
698 };
699 
700 &kpp {
701         pinctrl-names = "default";
702         pinctrl-0 = <&pinctrl_kpp>;
703         /* sample keymap */
704         /* row/col 0,1 are mapped to KPP row/col 6,7 */
705         linux,keymap = <
706                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
707                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
708                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
709                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
710                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
711                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
712                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
713                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
714                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
715                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
716                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
717         >;
718         status = "okay";
719 };
720 
721 &pwm1 {
722         pinctrl-names = "default";
723         pinctrl-0 = <&pinctrl_pwm1>;
724         status = "disabled";
725 };
726 
727 &pwm2 {
728         pinctrl-names = "default";
729         pinctrl-0 = <&pinctrl_pwm2>;
730         status = "okay";
731 };
732 
733 &ssi1 {
734         status = "okay";
735 };
736 
737 &uart1 {
738         pinctrl-names = "default";
739         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
740         uart-has-rtscts;
741         status = "okay";
742 };
743 
744 &uart2 {
745         pinctrl-names = "default";
746         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
747         uart-has-rtscts;
748         status = "okay";
749 };
750 
751 &uart3 {
752         pinctrl-names = "default";
753         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
754         uart-has-rtscts;
755         status = "okay";
756 };
757 
758 &usbh1 {
759         vbus-supply = <&reg_usbh1_vbus>;
760         dr_mode = "host";
761         disable-over-current;
762         status = "okay";
763 };
764 
765 &usbotg {
766         vbus-supply = <&reg_usbotg_vbus>;
767         pinctrl-names = "default";
768         pinctrl-0 = <&pinctrl_usbotg>;
769         dr_mode = "peripheral";
770         disable-over-current;
771         status = "okay";
772 };
773 
774 &usdhc1 {
775         pinctrl-names = "default";
776         pinctrl-0 = <&pinctrl_usdhc1>;
777         bus-width = <4>;
778         no-1-8-v;
779         cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
780         fsl,wp-controller;
781         status = "okay";
782 };
783 
784 &usdhc2 {
785         pinctrl-names = "default";
786         pinctrl-0 = <&pinctrl_usdhc2>;
787         bus-width = <4>;
788         no-1-8-v;
789         cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
790         fsl,wp-controller;
791         status = "okay";
792 };

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