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Linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6qp.dtsi

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  1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2 //
  3 // Copyright 2016 Freescale Semiconductor, Inc.
  4 
  5 #include "imx6q.dtsi"
  6 
  7 / {
  8         soc {
  9                 ocram2: sram@940000 {
 10                         compatible = "mmio-sram";
 11                         reg = <0x00940000 0x20000>;
 12                         ranges = <0 0x00940000 0x20000>;
 13                         #address-cells = <1>;
 14                         #size-cells = <1>;
 15                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
 16                 };
 17 
 18                 ocram3: sram@960000 {
 19                         compatible = "mmio-sram";
 20                         reg = <0x00960000 0x20000>;
 21                         ranges = <0 0x00960000 0x20000>;
 22                         #address-cells = <1>;
 23                         #size-cells = <1>;
 24                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
 25                 };
 26 
 27                 bus@2100000 {
 28                         pre1: pre@21c8000 {
 29                                 compatible = "fsl,imx6qp-pre";
 30                                 reg = <0x021c8000 0x1000>;
 31                                 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
 32                                 clocks = <&clks IMX6QDL_CLK_PRE0>;
 33                                 clock-names = "axi";
 34                                 fsl,iram = <&ocram2>;
 35                         };
 36 
 37                         pre2: pre@21c9000 {
 38                                 compatible = "fsl,imx6qp-pre";
 39                                 reg = <0x021c9000 0x1000>;
 40                                 interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
 41                                 clocks = <&clks IMX6QDL_CLK_PRE1>;
 42                                 clock-names = "axi";
 43                                 fsl,iram = <&ocram2>;
 44                         };
 45 
 46                         pre3: pre@21ca000 {
 47                                 compatible = "fsl,imx6qp-pre";
 48                                 reg = <0x021ca000 0x1000>;
 49                                 interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
 50                                 clocks = <&clks IMX6QDL_CLK_PRE2>;
 51                                 clock-names = "axi";
 52                                 fsl,iram = <&ocram3>;
 53                         };
 54 
 55                         pre4: pre@21cb000 {
 56                                 compatible = "fsl,imx6qp-pre";
 57                                 reg = <0x021cb000 0x1000>;
 58                                 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
 59                                 clocks = <&clks IMX6QDL_CLK_PRE3>;
 60                                 clock-names = "axi";
 61                                 fsl,iram = <&ocram3>;
 62                         };
 63 
 64                         prg1: prg@21cc000 {
 65                                 compatible = "fsl,imx6qp-prg";
 66                                 reg = <0x021cc000 0x1000>;
 67                                 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
 68                                          <&clks IMX6QDL_CLK_PRG0_AXI>;
 69                                 clock-names = "ipg", "axi";
 70                                 fsl,pres = <&pre1>, <&pre2>, <&pre3>;
 71                         };
 72 
 73                         prg2: prg@21cd000 {
 74                                 compatible = "fsl,imx6qp-prg";
 75                                 reg = <0x021cd000 0x1000>;
 76                                 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
 77                                          <&clks IMX6QDL_CLK_PRG1_AXI>;
 78                                 clock-names = "ipg", "axi";
 79                                 fsl,pres = <&pre4>, <&pre2>, <&pre3>;
 80                         };
 81                 };
 82         };
 83 };
 84 
 85 &fec {
 86         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
 87                      <0 119 IRQ_TYPE_LEVEL_HIGH>;
 88 };
 89 
 90 &gpc {
 91         compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
 92 };
 93 
 94 &ipu1 {
 95         compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
 96         fsl,prg = <&prg1>;
 97 };
 98 
 99 &ipu2 {
100         compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
101         fsl,prg = <&prg2>;
102 };
103 
104 &ldb {
105         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
106                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
107                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
108                  <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
109         clock-names = "di0_pll", "di1_pll",
110                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
111                       "di0", "di1";
112 };
113 
114 &mmdc0 {
115         compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
116 };
117 
118 &pcie {
119         compatible = "fsl,imx6qp-pcie";
120 };

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