1 // SPDX-License-Identifier: GPL-2.0 OR X11
2 /*
3 * Copyright (C) 2016 Amarula Solutions B.V.
4 * Copyright (C) 2016 Engicam S.r.l.
5 */
6
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include "imx6ul.dtsi"
10
11 / {
12 memory@80000000 {
13 device_type = "memory";
14 reg = <0x80000000 0x20000000>;
15 };
16
17 chosen {
18 stdout-path = &uart1;
19 };
20
21 backlight {
22 compatible = "pwm-backlight";
23 pwms = <&pwm8 0 100000 0>;
24 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
25 10 11 12 13 14 15 16 17 18 19
26 20 21 22 23 24 25 26 27 28 29
27 30 31 32 33 34 35 36 37 38 39
28 40 41 42 43 44 45 46 47 48 49
29 50 51 52 53 54 55 56 57 58 59
30 60 61 62 63 64 65 66 67 68 69
31 70 71 72 73 74 75 76 77 78 79
32 80 81 82 83 84 85 86 87 88 89
33 90 91 92 93 94 95 96 97 98 99
34 100>;
35 default-brightness-level = <100>;
36 };
37
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
40 regulator-name = "1P8V";
41 regulator-min-microvolt = <1800000>;
42 regulator-max-microvolt = <1800000>;
43 regulator-always-on;
44 regulator-boot-on;
45 };
46
47 reg_3p3v: regulator-3p3v {
48 compatible = "regulator-fixed";
49 regulator-name = "3P3V";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-always-on;
53 regulator-boot-on;
54 };
55
56 sound {
57 compatible = "simple-audio-card";
58 simple-audio-card,name = "imx6ul-isiot-sgtl5000";
59 simple-audio-card,format = "i2s";
60 simple-audio-card,bitclock-master = <&dailink_master>;
61 simple-audio-card,frame-master = <&dailink_master>;
62 simple-audio-card,widgets =
63 "Microphone", "Mic Jack",
64 "Line", "Line In",
65 "Line", "Line Out",
66 "Headphone", "Headphone Jack";
67 simple-audio-card,routing =
68 "MIC_IN", "Mic Jack",
69 "Mic Jack", "Mic Bias",
70 "Headphone Jack", "HP_OUT";
71
72 simple-audio-card,cpu {
73 sound-dai = <&sai2>;
74 };
75
76 dailink_master: simple-audio-card,codec {
77 sound-dai = <&sgtl5000>;
78 clocks = <&clks IMX6UL_CLK_SAI2>;
79 };
80 };
81 };
82
83 &fec1 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_enet1>;
86 phy-mode = "rmii";
87 phy-handle = <ðphy0>;
88 status = "okay";
89
90 mdio {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 ethphy0: ethernet-phy@0 {
95 compatible = "ethernet-phy-ieee802.3-c22";
96 reg = <0>;
97 };
98 };
99 };
100
101 &gpmi {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_gpmi_nand>;
104 nand-on-flash-bbt;
105 status = "disabled";
106 };
107
108 &i2c1 {
109 clock-frequency = <100000>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_i2c1>;
112 status = "okay";
113
114 sgtl5000: codec@a {
115 compatible = "fsl,sgtl5000";
116 reg = <0x0a>;
117 #sound-dai-cells = <0>;
118 clocks = <&clks IMX6UL_CLK_OSC>;
119 clock-names = "mclk";
120 VDDA-supply = <®_3p3v>;
121 VDDIO-supply = <®_3p3v>;
122 VDDD-supply = <®_1p8v>;
123 };
124
125 stmpe811: gpio-expander@44 {
126 compatible = "st,stmpe811";
127 reg = <0x44>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_stmpe>;
130 interrupt-parent = <&gpio1>;
131 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134
135 stmpe: touchscreen {
136 compatible = "st,stmpe-ts";
137 st,sample-time = <4>;
138 st,mod-12b = <1>;
139 st,ref-sel = <0>;
140 st,adc-freq = <1>;
141 st,ave-ctrl = <1>;
142 st,touch-det-delay = <2>;
143 st,settling = <2>;
144 st,fraction-z = <7>;
145 st,i-drive = <1>;
146 };
147 };
148 };
149
150 &i2c2 {
151 clock-frequency = <100000>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c2>;
154 status = "okay";
155 };
156
157 &lcdif {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_lcdif_dat
160 &pinctrl_lcdif_ctrl>;
161 display = <&display0>;
162 status = "okay";
163
164 display0: display0 {
165 bits-per-pixel = <16>;
166 bus-width = <18>;
167
168 display-timings {
169 native-mode = <&timing0>;
170 timing0: timing0 {
171 clock-frequency = <28000000>;
172 hactive = <800>;
173 vactive = <480>;
174 hfront-porch = <30>;
175 hback-porch = <30>;
176 hsync-len = <64>;
177 vback-porch = <5>;
178 vfront-porch = <5>;
179 vsync-len = <20>;
180 hsync-active = <0>;
181 vsync-active = <0>;
182 de-active = <1>;
183 pixelclk-active = <0>;
184 };
185 };
186 };
187 };
188
189 &pwm8 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_pwm8>;
192 status = "okay";
193 };
194
195 &sai2 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_sai2>;
198 status = "okay";
199 };
200
201 &uart1 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_uart1>;
204 status = "okay";
205 };
206
207 &usdhc1 {
208 pinctrl-names = "default", "state_100mhz", "state_200mhz";
209 pinctrl-0 = <&pinctrl_usdhc1>;
210 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
211 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
212 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
213 bus-width = <4>;
214 no-1-8-v;
215 status = "okay";
216 };
217
218 &usdhc2 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_usdhc2>;
221 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
222 bus-width = <8>;
223 no-1-8-v;
224 status = "disabled";
225 };
226
227 &iomuxc {
228 pinctrl_enet1: enet1grp {
229 fsl,pins = <
230 MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
231 MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
232 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
233 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
234 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
235 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
236 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
237 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
238 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
239 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
240 >;
241 };
242
243 pinctrl_gpmi_nand: gpminandgrp {
244 fsl,pins = <
245 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
246 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
247 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
248 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
249 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
250 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
251 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
252 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
253 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
254 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
255 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
256 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
257 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
258 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
259 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
260 >;
261 };
262
263 pinctrl_i2c1: i2c1grp {
264 fsl,pins = <
265 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
266 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
267 >;
268 };
269
270 pinctrl_i2c2: i2c2grp {
271 fsl,pins = <
272 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
273 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
274 >;
275 };
276
277 pinctrl_lcdif_ctrl: lcdifctrlgrp {
278 fsl,pins = <
279 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
280 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
281 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
282 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
283 >;
284 };
285
286 pinctrl_lcdif_dat: lcdifdatgrp {
287 fsl,pins = <
288 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
289 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
290 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
291 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
292 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
293 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
294 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
295 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
296 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
297 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
298 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
299 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
300 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
301 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
302 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
303 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
304 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
305 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
306 >;
307 };
308
309 pinctrl_pwm8: pwm8grp {
310 fsl,pins = <
311 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
312 >;
313 };
314
315 pinctrl_sai2: sai2grp {
316 fsl,pins = <
317 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
318 MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
319 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
320 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
321 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
322 >;
323 };
324
325 pinctrl_stmpe: stmpegrp {
326 fsl,pins = <
327 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
328 >;
329 };
330
331 pinctrl_uart1: uart1grp {
332 fsl,pins = <
333 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
334 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
335 >;
336 };
337
338 pinctrl_usdhc1: usdhc1grp {
339 fsl,pins = <
340 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
341 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
342 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
343 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
344 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
345 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
346 >;
347 };
348
349 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
350 fsl,pins = <
351 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
352 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
353 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
354 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
355 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
356 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
357 >;
358 };
359
360 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
361 fsl,pins = <
362 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
363 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
364 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
365 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
366 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
367 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
368 >;
369 };
370
371 pinctrl_usdhc2: usdhc2grp {
372 fsl,pins = <
373 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
374 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
375 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
376 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
377 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
378 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
379 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
380 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
381 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
382 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
383 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
384 >;
385 };
386 };
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