1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
10
11 / {
12 model = "PHYTEC phyCORE-i.MX6 UltraLite";
13 compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 /*
20 * Set the minimum memory size here and
21 * let the bootloader set the real size.
22 */
23 memory@80000000 {
24 device_type = "memory";
25 reg = <0x80000000 0x8000000>;
26 };
27
28 gpio_leds_som: leds {
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpioleds_som>;
31 compatible = "gpio-leds";
32
33 led-phycore-green {
34 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
35 linux,default-trigger = "heartbeat";
36 };
37 };
38 };
39
40 &fec1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_enet1>;
43 phy-mode = "rmii";
44 phy-handle = <ðphy1>;
45 status = "disabled";
46
47 mdio: mdio {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 ethphy1: ethernet-phy@1 {
52 reg = <1>;
53 interrupt-parent = <&gpio1>;
54 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
55 micrel,led-mode = <1>;
56 clocks = <&clks IMX6UL_CLK_ENET_REF>;
57 clock-names = "rmii-ref";
58 status = "disabled";
59 };
60 };
61 };
62
63 &gpmi {
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_gpmi_nand>;
66 nand-on-flash-bbt;
67 status = "disabled";
68 };
69
70 &i2c1 {
71 pinctrl-names = "default", "gpio";
72 pinctrl-0 = <&pinctrl_i2c1>;
73 pinctrl-1 = <&pinctrl_i2c1_gpio>;
74 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
75 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
76 clock-frequency = <100000>;
77 status = "okay";
78
79 eeprom@52 {
80 compatible = "catalyst,24c32", "atmel,24c32";
81 pagesize = <32>;
82 reg = <0x52>;
83 };
84 };
85
86 &snvs_poweroff {
87 status = "okay";
88 };
89
90 &uart1 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_uart1>;
93 status = "okay";
94 };
95
96 &usdhc2 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_usdhc2>;
99 bus-width = <8>;
100 no-1-8-v;
101 non-removable;
102 status = "disabled";
103 };
104
105 &wdog1 {
106 fsl,suspend-in-wait;
107 };
108
109 &iomuxc {
110 pinctrl_enet1: enet1grp {
111 fsl,pins = <
112 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
113 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010
114 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
115 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
116 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
117 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
118 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
119 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
120 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
121 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
122 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
123 >;
124 };
125
126 pinctrl_gpioleds_som: gpioledssomgrp {
127 fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0>;
128 };
129
130 pinctrl_gpmi_nand: gpminandgrp {
131 fsl,pins = <
132 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
133 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
134 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
135 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
136 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
137 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
138 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
139 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
140 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
141 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
142 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
143 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
144 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
145 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
146 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
147 >;
148 };
149
150 pinctrl_i2c1: i2cgrp {
151 fsl,pins = <
152 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
153 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
154 >;
155 };
156
157 pinctrl_i2c1_gpio: i2cgpiogrp {
158 fsl,pins = <
159 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
160 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
161 >;
162 };
163
164 pinctrl_uart1: uart1grp {
165 fsl,pins = <
166 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
167 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
168 >;
169 };
170
171 pinctrl_usdhc2: usdhc2grp {
172 fsl,pins = <
173 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
174 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
175 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
176 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
177 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
178 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
179 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
180 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
181 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
182 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
183 >;
184 };
185
186 };
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