1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7 / {
8 model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
9 compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
10
11 aliases {
12 rtc0 = &i2c_rtc;
13 rtc1 = &snvs_rtc;
14 };
15
16 reg_sound_1v8: regulator-1v8 {
17 compatible = "regulator-fixed";
18 regulator-name = "i2s-audio-1v8";
19 regulator-min-microvolt = <1800000>;
20 regulator-max-microvolt = <1800000>;
21 status = "disabled";
22 };
23
24 reg_sound_3v3: regulator-3v3 {
25 compatible = "regulator-fixed";
26 regulator-name = "i2s-audio-3v3";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 status = "disabled";
30 };
31
32 reg_can1_en: regulator-can1 {
33 compatible = "regulator-fixed";
34 pinctrl-names = "default";
35 pinctrl-0 = <&princtrl_flexcan1_en>;
36 regulator-name = "Can";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
40 enable-active-high;
41 status = "disabled";
42 };
43
44 reg_adc1_vref_3v3: regulator-vref-3v3 {
45 compatible = "regulator-fixed";
46 regulator-name = "vref-3v3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 };
50
51 sound: sound {
52 compatible = "simple-audio-card";
53 simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
54 simple-audio-card,format = "i2s";
55 simple-audio-card,bitclock-master = <&dailink_master>;
56 simple-audio-card,frame-master = <&dailink_master>;
57 simple-audio-card,widgets =
58 "Line", "Line In",
59 "Line", "Line Out",
60 "Speaker", "Speaker";
61 simple-audio-card,routing =
62 "Line Out", "LLOUT",
63 "Line Out", "RLOUT",
64 "Speaker", "SPOP",
65 "Speaker", "SPOM",
66 "LINE1L", "Line In",
67 "LINE1R", "Line In";
68 status = "disabled";
69
70 simple-audio-card,cpu {
71 sound-dai = <&sai2>;
72 };
73
74 dailink_master: simple-audio-card,codec {
75 sound-dai = <&tlv320>;
76 clocks = <&clks IMX6UL_CLK_SAI2>;
77 };
78 };
79
80 };
81
82 &adc1 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_adc1>;
85 vref-supply = <®_adc1_vref_3v3>;
86 status = "disabled";
87 };
88
89 &can1 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_flexcan1>;
92 xceiver-supply = <®_can1_en>;
93 status = "disabled";
94 };
95
96 &clks {
97 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
98 assigned-clock-rates = <786432000>;
99 };
100
101 &ecspi3 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ecspi3>;
104 cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
105 status = "disabled";
106 };
107
108 &fec2 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_enet2>;
111 phy-mode = "rmii";
112 phy-handle = <ðphy2>;
113 status = "disabled";
114 };
115
116 &i2c1 {
117 tlv320: codec@18 {
118 compatible = "ti,tlv320aic3007";
119 #sound-dai-cells = <0>;
120 reg = <0x18>;
121 AVDD-supply = <®_sound_3v3>;
122 IOVDD-supply = <®_sound_3v3>;
123 DRVDD-supply = <®_sound_3v3>;
124 DVDD-supply = <®_sound_1v8>;
125 status = "disabled";
126 };
127
128 i2c_rtc: rtc@68 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_rtc_int>;
131 compatible = "microcrystal,rv4162";
132 reg = <0x68>;
133 interrupt-parent = <&gpio5>;
134 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
135 status = "disabled";
136 };
137 };
138
139 &mdio {
140 ethphy2: ethernet-phy@2 {
141 reg = <2>;
142 micrel,led-mode = <1>;
143 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
144 clock-names = "rmii-ref";
145 status = "disabled";
146 };
147 };
148
149 &sai2 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_sai2>;
152 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
153 <&clks IMX6UL_CLK_SAI2>;
154 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
155 assigned-clock-rates = <0>, <19200000>;
156 fsl,sai-mclk-direction-output;
157 status = "disabled";
158 };
159
160 &uart5 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_uart5>;
163 uart-has-rtscts;
164 status = "disabled";
165 };
166
167 &usbotg1 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_usb_otg1_id>;
170 dr_mode = "otg";
171 status = "disabled";
172 };
173
174 &usbotg2 {
175 dr_mode = "host";
176 disable-over-current;
177 status = "disabled";
178 };
179
180 &usdhc1 {
181 pinctrl-names = "default", "state_100mhz", "state_200mhz";
182 pinctrl-0 = <&pinctrl_usdhc1>;
183 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
184 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
185 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
186 no-1-8-v;
187 keep-power-in-suspend;
188 wakeup-source;
189 disable-wp;
190 status = "disabled";
191 };
192
193 &iomuxc {
194 pinctrl_adc1: adc1grp {
195 fsl,pins = <
196 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
197 >;
198 };
199
200 pinctrl_ecspi3: ecspi3grp {
201 fsl,pins = <
202 MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
203 MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
204 MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
205 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
206 >;
207 };
208
209 pinctrl_enet2: enet2grp {
210 fsl,pins = <
211 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
212 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
213 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
214 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
215 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
216 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
217 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
218 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
219 >;
220 };
221
222 pinctrl_flexcan1: flexcan1grp {
223 fsl,pins = <
224 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
225 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
226 >;
227 };
228
229 princtrl_flexcan1_en: flexcan1engrp {
230 fsl,pins = <
231 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
232 >;
233 };
234
235 pinctrl_rtc_int: rtcintgrp {
236 fsl,pins = <
237 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
238 >;
239 };
240
241 pinctrl_sai2: sai2grp {
242 fsl,pins = <
243 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
244 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
245 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
246 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
247 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
248 >;
249 };
250
251 pinctrl_uart5: uart5grp {
252 fsl,pins = <
253 MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
254 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
255 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
256 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
257 >;
258 };
259
260 pinctrl_usb_otg1_id: usbotg1idgrp {
261 fsl,pins = <
262 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
263 >;
264 };
265
266 pinctrl_usdhc1: usdhc1grp {
267 fsl,pins = <
268 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
269 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
270 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
271 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
272 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
273 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
274 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
275 >;
276 };
277
278 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
279 fsl,pins = <
280 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
281 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
282 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
283 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
284 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
285 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
286 >;
287 };
288
289 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
290 fsl,pins = <
291 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
292 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
293 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
294 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
295 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
296 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
297 >;
298 };
299 };
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