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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6ull-dhcor-maveo-box.dts

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  1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2 /*
  3  * Copyright (C) 2023 DH electronics GmbH
  4  * Copyright (C) 2023 Marantec electronics GmbH
  5  *
  6  * DHCOM iMX6ULL variant:
  7  * DHCR-iMX6ULL-C080-R051-SPI-WBT-I-01LG
  8  * DHCOR PCB number: 578-200 or newer
  9  * maveo box PCB number: 525-200 or newer
 10  */
 11 
 12 /dts-v1/;
 13 
 14 #include "imx6ull-dhcor-som.dtsi"
 15 
 16 / {
 17         model = "DH electronics i.MX6ULL DHCOR on maveo box";
 18         compatible = "marantec,imx6ull-dhcor-maveo-box", "dh,imx6ull-dhcor-som",
 19                      "fsl,imx6ull";
 20 
 21         aliases {
 22                 mmc2 = &usdhc2;
 23                 spi0 = &ecspi4;
 24                 spi3 = &ecspi1;
 25         };
 26 
 27         chosen {
 28                 stdout-path = "serial0:115200n8";
 29         };
 30 
 31         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
 32                 compatible = "regulator-fixed";
 33                 regulator-max-microvolt = <5000000>;
 34                 regulator-min-microvolt = <5000000>;
 35                 regulator-name = "usb-otg1-vbus";
 36         };
 37 
 38         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
 39                 compatible = "regulator-fixed";
 40                 regulator-max-microvolt = <5000000>;
 41                 regulator-min-microvolt = <5000000>;
 42                 regulator-name = "usb-otg2-vbus";
 43         };
 44 
 45         /* WiFi pin WL_REG_ON is connected to GPIO 5.9 */
 46         usdhc1_pwrseq: usdhc1-pwrseq {
 47                 compatible = "mmc-pwrseq-simple";
 48                 reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 49         };
 50 };
 51 
 52 /* BT pin BT_REG_ON is connected to GPIO 1.18 */
 53 &bluetooth {
 54         shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
 55 };
 56 
 57 /* X10 connector */
 58 &ecspi4 {
 59         cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
 60         pinctrl-0 = <&pinctrl_ecspi4>;
 61         pinctrl-names = "default";
 62         status = "okay";
 63 
 64         spidev@0 {
 65                 compatible = "dh,dhcom-board";
 66                 reg = <0>;
 67                 spi-cpha;
 68                 spi-cpol;
 69                 spi-max-frequency = <54000000>;
 70         };
 71 };
 72 
 73 &gpio1 {
 74         gpio-line-names =
 75                 "", "", "", "",
 76                 "", "BUTTON-USER", "", "",
 77                 "BUTTON-RESET", "", "", "",
 78                 "", "", "", "",
 79                 "", "", "BT-REG-ON", "",
 80                 "", "", "", "",
 81                 "", "", "", "",
 82                 "", "", "", "";
 83 };
 84 
 85 &gpio2 {
 86         gpio-line-names =
 87                 "PSOC-GPIO-1", "", "", "X10-12",
 88                 "X10-10", "PSOC-GPIO-2", "PSOC-GPIO-3", "",
 89                 "X10-11", "X10-9", "", "",
 90                 "", "", "", "",
 91                 "", "", "", "",
 92                 "", "", "", "",
 93                 "", "", "", "",
 94                 "", "", "", "";
 95 };
 96 
 97 &gpio3 {
 98         gpio-line-names =
 99                 "DHCOR-HW0", "DHCOR-HW1", "", "",
100                 "", "", "", "",
101                 "", "", "", "",
102                 "", "", "", "",
103                 "", "", "", "",
104                 "", "", "", "",
105                 "", "", "", "",
106                 "", "", "", "";
107 };
108 
109 &gpio4 {
110         gpio-line-names =
111                 "", "", "", "",
112                 "", "", "", "",
113                 "", "", "", "",
114                 "", "", "", "",
115                 "", "MAVEO-BOX-HW0", "LED-G", "MAVEO-BOX-VAR1",
116                 "MAVEO-BOX-VAR0", "MAVEO-BOX-HW1", "MAVEO-BOX-HW2", "LED-B",
117                 "LED-R", "", "", "",
118                 "", "", "", "";
119 };
120 
121 &gpio5 {
122         gpio-line-names =
123                 "PSOC-SWD-IO", "PSOC-SWD-CLK", "PSOC-RESET", "ZIGBEE-PROG",
124                 "ZIGBEE-RESET", "", "PSOC-PWR-FAIL-OUT", "NFC-ENABLE",
125                 "NFC-IRQ", "WL-REG-ON", "DHCOR-BOOT-M0", "DHCOR-BOOT-M1",
126                 "", "", "", "",
127                 "", "", "", "",
128                 "", "", "", "",
129                 "", "", "", "",
130                 "", "", "", "";
131 };
132 
133 &i2c2 {
134         clock-frequency = <100000>;
135         pinctrl-0 = <&pinctrl_i2c2>;
136         pinctrl-1 = <&pinctrl_i2c2_gpio>;
137         pinctrl-names = "default", "gpio";
138         scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
139         sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
140         status = "okay";
141 };
142 
143 /* Console UART */
144 &uart1 {
145         pinctrl-0 = <&pinctrl_uart1>;
146         pinctrl-names = "default";
147         status = "okay";
148 };
149 
150 /* BT on LGA */
151 &uart2 {
152         pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt_gpio>;
153 };
154 
155 /* Zigbee UART */
156 &uart3 {
157         pinctrl-0 = <&pinctrl_uart3 &pinctrl_snvs_zigbee_gpio>;
158         pinctrl-names = "default";
159         status = "okay";
160 };
161 
162 &usbotg1 {
163         adp-disable;
164         disable-over-current; /* Overcurrent pin isn't connected */
165         dr_mode = "otg";
166         hnp-disable;
167         pinctrl-0 = <&pinctrl_usbotg1>;
168         pinctrl-names = "default";
169         srp-disable;
170         vbus-supply = <&reg_usb_otg1_vbus>;
171         status = "okay";
172 };
173 
174 &usbotg2 {
175         disable-over-current; /* Overcurrent pin isn't connected */
176         dr_mode = "host";
177         pinctrl-0 = <&pinctrl_usbotg2>;
178         pinctrl-names = "default";
179         tpl-support;
180         vbus-supply = <&reg_usb_otg2_vbus>;
181         status = "okay";
182 };
183 
184 &usbphy1 {
185         fsl,tx-d-cal = <106>;
186 };
187 
188 &usbphy2 {
189         fsl,tx-d-cal = <106>;
190 };
191 
192 /* WiFi on LGA */
193 &usdhc1 {
194         mmc-pwrseq = <&usdhc1_pwrseq>;
195         pinctrl-0 = <&pinctrl_usdhc1_wifi &pinctrl_snvs_wifi_gpio>;
196 };
197 
198 /* eMMC */
199 &usdhc2 {
200         bus-width = <8>;
201         no-1-8-v;
202         non-removable;
203         pinctrl-0 = <&pinctrl_usdhc2>;
204         pinctrl-names = "default";
205         vmmc-supply = <&vcc_3v3>;
206         vqmmc-supply = <&vcc_3v3>;
207         status = "okay";
208 };
209 
210 &iomuxc {
211         pinctrl-0 = <&pinctrl_hog_maveo_box>;
212         pinctrl-names = "default";
213 
214         pinctrl_hog_maveo_box: hog-maveo-box-grp {
215                 fsl,pins = <
216                         MX6UL_PAD_GPIO1_IO05__GPIO1_IO05        0x120b0    /* BUTTON_USER */
217                         MX6UL_PAD_GPIO1_IO08__GPIO1_IO08        0x120b0    /* BUTTON_RESET */
218                         MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18        0x400120b0 /* LED_G */
219                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23        0x400120b0 /* LED_B */
220                         MX6UL_PAD_CSI_DATA03__GPIO4_IO24        0x400120b0 /* LED_R */
221                         MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09    0x400120b0 /* X10_9 */
222                         MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0x400120b0 /* X10_10 */
223                         MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08    0x400120b0 /* X10_11 */
224                         MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03    0x400120b0 /* X10_12 */
225                         MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x400120b0 /* PSOC_GPIO_1 */
226                         MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05       0x400120b0 /* PSOC_GPIO_2 */
227                         MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06      0x400120b0 /* PSOC_GPIO_3 */
228                         MX6UL_PAD_CSI_MCLK__GPIO4_IO17          0x120b0    /* MAVEO_BOX_HW0 */
229                         MX6UL_PAD_CSI_DATA00__GPIO4_IO21        0x120b0    /* MAVEO_BOX_HW1 */
230                         MX6UL_PAD_CSI_DATA01__GPIO4_IO22        0x120b0    /* MAVEO_BOX_HW2 */
231                         MX6UL_PAD_CSI_HSYNC__GPIO4_IO20         0x120b0    /* MAVEO_BOX_VAR0 */
232                         MX6UL_PAD_CSI_VSYNC__GPIO4_IO19         0x120b0    /* MAVEO_BOX_VAR1 */
233                         MX6UL_PAD_LCD_CLK__GPIO3_IO00           0x120b0    /* DHCOR_HW0 */
234                         MX6UL_PAD_LCD_ENABLE__GPIO3_IO01        0x120b0    /* DHCOR_HW1 */
235                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x120b0
236                         MX6UL_PAD_LCD_DATA01__GPIO3_IO06        0x120b0
237                         MX6UL_PAD_LCD_DATA02__GPIO3_IO07        0x120b0
238                         MX6UL_PAD_LCD_DATA03__GPIO3_IO08        0x120b0
239                         MX6UL_PAD_LCD_DATA04__GPIO3_IO09        0x120b0
240                         MX6UL_PAD_LCD_DATA05__GPIO3_IO10        0x120b0
241                         MX6UL_PAD_LCD_DATA06__GPIO3_IO11        0x120b0
242                         MX6UL_PAD_LCD_DATA07__GPIO3_IO12        0x120b0
243                         MX6UL_PAD_LCD_DATA08__GPIO3_IO13        0x120b0
244                         MX6UL_PAD_LCD_DATA09__GPIO3_IO14        0x120b0
245                         MX6UL_PAD_LCD_DATA10__GPIO3_IO15        0x120b0
246                         MX6UL_PAD_LCD_DATA11__GPIO3_IO16        0x120b0
247                         MX6UL_PAD_LCD_DATA12__GPIO3_IO17        0x120b0
248                         MX6UL_PAD_LCD_DATA13__GPIO3_IO18        0x120b0
249                         MX6UL_PAD_LCD_DATA14__GPIO3_IO19        0x120b0
250                         MX6UL_PAD_LCD_DATA15__GPIO3_IO20        0x120b0
251                         MX6UL_PAD_LCD_DATA16__GPIO3_IO21        0x120b0
252                         MX6UL_PAD_LCD_DATA17__GPIO3_IO22        0x120b0
253                         MX6UL_PAD_LCD_DATA18__GPIO3_IO23        0x120b0
254                 >;
255         };
256 
257         pinctrl_bt_gpio: bt-gpio-grp {
258                 fsl,pins = <
259                         MX6UL_PAD_UART1_CTS_B__GPIO1_IO18       0x400120b0 /* BT_REG_ON */
260                 >;
261         };
262 
263         pinctrl_ecspi4: ecspi4-grp {
264                 fsl,pins = <
265                         MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO     0x100b1
266                         MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI      0x100b1
267                         MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK   0x100b1
268                         MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15       0x1b0b0 /* SS0 */
269                 >;
270         };
271 
272         pinctrl_i2c2: i2c2-grp {
273                 fsl,pins = <
274                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL       0x4001b8b0
275                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA       0x4001b8b0
276                 >;
277         };
278 
279         pinctrl_i2c2_gpio: i2c2-gpio-grp {
280                 fsl,pins = <
281                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x4001b8b0
282                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x4001b8b0
283                 >;
284         };
285 
286         pinctrl_uart1: uart1-grp {
287                 fsl,pins = <
288                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
289                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
290                 >;
291         };
292 
293         pinctrl_uart3: uart3-grp {
294                 fsl,pins = <
295                         MX6UL_PAD_NAND_READY_B__UART3_DCE_TX    0x1b0b1
296                         MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX      0x1b0b1
297                 >;
298         };
299 
300         pinctrl_usbotg1: usbotg1-grp {
301                 fsl,pins = <
302                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
303                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0x120b0 /* USB_OTG1_PWR */
304                 >;
305         };
306 
307         pinctrl_usbotg2: usbotg2-grp {
308                 fsl,pins = <
309                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x120b0 /* USB_OTG2_PWR */
310                 >;
311         };
312 
313         pinctrl_usdhc2: usdhc2-grp {
314                 fsl,pins = <
315                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x10069
316                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
317                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x17059
318                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x17059
319                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x17059
320                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x17059
321                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x17059
322                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x17059
323                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x17059
324                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x17059
325                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x17059 /* SD2 Reset */
326                 >;
327         };
328 };
329 
330 &iomuxc_snvs {
331         pinctrl-0 = <&pinctrl_snvs_hog_maveo_box>;
332         pinctrl-names = "default";
333 
334         pinctrl_snvs_hog_maveo_box: snvs-hog-maveo-box-grp {
335                 fsl,pins = <
336                         MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x400120b0 /* PSOC_SWD_IO */
337                         MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x400120b0 /* PSOC_SWD_CLK */
338                         MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02     0x400120b0 /* PSOC_RESET */
339                         MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06     0x400120b0 /* PSOC_PWR_FAIL_OUT */
340                         MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07     0x400120b0 /* NFC_ENABLE */
341                         MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08     0x400120b0 /* NFC_IRQ */
342                         MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10       0x120b0    /* DHCOR_BOOT_M0 */
343                         MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x120b0    /* DHCOR_BOOT_M1 */
344                 >;
345         };
346 
347         pinctrl_snvs_wifi_gpio: snvs-wifi-gpio-grp {
348                 fsl,pins = <
349                         MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09     0x400120b0 /* WL_REG_ON */
350                 >;
351         };
352 
353         pinctrl_snvs_zigbee_gpio: snvs-zigbee-gpio-grp {
354                 fsl,pins = <
355                         MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03     0x400120b0 /* ZIGBEE_PROG */
356                         MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04     0x400120b0 /* ZIGBEE_RESET */
357                 >;
358         };
359 };

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