1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2023 DH electronics GmbH
4 */
5
6 #include <dt-bindings/clock/imx6ul-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include <dt-bindings/regulator/dlg,da9063-regulator.h>
12 #include "imx6ull.dtsi"
13
14 / {
15 aliases {
16 /delete-property/ mmc0;
17 /delete-property/ mmc1;
18 };
19
20 memory@80000000 {
21 /* Appropriate memory size will be filled by U-Boot */
22 reg = <0x80000000 0>;
23 device_type = "memory";
24 };
25 };
26
27 &cpu0 {
28 /*
29 * Due to the design as a solderable SOM, there are no capacitors
30 * below the SoC, therefore higher voltages are required.
31 * Due to CPU lifetime consideration of the SoC manufacturer and
32 * the preferred area of operation in the industrial related
33 * environment, set the maximum frequency for each DHCOM i.MX6ULL
34 * to 792MHz, as with the industrial type.
35 */
36 clock-frequency = <792000000>;
37 operating-points = <
38 /* kHz uV */
39 792000 1250000 /* Voltage increased */
40 528000 1175000
41 396000 1025000
42 198000 950000
43 >;
44 fsl,soc-operating-points = <
45 /* KHz uV */
46 792000 1250000 /* Voltage increased */
47 528000 1175000
48 396000 1175000
49 198000 1175000
50 >;
51 };
52
53 &gpio1 {
54 pinctrl-0 = <&pinctrl_spi1_switch>;
55 pinctrl-names = "default";
56 /*
57 * Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the
58 * DHCOM SPI1 interface or accessing the SPI bootflash. Both using
59 * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses
60 * the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins
61 * PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for
62 * DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they
63 * are used for the bus interface to the SPI bootflash. The GPIOs are
64 * disconnected by a buffer which is also controlled via the pin
65 * SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a
66 * special case and is disabled by setting GPIO 1.9 to high.
67 */
68 spi1-switch-hog {
69 gpio-hog;
70 gpios = <9 0>;
71 output-high;
72 line-name = "spi1-switch";
73 };
74 };
75
76 &i2c1 {
77 clock-frequency = <100000>;
78 pinctrl-0 = <&pinctrl_i2c1>;
79 pinctrl-1 = <&pinctrl_i2c1_gpio>;
80 pinctrl-names = "default", "gpio";
81 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
82 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
83 status = "okay";
84
85 pmic@58 {
86 compatible = "dlg,da9061";
87 reg = <0x58>;
88
89 onkey {
90 compatible = "dlg,da9061-onkey", "dlg,da9062-onkey";
91 status = "disabled";
92 };
93
94 regulators {
95 vdd_soc_in_1v4: buck1 {
96 regulator-allowed-modes = <DA9063_BUCK_MODE_SLEEP>; /* PFM */
97 regulator-always-on;
98 regulator-boot-on;
99 regulator-initial-mode = <DA9063_BUCK_MODE_SLEEP>;
100 regulator-max-microvolt = <1400000>;
101 regulator-min-microvolt = <1400000>;
102 regulator-name = "vdd_soc_in_1v4";
103 };
104
105 vcc_3v3: buck2 {
106 regulator-allowed-modes = <DA9063_BUCK_MODE_SYNC>; /* PWM */
107 regulator-always-on;
108 regulator-boot-on;
109 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
110 regulator-max-microvolt = <3300000>;
111 regulator-min-microvolt = <3300000>;
112 regulator-name = "vcc_3v3";
113 };
114
115 /*
116 * The current DRR3 memory can be supplied with a
117 * voltage of either 1.35V or 1.5V. For reasons of
118 * backward compatibility to only 1.5V DDR3 memory,
119 * the voltage is set to 1.5V.
120 */
121 vcc_ddr_1v35: buck3 {
122 regulator-allowed-modes = <DA9063_BUCK_MODE_SYNC>; /* PWM */
123 regulator-always-on;
124 regulator-boot-on;
125 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
126 regulator-max-microvolt = <1500000>;
127 regulator-min-microvolt = <1500000>;
128 regulator-name = "vcc_ddr_1v35";
129 };
130
131 vcc_2v5: ldo1 {
132 regulator-always-on;
133 regulator-boot-on;
134 regulator-max-microvolt = <2500000>;
135 regulator-min-microvolt = <2500000>;
136 regulator-name = "vcc_2v5";
137 };
138
139 vdd_snvs_in_3v3: ldo2 {
140 regulator-always-on;
141 regulator-boot-on;
142 regulator-max-microvolt = <3300000>;
143 regulator-min-microvolt = <3300000>;
144 regulator-name = "vdd_snvs_in_3v3";
145 };
146
147 vcc_1v8: ldo3 {
148 regulator-always-on;
149 regulator-boot-on;
150 regulator-max-microvolt = <1800000>;
151 regulator-min-microvolt = <1800000>;
152 regulator-name = "vcc_1v8";
153 };
154
155 vcc_1v2: ldo4 {
156 regulator-always-on;
157 regulator-boot-on;
158 regulator-max-microvolt = <1200000>;
159 regulator-min-microvolt = <1200000>;
160 regulator-name = "vcc_1v2";
161 };
162 };
163
164 thermal {
165 compatible = "dlg,da9061-thermal", "dlg,da9062-thermal";
166 status = "disabled";
167 };
168
169 watchdog {
170 compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog";
171 status = "disabled";
172 };
173 };
174 };
175
176 &ocotp {
177 /* Don't get write access by default */
178 read-only;
179 };
180
181 ®_arm {
182 vin-supply = <&vdd_soc_in_1v4>;
183 };
184
185 ®_soc {
186 vin-supply = <&vdd_soc_in_1v4>;
187 };
188
189 /* BT on LGA (BT_REG_ON is connected to LGA pin E1) */
190 &uart2 {
191 pinctrl-0 = <&pinctrl_uart2>;
192 pinctrl-names = "default";
193 uart-has-rtscts;
194 status = "okay";
195
196 /*
197 * Actually, the maximum speed of the chip is 4MBdps, but there are
198 * limitations that prevent this speed. It hasn't yet been figured out
199 * what the reason for this is. Currently, the maximum speed of 3MBdps
200 * can be used without any problems. If the limitation can be overcome,
201 * the speed can be increased accordingly.
202 */
203 bluetooth: bluetooth {
204 compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */
205 max-speed = <3000000>;
206 vbat-supply = <&vcc_3v3>;
207 vddio-supply = <&vcc_3v3>;
208 };
209 };
210
211 /* WiFi on LGA (WL_REG_ON is connected to LGA pin E3) */
212 &usdhc1 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 bus-width = <4>;
216 no-1-8-v;
217 non-removable;
218 keep-power-in-suspend;
219 pinctrl-0 = <&pinctrl_usdhc1_wifi>;
220 pinctrl-names = "default";
221 wakeup-source;
222 status = "okay";
223
224 brcmf: wifi@1 {
225 compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */
226 reg = <1>;
227 };
228 };
229
230 &iomuxc {
231 pinctrl_i2c1: i2c1-grp {
232 fsl,pins = <
233 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
234 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
235 >;
236 };
237
238 pinctrl_i2c1_gpio: i2c1-gpio-grp {
239 fsl,pins = <
240 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
241 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
242 >;
243 };
244
245 pinctrl_spi1_switch: spi1-switch-grp {
246 fsl,pins = <
247 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x120b0 /* SPI_BOOT_FLASH_EN */
248 >;
249 };
250
251 pinctrl_uart2: uart2-grp {
252 fsl,pins = <
253 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
254 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
255 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
256 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
257 >;
258 };
259
260 pinctrl_usdhc1_wifi: usdhc1-wifi-grp {
261 fsl,pins = <
262 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1b0b0
263 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10010
264 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x1b0b0
265 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x1b0b0
266 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x1b0b0
267 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x1b0b0
268 >;
269 };
270 };
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