1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2024 Linumiz
4 * Author: Parthiban <parthiban@linumiz.com>
5 */
6
7 #include <dt-bindings/gpio/gpio.h>
8
9 / {
10 model = "Seeed NPi-iMX6ULL Dev Board";
11 compatible = "seeed,imx6ull-seeed-npi", "fsl,imx6ull";
12
13 reg_dcdc_3v3: regulator-dcdc-3v3 {
14 compatible = "regulator-fixed";
15 regulator-name = "DCDC_3V3";
16 regulator-min-microvolt = <3300000>;
17 regulator-max-microvolt = <3300000>;
18 regulator-always-on;
19 };
20
21 reg_dram_1v35: regulator-dram-1v35 {
22 compatible = "regulator-fixed";
23 regulator-name = "DRAM_1V35";
24 regulator-min-microvolt = <1350000>;
25 regulator-max-microvolt = <1350000>;
26 regulator-always-on;
27 vin-supply = <®_dcdc_3v3>;
28 };
29
30 reg_vdd_arm_soc_in: regulator-vdd-arm-soc-in {
31 compatible = "regulator-fixed";
32 regulator-name = "VDD_ARM_SOC_IN";
33 regulator-min-microvolt = <1200000>;
34 regulator-max-microvolt = <1200000>;
35 regulator-always-on;
36 vin-supply = <®_dcdc_3v3>;
37 };
38
39 reg_dcdc_1v8: regulator-dcdc-1v8 {
40 compatible = "regulator-fixed";
41 regulator-name = "DCDC_1V8";
42 regulator-min-microvolt = <1800000>;
43 regulator-max-microvolt = <1800000>;
44 regulator-always-on;
45 vin-supply = <®_dcdc_3v3>;
46 };
47
48 reg_sd1_vqmmc: regulator-sd1-vqmmc {
49 compatible = "regulator-fixed";
50 regulator-name = "NVCC_SD";
51 regulator-min-microvolt = <1800000>;
52 regulator-max-microvolt = <1800000>;
53 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_reg_vqmmc>;
56 regulator-always-on;
57 vin-supply = <®_dcdc_1v8>;
58 };
59 };
60
61 &gpmi {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_gpmi_nand>;
64 status = "disabled";
65 };
66
67 &usdhc1 {
68 vqmmc-supply = <®_sd1_vqmmc>;
69 };
70
71 &usdhc2 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_usdhc2>;
74 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
75 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
76 bus-width = <8>;
77 non-removable;
78 keep-power-in-suspend;
79 status = "disabled";
80 };
81
82 &iomuxc {
83 pinctrl_gpmi_nand: gpminandgrp {
84 fsl,pins = <
85 MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
86 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
87 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
88 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
89 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
90 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
91 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
92 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
93 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
94 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
95 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
96 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
97 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
98 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
99 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
100 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
101 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
102 >;
103 };
104
105 pinctrl_reg_vqmmc: usdhc1regvqmmcgrp {
106 fsl,pins = <
107 MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x17059
108 >;
109 };
110
111 pinctrl_usdhc2: usdhc2grp {
112 fsl,pins = <
113 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
114 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
115 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
116 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
117 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
118 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
119 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
120 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
121 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
122 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
123 >;
124 };
125
126 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
127 fsl,pins = <
128 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
129 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
130 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
131 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
132 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
133 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
134 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
135 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
136 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
137 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
138 >;
139 };
140
141 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
142 fsl,pins = <
143 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
144 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
145 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
146 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
147 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
148 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
149 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
150 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
151 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
152 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
153 >;
154 };
155 };
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