~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6ull-tqma6ull2.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
  2 /*
  3  * Copyright 2018-2022 TQ-Systems GmbH
  4  * Author: Markus Niebel <Markus.Niebel@tq-group.com>
  5  */
  6 
  7 #include "imx6ull.dtsi"
  8 #include "imx6ul-tqma6ul-common.dtsi"
  9 #include "imx6ul-tqma6ulx-common.dtsi"
 10 
 11 / {
 12         model = "TQ-Systems TQMa6ULL2 SoM";
 13         compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
 14 };
 15 
 16 &usdhc2 {
 17         fsl,tuning-step = <6>;
 18         /* Errata ERR010450 Workaround */
 19         max-frequency = <99000000>;
 20         assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
 21         assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
 22         assigned-clock-rates = <0>, <198000000>;
 23 };
 24 
 25 &iomuxc {
 26         pinctrl_usdhc2: usdhc2grp {
 27                 fsl,pins = <
 28                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x00017031
 29                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x00017039
 30                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x00017039
 31                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x00017039
 32                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x00017039
 33                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x00017039
 34                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x00017039
 35                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x00017039
 36                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x00017039
 37                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x00017039
 38                         /* rst */
 39                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
 40                 >;
 41         };
 42 
 43         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 44                 fsl,pins = <
 45                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x000170f1
 46                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x000170f1
 47                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x000170f1
 48                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x000170f1
 49                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x000170f1
 50                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x000170f1
 51                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x000170f1
 52                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x000170f1
 53                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x000170f1
 54                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x000170f1
 55                         /* rst */
 56                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
 57                 >;
 58         };
 59 
 60         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 61                 fsl,pins = <
 62                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x000170f1
 63                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x000170f1
 64                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x000170f1
 65                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x000170f1
 66                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x000170f1
 67                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x000170f1
 68                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x000170f1
 69                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x000170f1
 70                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x000170f1
 71                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x000170f1
 72                         /* rst */
 73                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
 74                 >;
 75         };
 76 };

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

sflogo.php