1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /*
3 * Copyright 2016-2022 Toradex
4 */
5
6 #include <dt-bindings/pwm/pwm.h>
7
8 / {
9 aliases {
10 rtc0 = &rtc;
11 rtc1 = &snvs_rtc;
12 };
13
14 backlight: backlight {
15 brightness-levels = <0 45 63 88 119 158 203 255>;
16 compatible = "pwm-backlight";
17 default-brightness-level = <4>;
18 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_bl_on>;
21 power-supply = <®_module_3v3>;
22 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
23 status = "disabled";
24 };
25
26 chosen {
27 stdout-path = "serial0:115200n8";
28 };
29
30 extcon_usbc_det: usbc-det {
31 compatible = "linux,extcon-usb-gpio";
32 id-gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_usbc_det>;
35 };
36
37 gpio-keys {
38 compatible = "gpio-keys";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpiokeys>;
41
42 key-wakeup {
43 debounce-interval = <10>;
44 gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
45 label = "Wake-Up";
46 linux,code = <KEY_WAKEUP>;
47 wakeup-source;
48 };
49 };
50
51 panel_dpi: panel-dpi {
52 backlight = <&backlight>;
53 compatible = "edt,et057090dhu";
54 power-supply = <®_3v3>;
55 status = "disabled";
56
57 port {
58 lcd_panel_in: endpoint {
59 remote-endpoint = <&lcdif_out>;
60 };
61 };
62 };
63
64 reg_3v3: regulator-3v3 {
65 compatible = "regulator-fixed";
66 regulator-always-on;
67 regulator-max-microvolt = <3300000>;
68 regulator-min-microvolt = <3300000>;
69 regulator-name = "3.3V";
70 };
71
72 reg_5v0: regulator-5v0 {
73 compatible = "regulator-fixed";
74 regulator-always-on;
75 regulator-max-microvolt = <5000000>;
76 regulator-min-microvolt = <5000000>;
77 regulator-name = "5V";
78 };
79
80 reg_module_3v3: regulator-module-3v3 {
81 compatible = "regulator-fixed";
82 regulator-always-on;
83 regulator-max-microvolt = <3300000>;
84 regulator-min-microvolt = <3300000>;
85 regulator-name = "+V3.3";
86 };
87
88 reg_module_3v3_avdd: regulator-module-3v3-avdd {
89 compatible = "regulator-fixed";
90 regulator-always-on;
91 regulator-max-microvolt = <3300000>;
92 regulator-min-microvolt = <3300000>;
93 regulator-name = "+V3.3_AVDD_AUDIO";
94 };
95
96 reg_module_3v3_eth: regulator-module-3v3-eth {
97 compatible = "regulator-fixed";
98 off-on-delay-us = <200000>;
99 regulator-name = "+V3.3_ETH";
100 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <3300000>;
102 regulator-boot-on;
103 startup-delay-us = <200000>;
104 vin-supply = <®_LDO1>;
105 };
106
107 reg_usbh_vbus: regulator-usbh-vbus {
108 compatible = "regulator-fixed";
109 gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_usbh_reg>;
112 regulator-max-microvolt = <5000000>;
113 regulator-min-microvolt = <5000000>;
114 regulator-name = "VCC_USB[1-4]";
115 vin-supply = <®_5v0>;
116 };
117
118 sound {
119 compatible = "simple-audio-card";
120 simple-audio-card,bitclock-master = <&dailink_master>;
121 simple-audio-card,format = "i2s";
122 simple-audio-card,frame-master = <&dailink_master>;
123 simple-audio-card,name = "imx7-sgtl5000";
124
125 simple-audio-card,cpu {
126 sound-dai = <&sai1>;
127 };
128
129 dailink_master: simple-audio-card,codec {
130 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
131 sound-dai = <&codec>;
132 };
133 };
134 };
135
136 /* Colibri AD0 to AD3 */
137 &adc1 {
138 vref-supply = <®_DCDC3>;
139 };
140
141 /* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */
142
143 &cpu0 {
144 cpu-supply = <®_DCDC2>;
145 };
146
147 /* Colibri SSP */
148 &ecspi3 {
149 cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
152 };
153
154 /* Colibri Fast Ethernet */
155 &fec1 {
156 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
157 assigned-clock-rates = <0>, <100000000>;
158 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
159 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
160 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
161 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
162 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
163 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
164 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
165 fsl,magic-packet;
166 phy-handle = <ðphy0>;
167 phy-mode = "rmii";
168 phy-supply = <®_module_3v3_eth>;
169 pinctrl-names = "default", "sleep";
170 pinctrl-0 = <&pinctrl_enet1>;
171 pinctrl-1 = <&pinctrl_enet1_sleep>;
172
173 mdio {
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 /* Micrel KSZ8041RNL */
178 ethphy0: ethernet-phy@0 {
179 compatible = "ethernet-phy-ieee802.3-c22";
180 max-speed = <100>;
181 micrel,led-mode = <0>;
182 reg = <0>;
183 };
184 };
185 };
186
187 &flexcan1 {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_flexcan1>;
190 };
191
192 &flexcan2 {
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_flexcan2>;
195 };
196
197 &gpio1 {
198 gpio-line-names = "SODIMM_43",
199 "SODIMM_45",
200 "SODIMM_135",
201 "SODIMM_22",
202 "",
203 "",
204 "SODIMM_37",
205 "SODIMM_29",
206 "SODIMM_59",
207 "SODIMM_28",
208 "SODIMM_30",
209 "SODIMM_67",
210 "",
211 "",
212 "SODIMM_188",
213 "SODIMM_178";
214 };
215
216 &gpio2 {
217 gpio-line-names = "SODIMM_111",
218 "SODIMM_113",
219 "SODIMM_115",
220 "SODIMM_117",
221 "SODIMM_119",
222 "SODIMM_121",
223 "SODIMM_123",
224 "SODIMM_125",
225 "SODIMM_91",
226 "SODIMM_89",
227 "SODIMM_105",
228 "SODIMM_152",
229 "SODIMM_150",
230 "SODIMM_95",
231 "SODIMM_126",
232 "SODIMM_107",
233 "SODIMM_114",
234 "SODIMM_116",
235 "SODIMM_118",
236 "SODIMM_120",
237 "SODIMM_122",
238 "SODIMM_124",
239 "SODIMM_127",
240 "SODIMM_130",
241 "SODIMM_132",
242 "SODIMM_134",
243 "SODIMM_133",
244 "SODIMM_104",
245 "SODIMM_106",
246 "SODIMM_110",
247 "SODIMM_112",
248 "SODIMM_128";
249 };
250
251 &gpio3 {
252 gpio-line-names = "SODIMM_56",
253 "SODIMM_44",
254 "SODIMM_68",
255 "SODIMM_82",
256 "SODIMM_93",
257 "SODIMM_76",
258 "SODIMM_70",
259 "SODIMM_60",
260 "SODIMM_58",
261 "SODIMM_78",
262 "SODIMM_72",
263 "SODIMM_80",
264 "SODIMM_46",
265 "SODIMM_62",
266 "SODIMM_48",
267 "SODIMM_74",
268 "SODIMM_50",
269 "SODIMM_52",
270 "SODIMM_54",
271 "SODIMM_66",
272 "SODIMM_64",
273 "SODIMM_57",
274 "SODIMM_61",
275 "SODIMM_136",
276 "SODIMM_138",
277 "SODIMM_140",
278 "SODIMM_142",
279 "SODIMM_144",
280 "SODIMM_146";
281 };
282
283 &gpio4 {
284 gpio-line-names = "SODIMM_35",
285 "SODIMM_33",
286 "SODIMM_38",
287 "SODIMM_36",
288 "SODIMM_21",
289 "SODIMM_19",
290 "SODIMM_131",
291 "SODIMM_129",
292 "SODIMM_90",
293 "SODIMM_92",
294 "SODIMM_88",
295 "SODIMM_86",
296 "SODIMM_81",
297 "SODIMM_94",
298 "SODIMM_96",
299 "SODIMM_75",
300 "SODIMM_101",
301 "SODIMM_103",
302 "SODIMM_79",
303 "SODIMM_97",
304 "SODIMM_67",
305 "SODIMM_59",
306 "SODIMM_85",
307 "SODIMM_65";
308 };
309
310 &gpio5 {
311 gpio-line-names = "SODIMM_69",
312 "SODIMM_71",
313 "SODIMM_73",
314 "SODIMM_47",
315 "SODIMM_190",
316 "SODIMM_192",
317 "SODIMM_49",
318 "SODIMM_51",
319 "SODIMM_53",
320 "",
321 "",
322 "SODIMM_98",
323 "SODIMM_184",
324 "SODIMM_186",
325 "SODIMM_23",
326 "SODIMM_31",
327 "SODIMM_100",
328 "SODIMM_102";
329 };
330
331 &gpio6 {
332 gpio-line-names = "",
333 "",
334 "",
335 "",
336 "",
337 "",
338 "",
339 "",
340 "",
341 "",
342 "",
343 "",
344 "SODIMM_169",
345 "",
346 "",
347 "",
348 "SODIMM_77",
349 "SODIMM_24",
350 "",
351 "SODIMM_25",
352 "SODIMM_27",
353 "SODIMM_32",
354 "SODIMM_34";
355 };
356
357 &gpio7 {
358 gpio-line-names = "",
359 "",
360 "SODIMM_63",
361 "SODIMM_55",
362 "",
363 "",
364 "",
365 "",
366 "SODIMM_196",
367 "SODIMM_194",
368 "",
369 "SODIMM_99",
370 "",
371 "",
372 "SODIMM_137";
373 };
374
375 /* NAND on such SKUs */
376 &gpmi {
377 fsl,use-minimum-ecc;
378 nand-ecc-mode = "hw";
379 nand-on-flash-bbt;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_gpmi_nand>;
382 };
383
384 /* On-module Power I2C */
385 &i2c1 {
386 clock-frequency = <100000>;
387 pinctrl-names = "default", "gpio";
388 pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
389 pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
390 scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
391 sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
392 status = "okay";
393
394 codec: sgtl5000@a {
395 #sound-dai-cells = <0>;
396 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
397 compatible = "fsl,sgtl5000";
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_sai1_mclk>;
400 reg = <0xa>;
401 VDDA-supply = <®_module_3v3_avdd>;
402 VDDD-supply = <®_DCDC3>;
403 VDDIO-supply = <®_module_3v3>;
404 };
405
406 ad7879_ts: touchscreen@2c {
407 adi,acquisition-time = /bits/ 8 <1>;
408 adi,averaging = /bits/ 8 <1>;
409 adi,conversion-interval = /bits/ 8 <255>;
410 adi,first-conversion-delay = /bits/ 8 <3>;
411 adi,median-filter-size = /bits/ 8 <2>;
412 adi,resistance-plate-x = <120>;
413 compatible = "adi,ad7879-1";
414 interrupt-parent = <&gpio1>;
415 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
416 reg = <0x2c>;
417 touchscreen-max-pressure = <4096>;
418 status = "disabled";
419 };
420
421 pmic@33 {
422 compatible = "ricoh,rn5t567";
423 reg = <0x33>;
424
425 regulators {
426 reg_DCDC1: DCDC1 {
427 regulator-always-on;
428 regulator-boot-on;
429 regulator-max-microvolt = <1100000>;
430 regulator-min-microvolt = <1000000>;
431 regulator-name = "+V1.0_SOC";
432 };
433
434 reg_DCDC2: DCDC2 {
435 regulator-always-on;
436 regulator-boot-on;
437 regulator-max-microvolt = <1100000>;
438 regulator-min-microvolt = <975000>;
439 regulator-name = "+V1.1_ARM";
440 };
441
442 reg_DCDC3: DCDC3 {
443 regulator-always-on;
444 regulator-boot-on;
445 regulator-max-microvolt = <1800000>;
446 regulator-min-microvolt = <1800000>;
447 regulator-name = "+V1.8";
448 };
449
450 reg_DCDC4: DCDC4 {
451 regulator-always-on;
452 regulator-boot-on;
453 regulator-max-microvolt = <1350000>;
454 regulator-min-microvolt = <1350000>;
455 regulator-name = "+V1.35_DRAM";
456 };
457
458 reg_LDO1: LDO1 {
459 regulator-boot-on;
460 regulator-max-microvolt = <3300000>;
461 regulator-min-microvolt = <3300000>;
462 regulator-name = "PWR_EN_+V3.3_ETH";
463 };
464
465 reg_LDO2: LDO2 {
466 regulator-always-on;
467 regulator-boot-on;
468 regulator-max-microvolt = <3300000>;
469 regulator-min-microvolt = <1800000>;
470 regulator-name = "+V1.8_SD";
471 };
472
473 reg_LDO3: LDO3 {
474 regulator-always-on;
475 regulator-boot-on;
476 regulator-max-microvolt = <3300000>;
477 regulator-min-microvolt = <3300000>;
478 regulator-name = "PWR_EN_+V3.3_LPSR";
479 };
480
481 reg_LDO4: LDO4 {
482 regulator-always-on;
483 regulator-boot-on;
484 regulator-max-microvolt = <1800000>;
485 regulator-min-microvolt = <1800000>;
486 regulator-name = "+V1.8_LPSR";
487 };
488
489 reg_LDO5: LDO5 {
490 regulator-always-on;
491 regulator-boot-on;
492 regulator-max-microvolt = <3300000>;
493 regulator-min-microvolt = <3300000>;
494 regulator-name = "PWR_EN_+V3.3";
495 };
496 };
497 };
498 };
499
500 /* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
501 &i2c4 {
502 clock-frequency = <100000>;
503 pinctrl-names = "default", "gpio";
504 pinctrl-0 = <&pinctrl_i2c4>;
505 pinctrl-1 = <&pinctrl_i2c4_recovery>;
506 scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
507 sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
508 status = "disabled";
509
510 /* Atmel maxtouch controller */
511 atmel_mxt_ts: touchscreen@4a {
512 compatible = "atmel,maxtouch";
513 interrupt-parent = <&gpio2>;
514 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_atmel_connector>;
517 reg = <0x4a>;
518 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
519 status = "disabled";
520 };
521
522 /* M41T0M6 real time clock on carrier board */
523 rtc: rtc@68 {
524 compatible = "st,m41t0";
525 reg = <0x68>;
526 status = "disabled";
527 };
528 };
529
530 &lcdif {
531 assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>;
532 assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_lcdif_dat
535 &pinctrl_lcdif_ctrl>;
536 status = "disabled";
537
538 port {
539 lcdif_out: endpoint {
540 remote-endpoint = <&lcd_panel_in>;
541 };
542 };
543 };
544
545 /* Colibri PWM<A> */
546 &pwm1 {
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_pwm1>;
549 };
550
551 /* Colibri PWM<B> */
552 &pwm2 {
553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_pwm2>;
555 };
556
557 /* Colibri PWM<C> */
558 &pwm3 {
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_pwm3>;
561 };
562
563 /* Colibri PWM<D> */
564 &pwm4 {
565 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_pwm4>;
567 };
568
569 ®_1p0d {
570 vin-supply = <®_DCDC3>; /* VDDA_1P8_IN */
571 };
572
573 &sai1 {
574 pinctrl-names = "default";
575 pinctrl-0 = <&pinctrl_sai1>;
576 status = "okay";
577 };
578
579 /* Colibri UART_A */
580 &uart1 {
581 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
582 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
583 fsl,dte-mode;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
586 uart-has-rtscts;
587 };
588
589 /* Colibri UART_B */
590 &uart2 {
591 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
592 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
593 fsl,dte-mode;
594 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_uart2>;
596 uart-has-rtscts;
597 };
598
599 /* Colibri UART_C */
600 &uart3 {
601 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
602 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
603 fsl,dte-mode;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_uart3>;
606 };
607
608 /* Colibri USBC */
609 &usbotg1 {
610 dr_mode = "otg";
611 extcon = <0>, <&extcon_usbc_det>;
612 };
613
614 /* Colibri MMC/SD */
615 &usdhc1 {
616 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
617 disable-wp;
618 no-1-8-v;
619 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
620 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
621 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;
622 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;
623 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>;
624 vmmc-supply = <®_3v3>;
625 vqmmc-supply = <®_LDO2>;
626 wakeup-source;
627 };
628
629 /* eMMC on 1GB (eMMC) SKUs */
630 &usdhc3 {
631 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
632 assigned-clock-rates = <400000000>;
633 bus-width = <8>;
634 fsl,tuning-step = <2>;
635 non-removable;
636 pinctrl-names = "default", "state_100mhz", "state_200mhz";
637 pinctrl-0 = <&pinctrl_usdhc3>;
638 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
639 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
640 sdhci-caps-mask = <0x80000000 0x0>;
641 vmmc-supply = <®_module_3v3>;
642 vqmmc-supply = <®_DCDC3>;
643 };
644
645 &iomuxc {
646 pinctrl-names = "default";
647 pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
648
649 /*
650 * Atmel MXT touchsceen + Capacitive Touch Adapter
651 * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3.
652 * Don't use them simultaneously.
653 */
654 pinctrl_atmel_adapter: atmeladaptergrp {
655 fsl,pins = <
656 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */
657 MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */
658 >;
659 };
660
661 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
662 pinctrl_atmel_connector: atmelconnectorgrp {
663 fsl,pins = <
664 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */
665 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */
666 >;
667 };
668
669 pinctrl_can_int: canintgrp {
670 fsl,pins = <
671 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
672 >;
673 };
674
675 pinctrl_ecspi3: ecspi3grp {
676 fsl,pins = <
677 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 /* SODIMM 90 */
678 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 /* SODIMM 92 */
679 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 /* SODIMM 88 */
680 >;
681 };
682
683 pinctrl_ecspi3_cs: ecspi3csgrp {
684 fsl,pins = <
685 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 /* SODIMM 86 */
686 >;
687 };
688
689 pinctrl_enet1: enet1grp {
690 fsl,pins = <
691 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
692 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
693 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
694 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
695 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
696 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
697 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
698 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
699 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
700 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
701 >;
702 };
703
704 pinctrl_enet1_sleep: enet1-sleepgrp {
705 fsl,pins = <
706 MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
707 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
708 MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
709 MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
710 MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
711 MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
712 MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
713 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
714 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
715 MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
716 >;
717 };
718
719 pinctrl_flexcan1: flexcan1grp {
720 fsl,pins = <
721 MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
722 MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
723 >;
724 };
725
726 pinctrl_flexcan2: flexcan2grp {
727 fsl,pins = <
728 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
729 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
730 >;
731 };
732
733 pinctrl_gpio1: gpio1grp {
734 fsl,pins = <
735 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
736 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
737 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
738 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
739 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
740 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
741 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
742 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
743 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
744 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
745 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
746 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
747 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
748 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
749 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
750 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
751 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
752 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
753 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
754 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
755 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
756 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
757 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
758 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
759 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
760 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
761 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
762 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
763 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
764 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
765 MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
766 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
767 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
768 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
769 MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
770 MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
771 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
772 MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
773 >;
774 };
775
776 pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */
777 fsl,pins = <
778 MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
779 MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
780 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
781 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
782 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
783 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
784 MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
785 MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
786 MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
787 MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
788 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
789 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
790 >;
791 };
792
793 pinctrl_gpio3: gpio3grp { /* LCD 18-23 */
794 fsl,pins = <
795 MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
796 MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
797 MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
798 MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
799 MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
800 MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
801 >;
802 };
803
804 pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */
805 fsl,pins = <
806 MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
807 MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
808 >;
809 };
810
811 pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */
812 fsl,pins = <
813 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
814 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
815 >;
816 };
817
818 pinctrl_gpio_bl_on: gpioblongrp {
819 fsl,pins = <
820 MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
821 >;
822 };
823
824 pinctrl_gpmi_nand: gpminandgrp {
825 fsl,pins = <
826 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
827 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
828 MX7D_PAD_SD3_CLK__NAND_CLE 0x71
829 MX7D_PAD_SD3_CMD__NAND_ALE 0x71
830 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
831 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
832 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
833 MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
834 MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
835 MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
836 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
837 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
838 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
839 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
840 >;
841 };
842
843 pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */
844 fsl,pins = <
845 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
846 >;
847 };
848
849 pinctrl_i2c4: i2c4grp {
850 fsl,pins = <
851 MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f /* SODIMM 196 */
852 MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f /* SODIMM 194 */
853 >;
854 };
855
856 pinctrl_i2c4_recovery: i2c4-recoverygrp {
857 fsl,pins = <
858 MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
859 MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
860 >;
861 };
862
863 pinctrl_lcdif_dat: lcdifdatgrp {
864 fsl,pins = <
865 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 /* SODIMM 76 */
866 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 /* SODIMM 70 */
867 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 /* SODIMM 60 */
868 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 /* SODIMM 58 */
869 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 /* SODIMM 78 */
870 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 /* SODIMM 72 */
871 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 /* SODIMM 80 */
872 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 /* SODIMM 46 */
873 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 /* SODIMM 62 */
874 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 /* SODIMM 48 */
875 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 /* SODIMM 74 */
876 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 /* SODIMM 50 */
877 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 /* SODIMM 52 */
878 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 /* SODIMM 54 */
879 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 /* SODIMM 66 */
880 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 /* SODIMM 64 */
881 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 /* SODIMM 57 */
882 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 /* SODIMM 61 */
883 >;
884 };
885
886 pinctrl_lcdif_dat_24: lcdifdat24grp {
887 fsl,pins = <
888 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 /* SODIMM 136 */
889 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 /* SODIMM 138 */
890 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 /* SODIMM 140 */
891 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 /* SODIMM 142 */
892 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 /* SODIMM 144 */
893 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 /* SODIMM 146 */
894 >;
895 };
896
897 pinctrl_lcdif_ctrl: lcdifctrlgrp {
898 fsl,pins = <
899 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 /* SODIMM 56 */
900 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 /* SODIMM 44 */
901 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 /* SODIMM 68 */
902 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */
903 >;
904 };
905
906 pinctrl_lvds_transceiver: lvdstxgrp {
907 fsl,pins = <
908 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
909 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
910 MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
911 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
912 >;
913 };
914
915 pinctrl_pwm1: pwm1grp {
916 fsl,pins = <
917 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 /* SODIMM 59 */
918 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 /* SODIMM 59 */
919 >;
920 };
921
922 pinctrl_pwm2: pwm2grp {
923 fsl,pins = <
924 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 /* SODIMM 28 */
925 >;
926 };
927
928 pinctrl_pwm3: pwm3grp {
929 fsl,pins = <
930 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 /* SODIMM 30 */
931 >;
932 };
933
934 pinctrl_pwm4: pwm4grp {
935 fsl,pins = <
936 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 /* SODIMM 67 */
937 MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 /* SODIMM 67 */
938 >;
939 };
940
941 pinctrl_uart1: uart1grp {
942 fsl,pins = <
943 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 /* SODIMM 25 */
944 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 /* SODIMM 27 */
945 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 /* SODIMM 35 */
946 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 /* SODIMM 33 */
947 >;
948 };
949
950 pinctrl_uart1_ctrl1: uart1ctrl1grp {
951 fsl,pins = <
952 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* SODIMM 23 / DTR */
953 MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* SODIMM 31 / DCD */
954 >;
955 };
956
957 pinctrl_uart2: uart2grp {
958 fsl,pins = <
959 MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 /* SODIMM 32 / CTS */
960 MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 /* SODIMM 34 / RTS */
961 MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 /* SODIMM 38 */
962 MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 /* SODIMM 36 */
963 >;
964 };
965 pinctrl_uart3: uart3grp {
966 fsl,pins = <
967 MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 /* SODIMM 21 */
968 MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 /* SODIMM 19 */
969 >;
970 };
971
972 pinctrl_usbc_det: usbcdetgrp {
973 fsl,pins = <
974 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 /* SODIMM 137 / USBC_DET */
975 >;
976 };
977
978 pinctrl_usbh_reg: usbhreggrp {
979 fsl,pins = <
980 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 / USBH_PEN */
981 >;
982 };
983
984 pinctrl_usdhc1: usdhc1grp {
985 fsl,pins = <
986 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 /* SODIMM 47 */
987 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 /* SODIMM 190 */
988 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 /* SODIMM 192 */
989 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 /* SODIMM 49 */
990 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 /* SODIMM 51 */
991 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 /* SODIMM 53 */
992 >;
993 };
994
995 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
996 fsl,pins = <
997 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
998 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
999 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
1000 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
1001 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
1002 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
1003 >;
1004 };
1005
1006 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1007 fsl,pins = <
1008 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
1009 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
1010 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
1011 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
1012 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
1013 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
1014 >;
1015 };
1016
1017 /* Avoid backfeeding with removed card power. */
1018 pinctrl_usdhc1_sleep: usdhc1-slpgrp {
1019 fsl,pins = <
1020 MX7D_PAD_SD1_CMD__SD1_CMD 0x10
1021 MX7D_PAD_SD1_CLK__SD1_CLK 0x10
1022 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10
1023 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10
1024 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10
1025 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10
1026 >;
1027 };
1028
1029 pinctrl_usdhc3: usdhc3grp {
1030 fsl,pins = <
1031 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
1032 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
1033 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
1034 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
1035 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
1036 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
1037 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
1038 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
1039 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
1040 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
1041 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
1042 >;
1043 };
1044
1045 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1046 fsl,pins = <
1047 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
1048 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
1049 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
1050 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
1051 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
1052 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
1053 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
1054 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
1055 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
1056 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
1057 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
1058 >;
1059 };
1060
1061 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1062 fsl,pins = <
1063 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
1064 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
1065 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
1066 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
1067 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
1068 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
1069 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
1070 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
1071 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
1072 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
1073 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
1074 >;
1075 };
1076
1077 pinctrl_sai1: sai1grp {
1078 fsl,pins = <
1079 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
1080 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
1081 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
1082 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
1083 >;
1084 };
1085
1086 pinctrl_sai1_mclk: sai1mclkgrp {
1087 fsl,pins = <
1088 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
1089 >;
1090 };
1091 };
1092
1093 &iomuxc_lpsr {
1094 pinctrl-names = "default";
1095 pinctrl-0 = <&pinctrl_gpio_lpsr>;
1096
1097 pinctrl_cd_usdhc1: cdusdhc1grp {
1098 fsl,pins = <
1099 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* SODIMM 43 / MMC_CD */
1100 >;
1101 };
1102
1103 pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp {
1104 fsl,pins = <
1105 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0
1106 >;
1107 };
1108
1109 pinctrl_gpio_lpsr: gpiolpsrgrp {
1110 fsl,pins = <
1111 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* SODIMM 135 */
1112 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* SODIMM 22 */
1113 >;
1114 };
1115
1116 pinctrl_gpiokeys: gpiokeysgrp {
1117 fsl,pins = <
1118 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 /* SODIMM 45 / WAKE_UP */
1119 >;
1120 };
1121
1122 pinctrl_i2c1: i2c1grp {
1123 fsl,pins = <
1124 MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
1125 MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
1126 >;
1127 };
1128
1129 pinctrl_i2c1_recovery: i2c1-recoverygrp {
1130 fsl,pins = <
1131 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
1132 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
1133 >;
1134 };
1135
1136 pinctrl_uart1_ctrl2: uart1ctrl2grp {
1137 fsl,pins = <
1138 MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* SODIMM 37 / RI */
1139 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* SODIMM 29 / DSR */
1140 >;
1141 };
1142 };
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