1 // SPDX-License-Identifier: GPL-2.0 OR X11
2 /*
3 * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB.
4 *
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8 */
9
10 / {
11 memory@80000000 {
12 device_type = "memory";
13 /* 512 MB - default configuration */
14 reg = <0x80000000 0x20000000>;
15 };
16 };
17
18 &cpu0 {
19 cpu-supply = <&sw1a_reg>;
20 };
21
22 &gpio2 {
23 /* Configured as pullup by QSPI pin group */
24 qspi-reset-hog {
25 gpio-hog;
26 gpios = <4 GPIO_ACTIVE_LOW>;
27 input;
28 line-name = "qspi-reset";
29 };
30 };
31
32 &i2c1 {
33 pinctrl-names = "default", "gpio";
34 pinctrl-0 = <&pinctrl_i2c1>;
35 pinctrl-1 = <&pinctrl_i2c1_recovery>;
36 scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
37 sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
38 clock-frequency = <100000>;
39 status = "okay";
40
41 pfuze3000: pmic@8 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_pmic1>;
44 compatible = "fsl,pfuze3000";
45 reg = <0x08>;
46
47 regulators {
48 sw1a_reg: sw1a {
49 regulator-min-microvolt = <700000>;
50 regulator-max-microvolt = <3300000>;
51 regulator-boot-on;
52 regulator-always-on;
53 regulator-ramp-delay = <6250>;
54 };
55
56 /* use sw1c_reg to align with pfuze100/pfuze200 */
57 sw1c_reg: sw1b {
58 regulator-min-microvolt = <700000>;
59 regulator-max-microvolt = <1475000>;
60 regulator-boot-on;
61 regulator-always-on;
62 regulator-ramp-delay = <6250>;
63 };
64
65 sw2_reg: sw2 {
66 regulator-min-microvolt = <1500000>;
67 regulator-max-microvolt = <1850000>;
68 regulator-boot-on;
69 regulator-always-on;
70 };
71
72 sw3a_reg: sw3 {
73 regulator-min-microvolt = <900000>;
74 regulator-max-microvolt = <1650000>;
75 regulator-boot-on;
76 regulator-always-on;
77 };
78
79 swbst_reg: swbst {
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5150000>;
82 };
83
84 snvs_reg: vsnvs {
85 regulator-min-microvolt = <1000000>;
86 regulator-max-microvolt = <3000000>;
87 regulator-boot-on;
88 regulator-always-on;
89 };
90
91 vref_reg: vrefddr {
92 regulator-boot-on;
93 regulator-always-on;
94 };
95
96 vgen1_reg: vldo1 {
97 regulator-min-microvolt = <1800000>;
98 regulator-max-microvolt = <3300000>;
99 regulator-always-on;
100 };
101
102 vgen2_reg: vldo2 {
103 regulator-min-microvolt = <800000>;
104 regulator-max-microvolt = <1550000>;
105 regulator-always-on;
106 };
107
108 vgen3_reg: vccsd {
109 regulator-min-microvolt = <2850000>;
110 regulator-max-microvolt = <3300000>;
111 regulator-always-on;
112 };
113
114 vgen4_reg: v33 {
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 regulator-always-on;
118 };
119
120 vgen5_reg: vldo3 {
121 regulator-min-microvolt = <1800000>;
122 regulator-max-microvolt = <3300000>;
123 regulator-always-on;
124 };
125
126 vgen6_reg: vldo4 {
127 regulator-min-microvolt = <1800000>;
128 regulator-max-microvolt = <3300000>;
129 regulator-always-on;
130 };
131 };
132 };
133
134 /* LM75A temperature sensor, TQMa7x 01xx */
135 lm75a: temperature-sensor@48 {
136 compatible = "national,lm75a";
137 reg = <0x48>;
138 };
139
140 /* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */
141 se97b: temperature-sensor@1e {
142 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
143 reg = <0x1e>;
144 };
145
146 /* ST M24C64 */
147 m24c64: eeprom@50 {
148 compatible = "atmel,24c64";
149 read-only;
150 reg = <0x50>;
151 pagesize = <32>;
152 vcc-supply = <&vgen4_reg>;
153 status = "okay";
154 };
155
156 at24c02: eeprom@56 {
157 compatible = "nxp,se97b", "atmel,24c02";
158 reg = <0x56>;
159 pagesize = <16>;
160 vcc-supply = <&vgen4_reg>;
161 status = "okay";
162 };
163
164 ds1339: rtc@68 {
165 compatible = "dallas,ds1339";
166 reg = <0x68>;
167 };
168 };
169
170 &iomuxc {
171 pinctrl_i2c1: i2c1grp {
172 fsl,pins =
173 <MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078>,
174 <MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078>;
175 };
176
177 pinctrl_i2c1_recovery: i2c1recoverygrp {
178 fsl,pins =
179 <MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x40000078>,
180 <MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x40000078>;
181 };
182
183 pinctrl_pmic1: pmic1grp {
184 fsl,pins =
185 <MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C>;
186 };
187
188 pinctrl_qspi: qspigrp {
189 fsl,pins =
190 <MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A>,
191 <MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A>,
192 <MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A>,
193 <MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A>,
194 <MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11>,
195 <MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54>,
196 <MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54>;
197 };
198
199 pinctrl_qspi_reset: qspi_resetgrp {
200 fsl,pins =
201 /* #QSPI_RESET */
202 <MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52>;
203 };
204
205 pinctrl_usdhc3: usdhc3grp {
206 fsl,pins =
207 <MX7D_PAD_SD3_CMD__SD3_CMD 0x59>,
208 <MX7D_PAD_SD3_CLK__SD3_CLK 0x56>,
209 <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59>,
210 <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59>,
211 <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59>,
212 <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59>,
213 <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59>,
214 <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59>,
215 <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59>,
216 <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59>,
217 <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19>;
218 };
219
220 pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp {
221 fsl,pins =
222 <MX7D_PAD_SD3_CMD__SD3_CMD 0x5a>,
223 <MX7D_PAD_SD3_CLK__SD3_CLK 0x51>,
224 <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a>,
225 <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a>,
226 <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a>,
227 <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a>,
228 <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a>,
229 <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a>,
230 <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a>,
231 <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a>,
232 <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a>;
233 };
234
235 pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp {
236 fsl,pins =
237 <MX7D_PAD_SD3_CMD__SD3_CMD 0x5b>,
238 <MX7D_PAD_SD3_CLK__SD3_CLK 0x51>,
239 <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b>,
240 <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b>,
241 <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b>,
242 <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b>,
243 <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b>,
244 <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b>,
245 <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b>,
246 <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b>,
247 <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b>;
248 };
249 };
250
251 &iomuxc_lpsr {
252 pinctrl_wdog1: wdog1grp {
253 fsl,pins =
254 <MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>;
255 };
256 };
257
258 &qspi {
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
261 status = "okay";
262
263 flash0: flash@0 {
264 compatible = "jedec,spi-nor";
265 reg = <0>;
266 spi-max-frequency = <29000000>;
267 spi-rx-bus-width = <4>;
268 spi-tx-bus-width = <4>;
269 };
270 };
271
272 &usdhc3 {
273 pinctrl-names = "default", "state_100mhz", "state_200mhz";
274 pinctrl-0 = <&pinctrl_usdhc3>;
275 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
276 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
277 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
278 assigned-clock-rates = <400000000>;
279 bus-width = <8>;
280 non-removable;
281 no-sd;
282 no-sdio;
283 vmmc-supply = <&vgen4_reg>;
284 vqmmc-supply = <&sw2_reg>;
285 status = "okay";
286 };
287
288 &wdog1 {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_wdog1>;
291 /*
292 * Errata e10574:
293 * WDOG reset needs to run with WDOG_RESET_B signal enabled.
294 * X1-51 (WDOG1#) signal needs carrier board handling to reset
295 * TQMa7 on X1-22 (RESET_IN#).
296 */
297 fsl,ext-reset-output;
298 status = "okay";
299 };
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