1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2016 NXP Semiconductors.
4 * Author: Fabio Estevam <fabio.estevam@nxp.com>
5 */
6
7 /dts-v1/;
8
9 #include <dt-bindings/input/input.h>
10 #include "imx7s.dtsi"
11
12 / {
13 model = "Element14 Warp i.MX7 Board";
14 compatible = "element14,imx7s-warp", "fsl,imx7s";
15
16 memory@80000000 {
17 device_type = "memory";
18 reg = <0x80000000 0x20000000>;
19 };
20
21 gpio-keys {
22 compatible = "gpio-keys";
23 pinctrl-0 = <&pinctrl_gpio>;
24 autorepeat;
25
26 back {
27 label = "Back";
28 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
29 linux,code = <KEY_BACK>;
30 wakeup-source;
31 };
32 };
33
34 reg_brcm: regulator-brcm {
35 compatible = "regulator-fixed";
36 enable-active-high;
37 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_brcm_reg>;
40 regulator-name = "brcm_reg";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 startup-delay-us = <200000>;
44 };
45
46 reg_bt: regulator-bt {
47 compatible = "regulator-fixed";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_bt_reg>;
50 enable-active-high;
51 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
52 regulator-name = "bt_reg";
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 regulator-always-on;
56 };
57
58 reg_peri_3p15v: regulator-peri-3p15v {
59 compatible = "regulator-fixed";
60 regulator-name = "peri_3p15v_reg";
61 regulator-min-microvolt = <3150000>;
62 regulator-max-microvolt = <3150000>;
63 regulator-always-on;
64 };
65
66 sound {
67 compatible = "simple-audio-card";
68 simple-audio-card,name = "imx7-sgtl5000";
69 simple-audio-card,format = "i2s";
70 simple-audio-card,bitclock-master = <&dailink_master>;
71 simple-audio-card,frame-master = <&dailink_master>;
72 simple-audio-card,cpu {
73 sound-dai = <&sai1>;
74 };
75
76 dailink_master: simple-audio-card,codec {
77 sound-dai = <&codec>;
78 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
79 };
80 };
81 };
82
83 &clks {
84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
86 };
87
88 &csi {
89 status = "okay";
90 };
91
92 &i2c1 {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_i2c1>;
95 status = "okay";
96
97 pmic: pmic@8 {
98 compatible = "fsl,pfuze3000";
99 reg = <0x08>;
100
101 regulators {
102 sw1a_reg: sw1a {
103 regulator-min-microvolt = <700000>;
104 regulator-max-microvolt = <1475000>;
105 regulator-boot-on;
106 regulator-always-on;
107 regulator-ramp-delay = <6250>;
108 };
109
110 /* use sw1c_reg to align with pfuze100/pfuze200 */
111 sw1c_reg: sw1b {
112 regulator-min-microvolt = <700000>;
113 regulator-max-microvolt = <1475000>;
114 regulator-boot-on;
115 regulator-always-on;
116 regulator-ramp-delay = <6250>;
117 };
118
119 sw2_reg: sw2 {
120 regulator-min-microvolt = <1500000>;
121 regulator-max-microvolt = <1850000>;
122 regulator-boot-on;
123 regulator-always-on;
124 };
125
126 sw3a_reg: sw3 {
127 regulator-min-microvolt = <900000>;
128 regulator-max-microvolt = <1650000>;
129 regulator-boot-on;
130 regulator-always-on;
131 };
132
133 swbst_reg: swbst {
134 regulator-min-microvolt = <5000000>;
135 regulator-max-microvolt = <5150000>;
136 regulator-boot-on;
137 regulator-always-on;
138 };
139
140 snvs_reg: vsnvs {
141 regulator-min-microvolt = <1000000>;
142 regulator-max-microvolt = <3000000>;
143 regulator-boot-on;
144 regulator-always-on;
145 };
146
147 vref_reg: vrefddr {
148 regulator-boot-on;
149 regulator-always-on;
150 };
151
152 vgen1_reg: vldo1 {
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <3300000>;
155 regulator-always-on;
156 };
157
158 vgen2_reg: vldo2 {
159 regulator-min-microvolt = <800000>;
160 regulator-max-microvolt = <1550000>;
161 };
162
163 vgen3_reg: vccsd {
164 regulator-min-microvolt = <2850000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
167 };
168
169 vgen4_reg: v33 {
170 regulator-min-microvolt = <2850000>;
171 regulator-max-microvolt = <3300000>;
172 regulator-always-on;
173 };
174
175 vgen5_reg: vldo3 {
176 regulator-min-microvolt = <1800000>;
177 regulator-max-microvolt = <3300000>;
178 regulator-always-on;
179 };
180
181 vgen6_reg: vldo4 {
182 regulator-min-microvolt = <1800000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-always-on;
185 };
186 };
187 };
188 };
189
190 &i2c2 {
191 clock-frequency = <100000>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_i2c2>;
194 status = "okay";
195
196 ov2680: camera@36 {
197 compatible = "ovti,ov2680";
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_ov2680>;
200 reg = <0x36>;
201 clocks = <&osc>;
202 clock-names = "xvclk";
203 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
204 DOVDD-supply = <&sw2_reg>;
205 DVDD-supply = <&sw2_reg>;
206 AVDD-supply = <®_peri_3p15v>;
207
208 port {
209 ov2680_to_mipi: endpoint {
210 remote-endpoint = <&mipi_from_sensor>;
211 clock-lanes = <0>;
212 data-lanes = <1>;
213 link-frequencies = /bits/ 64 <330000000>;
214 };
215 };
216 };
217 };
218
219 &i2c3 {
220 clock-frequency = <100000>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c3>;
223 status = "okay";
224 };
225
226 &i2c4 {
227 clock-frequency = <100000>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_i2c4>;
230 status = "okay";
231
232 codec: sgtl5000@a {
233 #sound-dai-cells = <0>;
234 reg = <0x0a>;
235 compatible = "fsl,sgtl5000";
236 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_sai1_mclk>;
239 VDDA-supply = <&vgen4_reg>;
240 VDDIO-supply = <&vgen4_reg>;
241 VDDD-supply = <&vgen2_reg>;
242 };
243
244 mpl3115@60 {
245 compatible = "fsl,mpl3115";
246 reg = <0x60>;
247 };
248 };
249
250 &mipi_csi {
251 clock-frequency = <166000000>;
252 status = "okay";
253
254 ports {
255 port@0 {
256 reg = <0>;
257
258 mipi_from_sensor: endpoint {
259 remote-endpoint = <&ov2680_to_mipi>;
260 data-lanes = <1>;
261 };
262 };
263 };
264 };
265
266 &sai1 {
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_sai1>;
269 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
270 <&clks IMX7D_SAI1_ROOT_CLK>;
271 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
272 assigned-clock-rates = <0>, <36864000>;
273 status = "okay";
274 };
275
276 &uart1 {
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_uart1>;
279 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
280 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
281 status = "okay";
282 };
283
284 &uart3 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_uart3>;
287 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
288 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
289 uart-has-rtscts;
290 status = "okay";
291 };
292
293 &uart6 {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_uart6>;
296 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
297 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
298 fsl,dte-mode;
299 status = "okay";
300 };
301
302 &usbotg1 {
303 dr_mode = "peripheral";
304 status = "okay";
305 };
306
307 &usdhc1 {
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_usdhc1>;
310 bus-width = <4>;
311 keep-power-in-suspend;
312 no-1-8-v;
313 non-removable;
314 vmmc-supply = <®_brcm>;
315 status = "okay";
316 };
317
318 &usdhc3 {
319 pinctrl-names = "default", "state_100mhz", "state_200mhz";
320 pinctrl-0 = <&pinctrl_usdhc3>;
321 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
322 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
323 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
324 assigned-clock-rates = <400000000>;
325 bus-width = <8>;
326 no-1-8-v;
327 fsl,tuning-step = <2>;
328 non-removable;
329 status = "okay";
330 };
331
332 &video_mux {
333 status = "okay";
334 };
335
336 &wdog1 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_wdog>;
339 fsl,ext-reset-output;
340 status = "okay";
341 };
342
343 &iomuxc {
344 pinctrl_brcm_reg: brcmreggrp {
345 fsl,pins = <
346 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
347 >;
348 };
349
350 pinctrl_bt_reg: btreggrp {
351 fsl,pins = <
352 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
353 >;
354 };
355
356 pinctrl_gpio: gpiogrp {
357 fsl,pins = <
358 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
359 >;
360 };
361
362 pinctrl_i2c1: i2c1grp {
363 fsl,pins = <
364 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
365 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
366 >;
367 };
368
369 pinctrl_i2c2: i2c2grp {
370 fsl,pins = <
371 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
372 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
373 >;
374 };
375
376 pinctrl_i2c3: i2c3grp {
377 fsl,pins = <
378 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
379 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
380 >;
381 };
382
383 pinctrl_i2c4: i2c4grp {
384 fsl,pins = <
385 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
386 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
387 >;
388 };
389
390 pinctrl_ov2680: ov2660grp {
391 fsl,pins = <
392 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
393 >;
394 };
395
396 pinctrl_sai1: sai1grp {
397 fsl,pins = <
398 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
399 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
400 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
401 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
402 >;
403 };
404
405 pinctrl_sai1_mclk: sai1mclkgrp {
406 fsl,pins = <
407 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
408 >;
409 };
410
411 pinctrl_uart1: uart1grp {
412 fsl,pins = <
413 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
414 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
415 >;
416 };
417
418 pinctrl_uart3: uart3grp {
419 fsl,pins = <
420 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
421 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
422 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
423 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
424 >;
425 };
426
427 pinctrl_uart6: uart6grp {
428 fsl,pins = <
429 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
430 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
431 >;
432 };
433
434 pinctrl_usdhc1: usdhc1grp {
435 fsl,pins = <
436 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
437 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
438 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
439 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
440 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
441 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
442 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
443 >;
444 };
445
446 pinctrl_usdhc3: usdhc3grp {
447 fsl,pins = <
448 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
449 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
450 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
451 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
452 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
453 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
454 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
455 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
456 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
457 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
458 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
459 >;
460 };
461
462 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
463 fsl,pins = <
464 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
465 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
466 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
467 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
468 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
469 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
470 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
471 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
472 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
473 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
474 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
475 >;
476 };
477
478 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
479 fsl,pins = <
480 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
481 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
482 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
483 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
484 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
485 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
486 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
487 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
488 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
489 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
490 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
491 >;
492 };
493 };
494
495 &iomuxc_lpsr {
496 pinctrl_wdog: wdoggrp {
497 fsl,pins = <
498 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
499 >;
500 };
501 };
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