1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3 /*
4 * Copyright (C) 2018 Zodiac Inflight Innovations
5 */
6
7 /dts-v1/;
8 #include "vf610.dtsi"
9
10 / {
11 model = "ZII VF610 CFU1 Board";
12 compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610";
13
14 chosen {
15 stdout-path = &uart0;
16 };
17
18 memory@80000000 {
19 device_type = "memory";
20 reg = <0x80000000 0x20000000>;
21 };
22
23 gpio-leds {
24 compatible = "gpio-leds";
25 pinctrl-0 = <&pinctrl_leds_debug>;
26 pinctrl-names = "default";
27
28 led-debug {
29 label = "zii:green:debug1";
30 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
31 linux,default-trigger = "heartbeat";
32 };
33
34 led-fail {
35 label = "zii:red:fail";
36 gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
37 default-state = "off";
38 };
39
40 led-status {
41 label = "zii:green:status";
42 gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
43 default-state = "off";
44 };
45
46 led-debug-a {
47 label = "zii:green:debug_a";
48 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
49 default-state = "off";
50 };
51
52 led-debug-b {
53 label = "zii:green:debug_b";
54 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
55 default-state = "off";
56 };
57 };
58
59 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
60 compatible = "regulator-fixed";
61 regulator-name = "vcc_3v3_mcu";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 };
65
66 sff: sfp {
67 compatible = "sff,sff";
68 pinctrl-0 = <&pinctrl_optical>;
69 pinctrl-names = "default";
70 i2c-bus = <&i2c0>;
71 los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
72 tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
73 };
74
75 supply-voltage-monitor {
76 compatible = "iio-hwmon";
77 io-channels = <&adc0 8>, /* 28VDC_IN */
78 <&adc0 9>, /* +3.3V */
79 <&adc1 8>, /* VCC_1V5 */
80 <&adc1 9>; /* VCC_1V2 */
81 };
82 };
83
84 &adc0 {
85 vref-supply = <®_vcc_3v3_mcu>;
86 status = "okay";
87 };
88
89 &adc1 {
90 vref-supply = <®_vcc_3v3_mcu>;
91 status = "okay";
92 };
93
94 &dspi1 {
95 bus-num = <1>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_dspi1>;
98 /*
99 * Some CFU1s come with SPI-NOR chip DNPed, so we leave this
100 * node disabled by default and rely on bootloader to enable
101 * it when appropriate.
102 */
103 status = "disabled";
104
105 flash@0 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "m25p128", "jedec,spi-nor";
109 reg = <0>;
110 spi-max-frequency = <50000000>;
111
112 partition@0 {
113 label = "m25p128-0";
114 reg = <0x0 0x01000000>;
115 };
116 };
117 };
118
119 &edma0 {
120 status = "okay";
121 };
122
123 &edma1 {
124 status = "okay";
125 };
126
127 &esdhc0 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_esdhc0>;
130 bus-width = <8>;
131 non-removable;
132 no-1-8-v;
133 keep-power-in-suspend;
134 no-sdio;
135 no-sd;
136 status = "okay";
137 };
138
139 &esdhc1 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_esdhc1>;
142 bus-width = <4>;
143 no-sdio;
144 status = "okay";
145 };
146
147 &fec1 {
148 phy-mode = "rmii";
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_fec1>;
151 status = "okay";
152
153 fixed-link {
154 speed = <100>;
155 full-duplex;
156 };
157
158 mdio1: mdio {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 clock-frequency = <12500000>;
162 suppress-preamble;
163 status = "okay";
164
165 switch0: ethernet-switch@0 {
166 compatible = "marvell,mv88e6085";
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_switch>;
169 reg = <0>;
170 eeprom-length = <512>;
171 interrupt-parent = <&gpio3>;
172 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
173 interrupt-controller;
174 #interrupt-cells = <2>;
175
176 ethernet-ports {
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 ethernet-port@0 {
181 reg = <0>;
182 label = "eth_cu_1000_1";
183 };
184
185 ethernet-port@1 {
186 reg = <1>;
187 label = "eth_cu_1000_2";
188 };
189
190 ethernet-port@2 {
191 reg = <2>;
192 label = "eth_cu_1000_3";
193 };
194
195 ethernet-port@5 {
196 reg = <5>;
197 label = "eth_fc_1000_1";
198 phy-mode = "1000base-x";
199 managed = "in-band-status";
200 sfp = <&sff>;
201 };
202
203 ethernet-port@6 {
204 reg = <6>;
205 phy-mode = "rmii";
206 ethernet = <&fec1>;
207
208 fixed-link {
209 speed = <100>;
210 full-duplex;
211 };
212 };
213 };
214 };
215 };
216 };
217
218 &i2c0 {
219 clock-frequency = <100000>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_i2c0>;
222 status = "okay";
223
224 io-expander@22 {
225 compatible = "nxp,pca9554";
226 reg = <0x22>;
227 gpio-controller;
228 #gpio-cells = <2>;
229 };
230
231 lm75@48 {
232 compatible = "national,lm75";
233 reg = <0x48>;
234 };
235
236 eeprom@52 {
237 compatible = "atmel,24c04";
238 reg = <0x52>;
239 label = "nvm";
240 };
241
242 eeprom@54 {
243 compatible = "atmel,24c04";
244 reg = <0x54>;
245 label = "nameplate";
246 };
247 };
248
249 &i2c1 {
250 clock-frequency = <100000>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c1>;
253 status = "okay";
254
255 watchdog@38 {
256 compatible = "zii,rave-wdt";
257 reg = <0x38>;
258 };
259 };
260
261 &snvsrtc {
262 status = "disabled";
263 };
264
265 &uart0 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_uart0>;
268 status = "okay";
269 };
270
271 &iomuxc {
272 pinctrl_dspi1: dspi1grp {
273 fsl,pins = <
274 VF610_PAD_PTD5__DSPI1_CS0 0x1182
275 VF610_PAD_PTC6__DSPI1_SIN 0x1181
276 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
277 VF610_PAD_PTC8__DSPI1_SCK 0x1182
278 >;
279 };
280
281 pinctrl_esdhc0: esdhc0grp {
282 fsl,pins = <
283 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
284 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
285 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
286 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
287 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
288 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
289 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
290 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
291 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
292 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
293 >;
294 };
295
296 pinctrl_esdhc1: esdhc1grp {
297 fsl,pins = <
298 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
299 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
300 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
301 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
302 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
303 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
304 >;
305 };
306
307 pinctrl_fec1: fec1grp {
308 fsl,pins = <
309 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
310 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe
311 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
312 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
313 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
314 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
315 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
316 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
317 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
318 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
319 >;
320 };
321
322 pinctrl_i2c0: i2c0grp {
323 fsl,pins = <
324 VF610_PAD_PTB14__I2C0_SCL 0x37ff
325 VF610_PAD_PTB15__I2C0_SDA 0x37ff
326 >;
327 };
328
329 pinctrl_i2c1: i2c1grp {
330 fsl,pins = <
331 VF610_PAD_PTB16__I2C1_SCL 0x37ff
332 VF610_PAD_PTB17__I2C1_SDA 0x37ff
333 >;
334 };
335
336 pinctrl_leds_debug: pinctrl-leds-debug {
337 fsl,pins = <
338 VF610_PAD_PTD3__GPIO_82 0x31c2
339 VF610_PAD_PTE3__GPIO_108 0x31c2
340 VF610_PAD_PTE4__GPIO_109 0x31c2
341 VF610_PAD_PTE5__GPIO_110 0x31c2
342 VF610_PAD_PTE6__GPIO_111 0x31c2
343 >;
344 };
345
346 pinctrl_optical: optical-grp {
347 fsl,pins = <
348 /* SFF SD input */
349 VF610_PAD_PTE27__GPIO_132 0x3061
350
351 /* SFF Transmit disable output */
352 VF610_PAD_PTE13__GPIO_118 0x3043
353 >;
354 };
355
356 pinctrl_switch: switch-grp {
357 fsl,pins = <
358 VF610_PAD_PTB28__GPIO_98 0x3061
359 >;
360 };
361
362 pinctrl_uart0: uart0grp {
363 fsl,pins = <
364 VF610_PAD_PTB10__UART0_TX 0x21a2
365 VF610_PAD_PTB11__UART0_RX 0x21a1
366 >;
367 };
368 };
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