1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "Qualcomm APQ8064";
16 compatible = "qcom,apq8064";
17 interrupt-parent = <&intc>;
18
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 smem_region: smem@80000000 {
25 reg = <0x80000000 0x200000>;
26 no-map;
27 };
28
29 wcnss_mem: wcnss@8f000000 {
30 reg = <0x8f000000 0x700000>;
31 no-map;
32 };
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 CPU0: cpu@0 {
40 compatible = "qcom,krait";
41 enable-method = "qcom,kpss-acc-v1";
42 device_type = "cpu";
43 reg = <0>;
44 next-level-cache = <&L2>;
45 qcom,acc = <&acc0>;
46 qcom,saw = <&saw0>;
47 cpu-idle-states = <&CPU_SPC>;
48 };
49
50 CPU1: cpu@1 {
51 compatible = "qcom,krait";
52 enable-method = "qcom,kpss-acc-v1";
53 device_type = "cpu";
54 reg = <1>;
55 next-level-cache = <&L2>;
56 qcom,acc = <&acc1>;
57 qcom,saw = <&saw1>;
58 cpu-idle-states = <&CPU_SPC>;
59 };
60
61 CPU2: cpu@2 {
62 compatible = "qcom,krait";
63 enable-method = "qcom,kpss-acc-v1";
64 device_type = "cpu";
65 reg = <2>;
66 next-level-cache = <&L2>;
67 qcom,acc = <&acc2>;
68 qcom,saw = <&saw2>;
69 cpu-idle-states = <&CPU_SPC>;
70 };
71
72 CPU3: cpu@3 {
73 compatible = "qcom,krait";
74 enable-method = "qcom,kpss-acc-v1";
75 device_type = "cpu";
76 reg = <3>;
77 next-level-cache = <&L2>;
78 qcom,acc = <&acc3>;
79 qcom,saw = <&saw3>;
80 cpu-idle-states = <&CPU_SPC>;
81 };
82
83 L2: l2-cache {
84 compatible = "cache";
85 cache-level = <2>;
86 cache-unified;
87 };
88
89 idle-states {
90 CPU_SPC: cpu-spc {
91 compatible = "qcom,idle-state-spc",
92 "arm,idle-state";
93 entry-latency-us = <400>;
94 exit-latency-us = <900>;
95 min-residency-us = <3000>;
96 };
97 };
98 };
99
100 memory@0 {
101 device_type = "memory";
102 reg = <0x0 0x0>;
103 };
104
105 thermal-zones {
106 cpu0-thermal {
107 polling-delay-passive = <250>;
108 polling-delay = <1000>;
109
110 thermal-sensors = <&tsens 7>;
111 coefficients = <1199 0>;
112
113 trips {
114 cpu_alert0: trip0 {
115 temperature = <75000>;
116 hysteresis = <2000>;
117 type = "passive";
118 };
119 cpu_crit0: trip1 {
120 temperature = <110000>;
121 hysteresis = <2000>;
122 type = "critical";
123 };
124 };
125 };
126
127 cpu1-thermal {
128 polling-delay-passive = <250>;
129 polling-delay = <1000>;
130
131 thermal-sensors = <&tsens 8>;
132 coefficients = <1132 0>;
133
134 trips {
135 cpu_alert1: trip0 {
136 temperature = <75000>;
137 hysteresis = <2000>;
138 type = "passive";
139 };
140 cpu_crit1: trip1 {
141 temperature = <110000>;
142 hysteresis = <2000>;
143 type = "critical";
144 };
145 };
146 };
147
148 cpu2-thermal {
149 polling-delay-passive = <250>;
150 polling-delay = <1000>;
151
152 thermal-sensors = <&tsens 9>;
153 coefficients = <1199 0>;
154
155 trips {
156 cpu_alert2: trip0 {
157 temperature = <75000>;
158 hysteresis = <2000>;
159 type = "passive";
160 };
161 cpu_crit2: trip1 {
162 temperature = <110000>;
163 hysteresis = <2000>;
164 type = "critical";
165 };
166 };
167 };
168
169 cpu3-thermal {
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
172
173 thermal-sensors = <&tsens 10>;
174 coefficients = <1132 0>;
175
176 trips {
177 cpu_alert3: trip0 {
178 temperature = <75000>;
179 hysteresis = <2000>;
180 type = "passive";
181 };
182 cpu_crit3: trip1 {
183 temperature = <110000>;
184 hysteresis = <2000>;
185 type = "critical";
186 };
187 };
188 };
189 };
190
191 cpu-pmu {
192 compatible = "qcom,krait-pmu";
193 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
194 };
195
196 clocks {
197 cxo_board: cxo_board {
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <19200000>;
201 };
202
203 pxo_board: pxo_board {
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <27000000>;
207 };
208
209 sleep_clk: sleep_clk {
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <32768>;
213 };
214 };
215
216 sfpb_mutex: hwmutex {
217 compatible = "qcom,sfpb-mutex";
218 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
219 #hwlock-cells = <1>;
220 };
221
222 smem {
223 compatible = "qcom,smem";
224 memory-region = <&smem_region>;
225
226 hwlocks = <&sfpb_mutex 3>;
227 };
228
229 smsm {
230 compatible = "qcom,smsm";
231
232 #address-cells = <1>;
233 #size-cells = <0>;
234
235 qcom,ipc-1 = <&l2cc 8 4>;
236 qcom,ipc-2 = <&l2cc 8 14>;
237 qcom,ipc-3 = <&l2cc 8 23>;
238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
239
240 apps_smsm: apps@0 {
241 reg = <0>;
242 #qcom,smem-state-cells = <1>;
243 };
244
245 modem_smsm: modem@1 {
246 reg = <1>;
247 interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
248
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 q6_smsm: q6@2 {
254 reg = <2>;
255 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
256
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 };
260
261 wcnss_smsm: wcnss@3 {
262 reg = <3>;
263 interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
264
265 interrupt-controller;
266 #interrupt-cells = <2>;
267 };
268
269 dsps_smsm: dsps@4 {
270 reg = <4>;
271 interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>;
272
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
276 };
277
278 firmware {
279 scm {
280 compatible = "qcom,scm-apq8064", "qcom,scm";
281
282 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
283 clock-names = "core";
284 };
285 };
286
287 soc: soc {
288 #address-cells = <1>;
289 #size-cells = <1>;
290 ranges;
291 compatible = "simple-bus";
292
293 tlmm_pinmux: pinctrl@800000 {
294 compatible = "qcom,apq8064-pinctrl";
295 reg = <0x800000 0x4000>;
296
297 gpio-controller;
298 gpio-ranges = <&tlmm_pinmux 0 0 90>;
299 #gpio-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
303
304 pinctrl-names = "default";
305 pinctrl-0 = <&ps_hold_default_state>;
306 };
307
308 sfpb_wrapper_mutex: syscon@1200000 {
309 compatible = "syscon";
310 reg = <0x01200000 0x8000>;
311 };
312
313 intc: interrupt-controller@2000000 {
314 compatible = "qcom,msm-qgic2";
315 interrupt-controller;
316 #interrupt-cells = <3>;
317 reg = <0x02000000 0x1000>,
318 <0x02002000 0x1000>;
319 };
320
321 timer@200a000 {
322 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
323 "qcom,msm-timer";
324 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
325 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
326 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
327 reg = <0x0200a000 0x100>;
328 clock-frequency = <27000000>;
329 cpu-offset = <0x80000>;
330 };
331
332 acc0: clock-controller@2088000 {
333 compatible = "qcom,kpss-acc-v1";
334 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
335 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
336 clock-names = "pll8_vote", "pxo";
337 clock-output-names = "acpu0_aux";
338 #clock-cells = <0>;
339 };
340
341 acc1: clock-controller@2098000 {
342 compatible = "qcom,kpss-acc-v1";
343 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
344 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
345 clock-names = "pll8_vote", "pxo";
346 clock-output-names = "acpu1_aux";
347 #clock-cells = <0>;
348 };
349
350 acc2: clock-controller@20a8000 {
351 compatible = "qcom,kpss-acc-v1";
352 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
353 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
354 clock-names = "pll8_vote", "pxo";
355 clock-output-names = "acpu2_aux";
356 #clock-cells = <0>;
357 };
358
359 acc3: clock-controller@20b8000 {
360 compatible = "qcom,kpss-acc-v1";
361 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
362 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
363 clock-names = "pll8_vote", "pxo";
364 clock-output-names = "acpu3_aux";
365 #clock-cells = <0>;
366 };
367
368 saw0: power-manager@2089000 {
369 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
370 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
371
372 saw0_vreg: regulator {
373 regulator-min-microvolt = <850000>;
374 regulator-max-microvolt = <1300000>;
375 };
376 };
377
378 saw1: power-manager@2099000 {
379 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
380 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
381
382 saw1_vreg: regulator {
383 regulator-min-microvolt = <850000>;
384 regulator-max-microvolt = <1300000>;
385 };
386 };
387
388 saw2: power-manager@20a9000 {
389 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
390 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
391
392 saw2_vreg: regulator {
393 regulator-min-microvolt = <850000>;
394 regulator-max-microvolt = <1300000>;
395 };
396 };
397
398 saw3: power-manager@20b9000 {
399 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
400 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
401
402 saw3_vreg: regulator {
403 regulator-min-microvolt = <850000>;
404 regulator-max-microvolt = <1300000>;
405 };
406 };
407
408 sps_sic_non_secure: sps-sic-non-secure@12100000 {
409 compatible = "syscon";
410 reg = <0x12100000 0x10000>;
411 };
412
413 gsbi1: gsbi@12440000 {
414 status = "disabled";
415 compatible = "qcom,gsbi-v1.0.0";
416 cell-index = <1>;
417 reg = <0x12440000 0x100>;
418 clocks = <&gcc GSBI1_H_CLK>;
419 clock-names = "iface";
420 #address-cells = <1>;
421 #size-cells = <1>;
422 ranges;
423
424 syscon-tcsr = <&tcsr>;
425
426 gsbi1_serial: serial@12450000 {
427 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
428 reg = <0x12450000 0x100>,
429 <0x12400000 0x03>;
430 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
432 clock-names = "core", "iface";
433 status = "disabled";
434 };
435
436 gsbi1_i2c: i2c@12460000 {
437 compatible = "qcom,i2c-qup-v1.1.1";
438 pinctrl-0 = <&i2c1_default_state>;
439 pinctrl-1 = <&i2c1_sleep_state>;
440 pinctrl-names = "default", "sleep";
441 reg = <0x12460000 0x1000>;
442 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
444 clock-names = "core", "iface";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 status = "disabled";
448 };
449
450 };
451
452 gsbi2: gsbi@12480000 {
453 status = "disabled";
454 compatible = "qcom,gsbi-v1.0.0";
455 cell-index = <2>;
456 reg = <0x12480000 0x100>;
457 clocks = <&gcc GSBI2_H_CLK>;
458 clock-names = "iface";
459 #address-cells = <1>;
460 #size-cells = <1>;
461 ranges;
462
463 syscon-tcsr = <&tcsr>;
464
465 gsbi2_i2c: i2c@124a0000 {
466 compatible = "qcom,i2c-qup-v1.1.1";
467 reg = <0x124a0000 0x1000>;
468 pinctrl-0 = <&i2c2_default_state>;
469 pinctrl-1 = <&i2c2_sleep_state>;
470 pinctrl-names = "default", "sleep";
471 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
473 clock-names = "core", "iface";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478 };
479
480 gsbi3: gsbi@16200000 {
481 status = "disabled";
482 compatible = "qcom,gsbi-v1.0.0";
483 cell-index = <3>;
484 reg = <0x16200000 0x100>;
485 clocks = <&gcc GSBI3_H_CLK>;
486 clock-names = "iface";
487 #address-cells = <1>;
488 #size-cells = <1>;
489 ranges;
490 gsbi3_i2c: i2c@16280000 {
491 compatible = "qcom,i2c-qup-v1.1.1";
492 pinctrl-0 = <&i2c3_default_state>;
493 pinctrl-1 = <&i2c3_sleep_state>;
494 pinctrl-names = "default", "sleep";
495 reg = <0x16280000 0x1000>;
496 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&gcc GSBI3_QUP_CLK>,
498 <&gcc GSBI3_H_CLK>;
499 clock-names = "core", "iface";
500 #address-cells = <1>;
501 #size-cells = <0>;
502 status = "disabled";
503 };
504 };
505
506 gsbi4: gsbi@16300000 {
507 status = "disabled";
508 compatible = "qcom,gsbi-v1.0.0";
509 cell-index = <4>;
510 reg = <0x16300000 0x03>;
511 clocks = <&gcc GSBI4_H_CLK>;
512 clock-names = "iface";
513 #address-cells = <1>;
514 #size-cells = <1>;
515 ranges;
516
517 gsbi4_serial: serial@16340000 {
518 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
519 reg = <0x16340000 0x100>,
520 <0x16300000 0x3>;
521 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
522 pinctrl-0 = <&gsbi4_uart_pin_a>;
523 pinctrl-names = "default";
524 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
525 clock-names = "core", "iface";
526 status = "disabled";
527 };
528
529 gsbi4_i2c: i2c@16380000 {
530 compatible = "qcom,i2c-qup-v1.1.1";
531 pinctrl-0 = <&i2c4_default_state>;
532 pinctrl-1 = <&i2c4_sleep_state>;
533 pinctrl-names = "default", "sleep";
534 reg = <0x16380000 0x1000>;
535 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&gcc GSBI4_QUP_CLK>,
537 <&gcc GSBI4_H_CLK>;
538 clock-names = "core", "iface";
539 status = "disabled";
540 };
541 };
542
543 gsbi5: gsbi@1a200000 {
544 status = "disabled";
545 compatible = "qcom,gsbi-v1.0.0";
546 cell-index = <5>;
547 reg = <0x1a200000 0x03>;
548 clocks = <&gcc GSBI5_H_CLK>;
549 clock-names = "iface";
550 #address-cells = <1>;
551 #size-cells = <1>;
552 ranges;
553
554 gsbi5_serial: serial@1a240000 {
555 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
556 reg = <0x1a240000 0x100>,
557 <0x1a200000 0x03>;
558 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
560 clock-names = "core", "iface";
561 status = "disabled";
562 };
563
564 gsbi5_spi: spi@1a280000 {
565 compatible = "qcom,spi-qup-v1.1.1";
566 reg = <0x1a280000 0x1000>;
567 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
568 pinctrl-0 = <&spi5_default_state>;
569 pinctrl-1 = <&spi5_sleep_state>;
570 pinctrl-names = "default", "sleep";
571 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
572 clock-names = "core", "iface";
573 status = "disabled";
574 #address-cells = <1>;
575 #size-cells = <0>;
576 };
577 };
578
579 gsbi6: gsbi@16500000 {
580 status = "disabled";
581 compatible = "qcom,gsbi-v1.0.0";
582 cell-index = <6>;
583 reg = <0x16500000 0x03>;
584 clocks = <&gcc GSBI6_H_CLK>;
585 clock-names = "iface";
586 #address-cells = <1>;
587 #size-cells = <1>;
588 ranges;
589
590 gsbi6_serial: serial@16540000 {
591 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
592 reg = <0x16540000 0x100>,
593 <0x16500000 0x03>;
594 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
596 clock-names = "core", "iface";
597 status = "disabled";
598 };
599
600 gsbi6_i2c: i2c@16580000 {
601 compatible = "qcom,i2c-qup-v1.1.1";
602 pinctrl-0 = <&i2c6_default_state>;
603 pinctrl-1 = <&i2c6_sleep_state>;
604 pinctrl-names = "default", "sleep";
605 reg = <0x16580000 0x1000>;
606 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&gcc GSBI6_QUP_CLK>,
608 <&gcc GSBI6_H_CLK>;
609 clock-names = "core", "iface";
610 status = "disabled";
611 };
612 };
613
614 gsbi7: gsbi@16600000 {
615 status = "disabled";
616 compatible = "qcom,gsbi-v1.0.0";
617 cell-index = <7>;
618 reg = <0x16600000 0x100>;
619 clocks = <&gcc GSBI7_H_CLK>;
620 clock-names = "iface";
621 #address-cells = <1>;
622 #size-cells = <1>;
623 ranges;
624 syscon-tcsr = <&tcsr>;
625
626 gsbi7_serial: serial@16640000 {
627 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
628 reg = <0x16640000 0x1000>,
629 <0x16600000 0x1000>;
630 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
632 clock-names = "core", "iface";
633 status = "disabled";
634 };
635
636 gsbi7_i2c: i2c@16680000 {
637 compatible = "qcom,i2c-qup-v1.1.1";
638 pinctrl-0 = <&i2c7_default_state>;
639 pinctrl-1 = <&i2c7_sleep_state>;
640 pinctrl-names = "default", "sleep";
641 reg = <0x16680000 0x1000>;
642 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&gcc GSBI7_QUP_CLK>,
644 <&gcc GSBI7_H_CLK>;
645 clock-names = "core", "iface";
646 status = "disabled";
647 };
648 };
649
650 rng@1a500000 {
651 compatible = "qcom,prng";
652 reg = <0x1a500000 0x200>;
653 clocks = <&gcc PRNG_CLK>;
654 clock-names = "core";
655 };
656
657 ssbi2: ssbi@c00000 {
658 compatible = "qcom,ssbi";
659 reg = <0x00c00000 0x1000>;
660 qcom,controller-type = "pmic-arbiter";
661 };
662
663 ssbi: ssbi@500000 {
664 compatible = "qcom,ssbi";
665 reg = <0x00500000 0x1000>;
666 qcom,controller-type = "pmic-arbiter";
667 };
668
669 qfprom: efuse@700000 {
670 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
671 reg = <0x00700000 0x1000>;
672 #address-cells = <1>;
673 #size-cells = <1>;
674
675 tsens_calib: calib@404 {
676 reg = <0x404 0x10>;
677 };
678 tsens_backup: backup_calib@414 {
679 reg = <0x414 0x10>;
680 };
681 };
682
683 gcc: clock-controller@900000 {
684 compatible = "qcom,gcc-apq8064", "syscon";
685 reg = <0x00900000 0x4000>;
686 #clock-cells = <1>;
687 #reset-cells = <1>;
688 clocks = <&cxo_board>,
689 <&pxo_board>,
690 <&lcc PLL4>;
691 clock-names = "cxo", "pxo", "pll4";
692
693 tsens: thermal-sensor {
694 compatible = "qcom,msm8960-tsens";
695
696 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
697 nvmem-cell-names = "calib", "calib_backup";
698 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
699 interrupt-names = "uplow";
700
701 #qcom,sensors = <11>;
702 #thermal-sensor-cells = <1>;
703 };
704 };
705
706 lcc: clock-controller@28000000 {
707 compatible = "qcom,lcc-apq8064";
708 reg = <0x28000000 0x1000>;
709 #clock-cells = <1>;
710 #reset-cells = <1>;
711 clocks = <&pxo_board>,
712 <&gcc PLL4_VOTE>,
713 <0>,
714 <0>, <0>,
715 <0>, <0>,
716 <0>;
717 clock-names = "pxo",
718 "pll4_vote",
719 "mi2s_codec_clk",
720 "codec_i2s_mic_codec_clk",
721 "spare_i2s_mic_codec_clk",
722 "codec_i2s_spkr_codec_clk",
723 "spare_i2s_spkr_codec_clk",
724 "pcm_codec_clk";
725 };
726
727 mmcc: clock-controller@4000000 {
728 compatible = "qcom,mmcc-apq8064";
729 reg = <0x4000000 0x1000>;
730 #clock-cells = <1>;
731 #power-domain-cells = <1>;
732 #reset-cells = <1>;
733 clocks = <&pxo_board>,
734 <&gcc PLL3>,
735 <&gcc PLL8_VOTE>,
736 <&dsi0_phy 1>,
737 <&dsi0_phy 0>,
738 <&dsi1_phy 1>,
739 <&dsi1_phy 0>,
740 <&hdmi_phy>;
741 clock-names = "pxo",
742 "pll3",
743 "pll8_vote",
744 "dsi1pll",
745 "dsi1pllbyte",
746 "dsi2pll",
747 "dsi2pllbyte",
748 "hdmipll";
749 };
750
751 l2cc: clock-controller@2011000 {
752 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
753 reg = <0x2011000 0x1000>;
754 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
755 clock-names = "pll8_vote", "pxo";
756 #clock-cells = <0>;
757 };
758
759 rpm: rpm@108000 {
760 compatible = "qcom,rpm-apq8064";
761 reg = <0x108000 0x1000>;
762 qcom,ipc = <&l2cc 0x8 2>;
763
764 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
765 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
766 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
767 interrupt-names = "ack", "err", "wakeup";
768
769 rpmcc: clock-controller {
770 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
771 #clock-cells = <1>;
772 clocks = <&pxo_board>, <&cxo_board>;
773 clock-names = "pxo", "cxo";
774 };
775 };
776
777 usb1: usb@12500000 {
778 compatible = "qcom,ci-hdrc";
779 reg = <0x12500000 0x200>,
780 <0x12500200 0x200>;
781 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
783 clock-names = "core", "iface";
784 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
785 assigned-clock-rates = <60000000>;
786 resets = <&gcc USB_HS1_RESET>;
787 reset-names = "core";
788 phy_type = "ulpi";
789 ahb-burst-config = <0>;
790 phys = <&usb_hs1_phy>;
791 phy-names = "usb-phy";
792 status = "disabled";
793 #reset-cells = <1>;
794
795 ulpi {
796 usb_hs1_phy: phy {
797 compatible = "qcom,usb-hs-phy-apq8064",
798 "qcom,usb-hs-phy";
799 clocks = <&sleep_clk>, <&cxo_board>;
800 clock-names = "sleep", "ref";
801 resets = <&usb1 0>;
802 reset-names = "por";
803 #phy-cells = <0>;
804 };
805 };
806 };
807
808 usb3: usb@12520000 {
809 compatible = "qcom,ci-hdrc";
810 reg = <0x12520000 0x200>,
811 <0x12520200 0x200>;
812 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
814 clock-names = "core", "iface";
815 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
816 assigned-clock-rates = <60000000>;
817 resets = <&gcc USB_HS3_RESET>;
818 reset-names = "core";
819 phy_type = "ulpi";
820 ahb-burst-config = <0>;
821 phys = <&usb_hs3_phy>;
822 phy-names = "usb-phy";
823 status = "disabled";
824 #reset-cells = <1>;
825
826 ulpi {
827 usb_hs3_phy: phy {
828 compatible = "qcom,usb-hs-phy-apq8064",
829 "qcom,usb-hs-phy";
830 #phy-cells = <0>;
831 clocks = <&sleep_clk>, <&cxo_board>;
832 clock-names = "sleep", "ref";
833 resets = <&usb3 0>;
834 reset-names = "por";
835 };
836 };
837 };
838
839 usb4: usb@12530000 {
840 compatible = "qcom,ci-hdrc";
841 reg = <0x12530000 0x200>,
842 <0x12530200 0x200>;
843 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
845 clock-names = "core", "iface";
846 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
847 assigned-clock-rates = <60000000>;
848 resets = <&gcc USB_HS4_RESET>;
849 reset-names = "core";
850 phy_type = "ulpi";
851 ahb-burst-config = <0>;
852 phys = <&usb_hs4_phy>;
853 phy-names = "usb-phy";
854 status = "disabled";
855 #reset-cells = <1>;
856
857 ulpi {
858 usb_hs4_phy: phy {
859 compatible = "qcom,usb-hs-phy-apq8064",
860 "qcom,usb-hs-phy";
861 #phy-cells = <0>;
862 clocks = <&sleep_clk>, <&cxo_board>;
863 clock-names = "sleep", "ref";
864 resets = <&usb4 0>;
865 reset-names = "por";
866 };
867 };
868 };
869
870 sata_phy0: phy@1b400000 {
871 compatible = "qcom,apq8064-sata-phy";
872 status = "disabled";
873 reg = <0x1b400000 0x200>;
874 clocks = <&gcc SATA_PHY_CFG_CLK>;
875 clock-names = "cfg";
876 #phy-cells = <0>;
877 };
878
879 sata0: sata@29000000 {
880 compatible = "qcom,apq8064-ahci", "generic-ahci";
881 status = "disabled";
882 reg = <0x29000000 0x180>;
883 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
884
885 clocks = <&gcc SFAB_SATA_S_H_CLK>,
886 <&gcc SATA_H_CLK>,
887 <&gcc SATA_A_CLK>,
888 <&gcc SATA_RXOOB_CLK>,
889 <&gcc SATA_PMALIVE_CLK>;
890 clock-names = "slave_iface",
891 "iface",
892 "core",
893 "rxoob",
894 "pmalive";
895
896 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
897 <&gcc SATA_PMALIVE_CLK>;
898 assigned-clock-rates = <100000000>, <100000000>;
899
900 phys = <&sata_phy0>;
901 phy-names = "sata-phy";
902 ports-implemented = <0x1>;
903 };
904
905 sdcc3: mmc@12180000 {
906 compatible = "arm,pl18x", "arm,primecell";
907 arm,primecell-periphid = <0x00051180>;
908 status = "disabled";
909 reg = <0x12180000 0x2000>;
910 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
912 clock-names = "mclk", "apb_pclk";
913 bus-width = <4>;
914 cap-sd-highspeed;
915 cap-mmc-highspeed;
916 max-frequency = <192000000>;
917 no-1-8-v;
918 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
919 dma-names = "tx", "rx";
920 };
921
922 sdcc3bam: dma-controller@12182000 {
923 compatible = "qcom,bam-v1.3.0";
924 reg = <0x12182000 0x8000>;
925 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&gcc SDC3_H_CLK>;
927 clock-names = "bam_clk";
928 #dma-cells = <1>;
929 qcom,ee = <0>;
930 };
931
932 sdcc4: mmc@121c0000 {
933 compatible = "arm,pl18x", "arm,primecell";
934 arm,primecell-periphid = <0x00051180>;
935 status = "disabled";
936 reg = <0x121c0000 0x2000>;
937 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
939 clock-names = "mclk", "apb_pclk";
940 bus-width = <4>;
941 cap-sd-highspeed;
942 cap-mmc-highspeed;
943 max-frequency = <48000000>;
944 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
945 dma-names = "tx", "rx";
946 pinctrl-names = "default";
947 pinctrl-0 = <&sdc4_default_state>;
948 };
949
950 sdcc4bam: dma-controller@121c2000 {
951 compatible = "qcom,bam-v1.3.0";
952 reg = <0x121c2000 0x8000>;
953 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&gcc SDC4_H_CLK>;
955 clock-names = "bam_clk";
956 #dma-cells = <1>;
957 qcom,ee = <0>;
958 };
959
960 sdcc1: mmc@12400000 {
961 status = "disabled";
962 compatible = "arm,pl18x", "arm,primecell";
963 pinctrl-names = "default";
964 pinctrl-0 = <&sdcc1_default_state>;
965 arm,primecell-periphid = <0x00051180>;
966 reg = <0x12400000 0x2000>;
967 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
969 clock-names = "mclk", "apb_pclk";
970 bus-width = <8>;
971 max-frequency = <96000000>;
972 non-removable;
973 cap-sd-highspeed;
974 cap-mmc-highspeed;
975 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
976 dma-names = "tx", "rx";
977 };
978
979 sdcc1bam: dma-controller@12402000 {
980 compatible = "qcom,bam-v1.3.0";
981 reg = <0x12402000 0x8000>;
982 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&gcc SDC1_H_CLK>;
984 clock-names = "bam_clk";
985 #dma-cells = <1>;
986 qcom,ee = <0>;
987 };
988
989 tcsr: syscon@1a400000 {
990 compatible = "qcom,tcsr-apq8064", "syscon";
991 reg = <0x1a400000 0x100>;
992 };
993
994 gpu: gpu@4300000 {
995 compatible = "qcom,adreno-320.2", "qcom,adreno";
996 reg = <0x04300000 0x20000>;
997 reg-names = "kgsl_3d0_reg_memory";
998 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
999 interrupt-names = "kgsl_3d0_irq";
1000 clock-names =
1001 "core",
1002 "iface",
1003 "mem",
1004 "mem_iface";
1005 clocks =
1006 <&mmcc GFX3D_CLK>,
1007 <&mmcc GFX3D_AHB_CLK>,
1008 <&mmcc GFX3D_AXI_CLK>,
1009 <&mmcc MMSS_IMEM_AHB_CLK>;
1010
1011 iommus = <&gfx3d 0
1012 &gfx3d 1
1013 &gfx3d 2
1014 &gfx3d 3
1015 &gfx3d 4
1016 &gfx3d 5
1017 &gfx3d 6
1018 &gfx3d 7
1019 &gfx3d 8
1020 &gfx3d 9
1021 &gfx3d 10
1022 &gfx3d 11
1023 &gfx3d 12
1024 &gfx3d 13
1025 &gfx3d 14
1026 &gfx3d 15
1027 &gfx3d 16
1028 &gfx3d 17
1029 &gfx3d 18
1030 &gfx3d 19
1031 &gfx3d 20
1032 &gfx3d 21
1033 &gfx3d 22
1034 &gfx3d 23
1035 &gfx3d 24
1036 &gfx3d 25
1037 &gfx3d 26
1038 &gfx3d 27
1039 &gfx3d 28
1040 &gfx3d 29
1041 &gfx3d 30
1042 &gfx3d 31
1043 &gfx3d1 0
1044 &gfx3d1 1
1045 &gfx3d1 2
1046 &gfx3d1 3
1047 &gfx3d1 4
1048 &gfx3d1 5
1049 &gfx3d1 6
1050 &gfx3d1 7
1051 &gfx3d1 8
1052 &gfx3d1 9
1053 &gfx3d1 10
1054 &gfx3d1 11
1055 &gfx3d1 12
1056 &gfx3d1 13
1057 &gfx3d1 14
1058 &gfx3d1 15
1059 &gfx3d1 16
1060 &gfx3d1 17
1061 &gfx3d1 18
1062 &gfx3d1 19
1063 &gfx3d1 20
1064 &gfx3d1 21
1065 &gfx3d1 22
1066 &gfx3d1 23
1067 &gfx3d1 24
1068 &gfx3d1 25
1069 &gfx3d1 26
1070 &gfx3d1 27
1071 &gfx3d1 28
1072 &gfx3d1 29
1073 &gfx3d1 30
1074 &gfx3d1 31>;
1075
1076 operating-points-v2 = <&gpu_opp_table>;
1077
1078 gpu_opp_table: opp-table {
1079 compatible = "operating-points-v2";
1080
1081 opp-450000000 {
1082 opp-hz = /bits/ 64 <450000000>;
1083 };
1084
1085 opp-27000000 {
1086 opp-hz = /bits/ 64 <27000000>;
1087 };
1088 };
1089 };
1090
1091 mmss_sfpb: syscon@5700000 {
1092 compatible = "syscon";
1093 reg = <0x5700000 0x70>;
1094 };
1095
1096 dsi0: dsi@4700000 {
1097 compatible = "qcom,apq8064-dsi-ctrl",
1098 "qcom,mdss-dsi-ctrl";
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1102 reg = <0x04700000 0x200>;
1103 reg-names = "dsi_ctrl";
1104
1105 clocks = <&mmcc DSI_M_AHB_CLK>,
1106 <&mmcc DSI_S_AHB_CLK>,
1107 <&mmcc AMP_AHB_CLK>,
1108 <&mmcc DSI_CLK>,
1109 <&mmcc DSI1_BYTE_CLK>,
1110 <&mmcc DSI_PIXEL_CLK>,
1111 <&mmcc DSI1_ESC_CLK>;
1112 clock-names = "iface", "bus", "core_mmss",
1113 "src", "byte", "pixel",
1114 "core";
1115
1116 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1117 <&mmcc DSI1_ESC_SRC>,
1118 <&mmcc DSI_SRC>,
1119 <&mmcc DSI_PIXEL_SRC>;
1120 assigned-clock-parents = <&dsi0_phy 0>,
1121 <&dsi0_phy 0>,
1122 <&dsi0_phy 1>,
1123 <&dsi0_phy 1>;
1124 syscon-sfpb = <&mmss_sfpb>;
1125 phys = <&dsi0_phy>;
1126 status = "disabled";
1127
1128 ports {
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131
1132 port@0 {
1133 reg = <0>;
1134 dsi0_in: endpoint {
1135 };
1136 };
1137
1138 port@1 {
1139 reg = <1>;
1140 dsi0_out: endpoint {
1141 };
1142 };
1143 };
1144 };
1145
1146
1147 dsi0_phy: phy@4700200 {
1148 compatible = "qcom,dsi-phy-28nm-8960";
1149 #clock-cells = <1>;
1150 #phy-cells = <0>;
1151
1152 reg = <0x04700200 0x100>,
1153 <0x04700300 0x200>,
1154 <0x04700500 0x5c>;
1155 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1156 clock-names = "iface", "ref";
1157 clocks = <&mmcc DSI_M_AHB_CLK>,
1158 <&pxo_board>;
1159 status = "disabled";
1160 };
1161
1162 dsi1: dsi@5800000 {
1163 compatible = "qcom,mdss-dsi-ctrl";
1164 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1165 reg = <0x05800000 0x200>;
1166 reg-names = "dsi_ctrl";
1167
1168 clocks = <&mmcc DSI2_M_AHB_CLK>,
1169 <&mmcc DSI2_S_AHB_CLK>,
1170 <&mmcc AMP_AHB_CLK>,
1171 <&mmcc DSI2_CLK>,
1172 <&mmcc DSI2_BYTE_CLK>,
1173 <&mmcc DSI2_PIXEL_CLK>,
1174 <&mmcc DSI2_ESC_CLK>;
1175 clock-names = "iface",
1176 "bus",
1177 "core_mmss",
1178 "src",
1179 "byte",
1180 "pixel",
1181 "core";
1182
1183 assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1184 <&mmcc DSI2_ESC_SRC>,
1185 <&mmcc DSI2_SRC>,
1186 <&mmcc DSI2_PIXEL_SRC>;
1187 assigned-clock-parents = <&dsi1_phy 0>,
1188 <&dsi1_phy 0>,
1189 <&dsi1_phy 1>,
1190 <&dsi1_phy 1>;
1191
1192 syscon-sfpb = <&mmss_sfpb>;
1193 phys = <&dsi1_phy>;
1194
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1197
1198 status = "disabled";
1199
1200 ports {
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1203
1204 port@0 {
1205 reg = <0>;
1206 dsi1_in: endpoint {
1207 };
1208 };
1209
1210 port@1 {
1211 reg = <1>;
1212 dsi1_out: endpoint {
1213 };
1214 };
1215 };
1216 };
1217
1218
1219 dsi1_phy: dsi-phy@5800200 {
1220 compatible = "qcom,dsi-phy-28nm-8960";
1221 reg = <0x05800200 0x100>,
1222 <0x05800300 0x200>,
1223 <0x05800500 0x5c>;
1224 reg-names = "dsi_pll",
1225 "dsi_phy",
1226 "dsi_phy_regulator";
1227 clock-names = "iface",
1228 "ref";
1229 clocks = <&mmcc DSI2_M_AHB_CLK>,
1230 <&pxo_board>;
1231 #clock-cells = <1>;
1232 #phy-cells = <0>;
1233
1234 status = "disabled";
1235 };
1236
1237 mdp_port0: iommu@7500000 {
1238 compatible = "qcom,apq8064-iommu";
1239 #iommu-cells = <1>;
1240 clock-names =
1241 "smmu_pclk",
1242 "iommu_clk";
1243 clocks =
1244 <&mmcc SMMU_AHB_CLK>,
1245 <&mmcc MDP_AXI_CLK>;
1246 reg = <0x07500000 0x100000>;
1247 interrupts =
1248 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1250 qcom,ncb = <2>;
1251 };
1252
1253 mdp_port1: iommu@7600000 {
1254 compatible = "qcom,apq8064-iommu";
1255 #iommu-cells = <1>;
1256 clock-names =
1257 "smmu_pclk",
1258 "iommu_clk";
1259 clocks =
1260 <&mmcc SMMU_AHB_CLK>,
1261 <&mmcc MDP_AXI_CLK>;
1262 reg = <0x07600000 0x100000>;
1263 interrupts =
1264 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1266 qcom,ncb = <2>;
1267 };
1268
1269 gfx3d: iommu@7c00000 {
1270 compatible = "qcom,apq8064-iommu";
1271 #iommu-cells = <1>;
1272 clock-names =
1273 "smmu_pclk",
1274 "iommu_clk";
1275 clocks =
1276 <&mmcc SMMU_AHB_CLK>,
1277 <&mmcc GFX3D_AXI_CLK>;
1278 reg = <0x07c00000 0x100000>;
1279 interrupts =
1280 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1282 qcom,ncb = <3>;
1283 };
1284
1285 gfx3d1: iommu@7d00000 {
1286 compatible = "qcom,apq8064-iommu";
1287 #iommu-cells = <1>;
1288 clock-names =
1289 "smmu_pclk",
1290 "iommu_clk";
1291 clocks =
1292 <&mmcc SMMU_AHB_CLK>,
1293 <&mmcc GFX3D_AXI_CLK>;
1294 reg = <0x07d00000 0x100000>;
1295 interrupts =
1296 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1298 qcom,ncb = <3>;
1299 };
1300
1301 pcie: pcie@1b500000 {
1302 compatible = "qcom,pcie-apq8064";
1303 reg = <0x1b500000 0x1000>,
1304 <0x1b502000 0x80>,
1305 <0x1b600000 0x100>,
1306 <0x0ff00000 0x100000>;
1307 reg-names = "dbi", "elbi", "parf", "config";
1308 device_type = "pci";
1309 linux,pci-domain = <0>;
1310 bus-range = <0x00 0xff>;
1311 num-lanes = <1>;
1312 #address-cells = <3>;
1313 #size-cells = <2>;
1314 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1315 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1316 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1317 interrupt-names = "msi";
1318 #interrupt-cells = <1>;
1319 interrupt-map-mask = <0 0 0 0x7>;
1320 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1321 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1322 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1323 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1324 clocks = <&gcc PCIE_A_CLK>,
1325 <&gcc PCIE_H_CLK>,
1326 <&gcc PCIE_PHY_REF_CLK>;
1327 clock-names = "core", "iface", "phy";
1328 resets = <&gcc PCIE_ACLK_RESET>,
1329 <&gcc PCIE_HCLK_RESET>,
1330 <&gcc PCIE_POR_RESET>,
1331 <&gcc PCIE_PCI_RESET>,
1332 <&gcc PCIE_PHY_RESET>;
1333 reset-names = "axi", "ahb", "por", "pci", "phy";
1334 status = "disabled";
1335
1336 pcie@0 {
1337 device_type = "pci";
1338 reg = <0x0 0x0 0x0 0x0 0x0>;
1339 bus-range = <0x01 0xff>;
1340
1341 #address-cells = <3>;
1342 #size-cells = <2>;
1343 ranges;
1344 };
1345 };
1346
1347 hdmi: hdmi-tx@4a00000 {
1348 compatible = "qcom,hdmi-tx-8960";
1349 pinctrl-names = "default";
1350 pinctrl-0 = <&hdmi_pinctrl>;
1351 reg = <0x04a00000 0x2f0>;
1352 reg-names = "core_physical";
1353 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1354 clocks = <&mmcc HDMI_APP_CLK>,
1355 <&mmcc HDMI_M_AHB_CLK>,
1356 <&mmcc HDMI_S_AHB_CLK>;
1357 clock-names = "core",
1358 "master_iface",
1359 "slave_iface";
1360
1361 phys = <&hdmi_phy>;
1362
1363 status = "disabled";
1364
1365 ports {
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1368
1369 port@0 {
1370 reg = <0>;
1371 hdmi_in: endpoint {
1372 };
1373 };
1374
1375 port@1 {
1376 reg = <1>;
1377 hdmi_out: endpoint {
1378 };
1379 };
1380 };
1381 };
1382
1383 hdmi_phy: phy@4a00400 {
1384 compatible = "qcom,hdmi-phy-8960";
1385 reg = <0x4a00400 0x60>,
1386 <0x4a00500 0x100>;
1387 reg-names = "hdmi_phy",
1388 "hdmi_pll";
1389
1390 clocks = <&mmcc HDMI_S_AHB_CLK>;
1391 clock-names = "slave_iface";
1392 #phy-cells = <0>;
1393 #clock-cells = <0>;
1394
1395 status = "disabled";
1396 };
1397
1398 mdp: display-controller@5100000 {
1399 compatible = "qcom,mdp4";
1400 reg = <0x05100000 0xf0000>;
1401 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1402 clocks = <&mmcc MDP_CLK>,
1403 <&mmcc MDP_AHB_CLK>,
1404 <&mmcc MDP_AXI_CLK>,
1405 <&mmcc MDP_LUT_CLK>,
1406 <&mmcc HDMI_TV_CLK>,
1407 <&mmcc MDP_TV_CLK>;
1408 clock-names = "core_clk",
1409 "iface_clk",
1410 "bus_clk",
1411 "lut_clk",
1412 "hdmi_clk",
1413 "tv_clk";
1414
1415 iommus = <&mdp_port0 0
1416 &mdp_port0 2
1417 &mdp_port1 0
1418 &mdp_port1 2>;
1419
1420 ports {
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1423
1424 port@0 {
1425 reg = <0>;
1426 mdp_lvds_out: endpoint {
1427 };
1428 };
1429
1430 port@1 {
1431 reg = <1>;
1432 mdp_dsi1_out: endpoint {
1433 };
1434 };
1435
1436 port@2 {
1437 reg = <2>;
1438 mdp_dsi2_out: endpoint {
1439 };
1440 };
1441
1442 port@3 {
1443 reg = <3>;
1444 mdp_dtv_out: endpoint {
1445 };
1446 };
1447 };
1448 };
1449
1450 riva: riva-pil@3200800 {
1451 compatible = "qcom,riva-pil";
1452
1453 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1454 reg-names = "ccu", "dxe", "pmu";
1455
1456 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1457 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1458 interrupt-names = "wdog", "fatal";
1459
1460 memory-region = <&wcnss_mem>;
1461
1462 status = "disabled";
1463
1464 iris {
1465 compatible = "qcom,wcn3660";
1466
1467 clocks = <&cxo_board>;
1468 clock-names = "xo";
1469 };
1470
1471 smd-edge {
1472 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1473
1474 qcom,ipc = <&l2cc 8 25>;
1475 qcom,smd-edge = <6>;
1476
1477 label = "riva";
1478
1479 wcnss {
1480 compatible = "qcom,wcnss";
1481 qcom,smd-channels = "WCNSS_CTRL";
1482
1483 qcom,mmio = <&riva>;
1484
1485 bluetooth {
1486 compatible = "qcom,wcnss-bt";
1487 };
1488
1489 wifi {
1490 compatible = "qcom,wcnss-wlan";
1491
1492 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1494 interrupt-names = "tx", "rx";
1495
1496 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1497 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1498 };
1499 };
1500 };
1501 };
1502
1503 etb@1a01000 {
1504 compatible = "arm,coresight-etb10", "arm,primecell";
1505 reg = <0x1a01000 0x1000>;
1506
1507 clocks = <&rpmcc RPM_QDSS_CLK>;
1508 clock-names = "apb_pclk";
1509
1510 in-ports {
1511 port {
1512 etb_in: endpoint {
1513 remote-endpoint = <&replicator_out0>;
1514 };
1515 };
1516 };
1517 };
1518
1519 tpiu@1a03000 {
1520 compatible = "arm,coresight-tpiu", "arm,primecell";
1521 reg = <0x1a03000 0x1000>;
1522
1523 clocks = <&rpmcc RPM_QDSS_CLK>;
1524 clock-names = "apb_pclk";
1525
1526 in-ports {
1527 port {
1528 tpiu_in: endpoint {
1529 remote-endpoint = <&replicator_out1>;
1530 };
1531 };
1532 };
1533 };
1534
1535 replicator {
1536 compatible = "arm,coresight-static-replicator";
1537
1538 clocks = <&rpmcc RPM_QDSS_CLK>;
1539 clock-names = "apb_pclk";
1540
1541 out-ports {
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544
1545 port@0 {
1546 reg = <0>;
1547 replicator_out0: endpoint {
1548 remote-endpoint = <&etb_in>;
1549 };
1550 };
1551 port@1 {
1552 reg = <1>;
1553 replicator_out1: endpoint {
1554 remote-endpoint = <&tpiu_in>;
1555 };
1556 };
1557 };
1558
1559 in-ports {
1560 port {
1561 replicator_in: endpoint {
1562 remote-endpoint = <&funnel_out>;
1563 };
1564 };
1565 };
1566 };
1567
1568 funnel@1a04000 {
1569 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1570 reg = <0x1a04000 0x1000>;
1571
1572 clocks = <&rpmcc RPM_QDSS_CLK>;
1573 clock-names = "apb_pclk";
1574
1575 in-ports {
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1578
1579 /*
1580 * Not described input ports:
1581 * 2 - connected to STM component
1582 * 3 - not-connected
1583 * 6 - not-connected
1584 * 7 - not-connected
1585 */
1586 port@0 {
1587 reg = <0>;
1588 funnel_in0: endpoint {
1589 remote-endpoint = <&etm0_out>;
1590 };
1591 };
1592 port@1 {
1593 reg = <1>;
1594 funnel_in1: endpoint {
1595 remote-endpoint = <&etm1_out>;
1596 };
1597 };
1598 port@4 {
1599 reg = <4>;
1600 funnel_in4: endpoint {
1601 remote-endpoint = <&etm2_out>;
1602 };
1603 };
1604 port@5 {
1605 reg = <5>;
1606 funnel_in5: endpoint {
1607 remote-endpoint = <&etm3_out>;
1608 };
1609 };
1610 };
1611
1612 out-ports {
1613 port {
1614 funnel_out: endpoint {
1615 remote-endpoint = <&replicator_in>;
1616 };
1617 };
1618 };
1619 };
1620
1621 etm@1a1c000 {
1622 compatible = "arm,coresight-etm3x", "arm,primecell";
1623 reg = <0x1a1c000 0x1000>;
1624
1625 clocks = <&rpmcc RPM_QDSS_CLK>;
1626 clock-names = "apb_pclk";
1627
1628 cpu = <&CPU0>;
1629
1630 out-ports {
1631 port {
1632 etm0_out: endpoint {
1633 remote-endpoint = <&funnel_in0>;
1634 };
1635 };
1636 };
1637 };
1638
1639 etm@1a1d000 {
1640 compatible = "arm,coresight-etm3x", "arm,primecell";
1641 reg = <0x1a1d000 0x1000>;
1642
1643 clocks = <&rpmcc RPM_QDSS_CLK>;
1644 clock-names = "apb_pclk";
1645
1646 cpu = <&CPU1>;
1647
1648 out-ports {
1649 port {
1650 etm1_out: endpoint {
1651 remote-endpoint = <&funnel_in1>;
1652 };
1653 };
1654 };
1655 };
1656
1657 etm@1a1e000 {
1658 compatible = "arm,coresight-etm3x", "arm,primecell";
1659 reg = <0x1a1e000 0x1000>;
1660
1661 clocks = <&rpmcc RPM_QDSS_CLK>;
1662 clock-names = "apb_pclk";
1663
1664 cpu = <&CPU2>;
1665
1666 out-ports {
1667 port {
1668 etm2_out: endpoint {
1669 remote-endpoint = <&funnel_in4>;
1670 };
1671 };
1672 };
1673 };
1674
1675 etm@1a1f000 {
1676 compatible = "arm,coresight-etm3x", "arm,primecell";
1677 reg = <0x1a1f000 0x1000>;
1678
1679 clocks = <&rpmcc RPM_QDSS_CLK>;
1680 clock-names = "apb_pclk";
1681
1682 cpu = <&CPU3>;
1683
1684 out-ports {
1685 port {
1686 etm3_out: endpoint {
1687 remote-endpoint = <&funnel_in5>;
1688 };
1689 };
1690 };
1691 };
1692 };
1693 };
1694 #include "qcom-apq8064-pins.dtsi"
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