1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SDX55 SoC device tree source
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2020, Linaro Ltd.
7 */
8
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
21 interrupt-parent = <&intc>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0>;
26 };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <38400000>;
33 clock-output-names = "xo_board";
34 };
35
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32000>;
40 };
41
42 nand_clk_dummy: nand-clk-dummy {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <32000>;
46 };
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0x0>;
57 enable-method = "psci";
58 clocks = <&apcs>;
59 power-domains = <&rpmhpd SDX55_CX>;
60 power-domain-names = "rpmhpd";
61 operating-points-v2 = <&cpu_opp_table>;
62 };
63 };
64
65 firmware {
66 scm {
67 compatible = "qcom,scm-sdx55", "qcom,scm";
68 };
69 };
70
71 cpu_opp_table: opp-table-cpu {
72 compatible = "operating-points-v2";
73 opp-shared;
74
75 opp-345600000 {
76 opp-hz = /bits/ 64 <345600000>;
77 required-opps = <&rpmhpd_opp_low_svs>;
78 };
79
80 opp-576000000 {
81 opp-hz = /bits/ 64 <576000000>;
82 required-opps = <&rpmhpd_opp_svs>;
83 };
84
85 opp-1094400000 {
86 opp-hz = /bits/ 64 <1094400000>;
87 required-opps = <&rpmhpd_opp_nom>;
88 };
89
90 opp-1555200000 {
91 opp-hz = /bits/ 64 <1555200000>;
92 required-opps = <&rpmhpd_opp_turbo>;
93 };
94 };
95
96 psci {
97 compatible = "arm,psci-1.0";
98 method = "smc";
99 };
100
101 reserved-memory {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges;
105
106 hyp_mem: memory@8fc00000 {
107 no-map;
108 reg = <0x8fc00000 0x80000>;
109 };
110
111 ac_db_mem: memory@8fc80000 {
112 no-map;
113 reg = <0x8fc80000 0x40000>;
114 };
115
116 secdata_mem: memory@8fcfd000 {
117 no-map;
118 reg = <0x8fcfd000 0x1000>;
119 };
120
121 sbl_mem: memory@8fd00000 {
122 no-map;
123 reg = <0x8fd00000 0x100000>;
124 };
125
126 aop_image: memory@8fe00000 {
127 no-map;
128 reg = <0x8fe00000 0x20000>;
129 };
130
131 aop_cmd_db: memory@8fe20000 {
132 compatible = "qcom,cmd-db";
133 reg = <0x8fe20000 0x20000>;
134 no-map;
135 };
136
137 smem_mem: memory@8fe40000 {
138 no-map;
139 reg = <0x8fe40000 0xc0000>;
140 };
141
142 tz_mem: memory@8ff00000 {
143 no-map;
144 reg = <0x8ff00000 0x100000>;
145 };
146
147 tz_apps_mem: memory@90000000 {
148 no-map;
149 reg = <0x90000000 0x500000>;
150 };
151 };
152
153 smem {
154 compatible = "qcom,smem";
155 memory-region = <&smem_mem>;
156 hwlocks = <&tcsr_mutex 3>;
157 };
158
159 smp2p-mpss {
160 compatible = "qcom,smp2p";
161 qcom,smem = <435>, <428>;
162 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
163 mboxes = <&apcs 14>;
164 qcom,local-pid = <0>;
165 qcom,remote-pid = <1>;
166
167 modem_smp2p_out: master-kernel {
168 qcom,entry-name = "master-kernel";
169 #qcom,smem-state-cells = <1>;
170 };
171
172 modem_smp2p_in: slave-kernel {
173 qcom,entry-name = "slave-kernel";
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 };
177
178 ipa_smp2p_out: ipa-ap-to-modem {
179 qcom,entry-name = "ipa";
180 #qcom,smem-state-cells = <1>;
181 };
182
183 ipa_smp2p_in: ipa-modem-to-ap {
184 qcom,entry-name = "ipa";
185 interrupt-controller;
186 #interrupt-cells = <2>;
187 };
188 };
189
190 soc: soc {
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges;
194 compatible = "simple-bus";
195
196 gcc: clock-controller@100000 {
197 compatible = "qcom,gcc-sdx55";
198 reg = <0x100000 0x1f0000>;
199 #clock-cells = <1>;
200 #reset-cells = <1>;
201 #power-domain-cells = <1>;
202 clock-names = "bi_tcxo", "sleep_clk";
203 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
204 };
205
206 blsp1_uart3: serial@831000 {
207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
208 reg = <0x00831000 0x200>;
209 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&gcc 30>,
211 <&gcc 9>;
212 clock-names = "core", "iface";
213 status = "disabled";
214 };
215
216 usb_hsphy: phy@ff4000 {
217 compatible = "qcom,sdx55-usb-hs-phy",
218 "qcom,usb-snps-hs-7nm-phy";
219 reg = <0x00ff4000 0x114>;
220 status = "disabled";
221 #phy-cells = <0>;
222
223 clocks = <&rpmhcc RPMH_CXO_CLK>;
224 clock-names = "ref";
225
226 resets = <&gcc GCC_QUSB2PHY_BCR>;
227 };
228
229 usb_qmpphy: phy@ff6000 {
230 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
231 reg = <0x00ff6000 0x1000>;
232
233 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
234 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
235 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
236 <&gcc GCC_USB3_PHY_PIPE_CLK>;
237 clock-names = "aux",
238 "ref",
239 "cfg_ahb",
240 "pipe";
241 clock-output-names = "usb3_uni_phy_pipe_clk_src";
242 #clock-cells = <0>;
243 #phy-cells = <0>;
244
245 resets = <&gcc GCC_USB3_PHY_BCR>,
246 <&gcc GCC_USB3PHY_PHY_BCR>;
247 reset-names = "phy",
248 "phy_phy";
249
250 status = "disabled";
251 };
252
253 mc_virt: interconnect@1100000 {
254 compatible = "qcom,sdx55-mc-virt";
255 reg = <0x01100000 0x400000>;
256 #interconnect-cells = <1>;
257 qcom,bcm-voters = <&apps_bcm_voter>;
258 };
259
260 mem_noc: interconnect@9680000 {
261 compatible = "qcom,sdx55-mem-noc";
262 reg = <0x09680000 0x40000>;
263 #interconnect-cells = <1>;
264 qcom,bcm-voters = <&apps_bcm_voter>;
265 };
266
267 system_noc: interconnect@162c000 {
268 compatible = "qcom,sdx55-system-noc";
269 reg = <0x0162c000 0x31200>;
270 #interconnect-cells = <1>;
271 qcom,bcm-voters = <&apps_bcm_voter>;
272 };
273
274 qpic_bam: dma-controller@1b04000 {
275 compatible = "qcom,bam-v1.7.0";
276 reg = <0x01b04000 0x1c000>;
277 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&rpmhcc RPMH_QPIC_CLK>;
279 clock-names = "bam_clk";
280 #dma-cells = <1>;
281 qcom,ee = <0>;
282 qcom,controlled-remotely;
283 status = "disabled";
284 };
285
286 qpic_nand: nand-controller@1b30000 {
287 compatible = "qcom,sdx55-nand";
288 reg = <0x01b30000 0x10000>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 clocks = <&rpmhcc RPMH_QPIC_CLK>,
292 <&nand_clk_dummy>;
293 clock-names = "core", "aon";
294
295 dmas = <&qpic_bam 0>,
296 <&qpic_bam 1>,
297 <&qpic_bam 2>;
298 dma-names = "tx", "rx", "cmd";
299 status = "disabled";
300 };
301
302 pcie_rc: pcie@1c00000 {
303 compatible = "qcom,pcie-sdx55";
304 reg = <0x01c00000 0x3000>,
305 <0x40000000 0xf1d>,
306 <0x40000f20 0xc8>,
307 <0x40001000 0x1000>,
308 <0x40100000 0x100000>;
309 reg-names = "parf",
310 "dbi",
311 "elbi",
312 "atu",
313 "config";
314 device_type = "pci";
315 linux,pci-domain = <0>;
316 bus-range = <0x00 0xff>;
317 num-lanes = <1>;
318
319 #address-cells = <3>;
320 #size-cells = <2>;
321
322 ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
323 <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
324
325 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
333 interrupt-names = "msi",
334 "msi2",
335 "msi3",
336 "msi4",
337 "msi5",
338 "msi6",
339 "msi7",
340 "msi8";
341 #interrupt-cells = <1>;
342 interrupt-map-mask = <0 0 0 0x7>;
343 interrupt-map = <0 0 0 1 &intc 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
344 <0 0 0 2 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
345 <0 0 0 3 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
346 <0 0 0 4 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
347
348 clocks = <&gcc GCC_PCIE_PIPE_CLK>,
349 <&gcc GCC_PCIE_AUX_CLK>,
350 <&gcc GCC_PCIE_CFG_AHB_CLK>,
351 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
352 <&gcc GCC_PCIE_SLV_AXI_CLK>,
353 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
354 <&gcc GCC_PCIE_SLEEP_CLK>;
355 clock-names = "pipe",
356 "aux",
357 "cfg",
358 "bus_master",
359 "bus_slave",
360 "slave_q2a",
361 "sleep";
362
363 assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
364 assigned-clock-rates = <19200000>;
365
366 iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
367 <0x100 &apps_smmu 0x0201 0x1>,
368 <0x200 &apps_smmu 0x0202 0x1>,
369 <0x300 &apps_smmu 0x0203 0x1>,
370 <0x400 &apps_smmu 0x0204 0x1>;
371
372 resets = <&gcc GCC_PCIE_BCR>;
373 reset-names = "pci";
374
375 power-domains = <&gcc PCIE_GDSC>;
376
377 phys = <&pcie_phy>;
378 phy-names = "pciephy";
379
380 status = "disabled";
381
382 pcie@0 {
383 device_type = "pci";
384 reg = <0x0 0x0 0x0 0x0 0x0>;
385 bus-range = <0x01 0xff>;
386
387 #address-cells = <3>;
388 #size-cells = <2>;
389 ranges;
390 };
391 };
392
393 pcie_ep: pcie-ep@1c00000 {
394 compatible = "qcom,sdx55-pcie-ep";
395 reg = <0x01c00000 0x3000>,
396 <0x40000000 0xf1d>,
397 <0x40000f20 0xc8>,
398 <0x40001000 0x1000>,
399 <0x40200000 0x100000>,
400 <0x01c03000 0x3000>;
401 reg-names = "parf",
402 "dbi",
403 "elbi",
404 "atu",
405 "addr_space",
406 "mmio";
407
408 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
409
410 clocks = <&gcc GCC_PCIE_AUX_CLK>,
411 <&gcc GCC_PCIE_CFG_AHB_CLK>,
412 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
413 <&gcc GCC_PCIE_SLV_AXI_CLK>,
414 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
415 <&gcc GCC_PCIE_SLEEP_CLK>,
416 <&gcc GCC_PCIE_0_CLKREF_CLK>;
417 clock-names = "aux",
418 "cfg",
419 "bus_master",
420 "bus_slave",
421 "slave_q2a",
422 "sleep",
423 "ref";
424
425 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "global",
428 "doorbell";
429
430 interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
431 interconnect-names = "pcie-mem";
432
433 resets = <&gcc GCC_PCIE_BCR>;
434 reset-names = "core";
435 power-domains = <&gcc PCIE_GDSC>;
436 phys = <&pcie_phy>;
437 phy-names = "pciephy";
438 max-link-speed = <3>;
439 num-lanes = <2>;
440
441 status = "disabled";
442 };
443
444 pcie_phy: phy@1c06000 {
445 compatible = "qcom,sdx55-qmp-pcie-phy";
446 reg = <0x01c06000 0x2000>;
447 #address-cells = <1>;
448 #size-cells = <1>;
449 ranges;
450 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
451 <&gcc GCC_PCIE_CFG_AHB_CLK>,
452 <&gcc GCC_PCIE_0_CLKREF_CLK>,
453 <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
454 <&gcc GCC_PCIE_PIPE_CLK>;
455 clock-names = "aux",
456 "cfg_ahb",
457 "ref",
458 "refgen",
459 "pipe";
460
461 clock-output-names = "pcie_pipe_clk";
462 #clock-cells = <0>;
463
464 #phy-cells = <0>;
465
466 resets = <&gcc GCC_PCIE_PHY_BCR>;
467 reset-names = "phy";
468
469 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
470 assigned-clock-rates = <100000000>;
471
472 status = "disabled";
473 };
474
475 ipa: ipa@1e40000 {
476 compatible = "qcom,sdx55-ipa";
477
478 iommus = <&apps_smmu 0x5e0 0x0>,
479 <&apps_smmu 0x5e2 0x0>;
480 reg = <0x1e40000 0x7000>,
481 <0x1e50000 0x4b20>,
482 <0x1e04000 0x2c000>;
483 reg-names = "ipa-reg",
484 "ipa-shared",
485 "gsi";
486
487 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
488 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
489 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
490 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
491 interrupt-names = "ipa",
492 "gsi",
493 "ipa-clock-query",
494 "ipa-setup-ready";
495
496 clocks = <&rpmhcc RPMH_IPA_CLK>;
497 clock-names = "core";
498
499 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>,
500 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
501 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>;
502 interconnect-names = "memory",
503 "imem",
504 "config";
505
506 qcom,smem-states = <&ipa_smp2p_out 0>,
507 <&ipa_smp2p_out 1>;
508 qcom,smem-state-names = "ipa-clock-enabled-valid",
509 "ipa-clock-enabled";
510
511 status = "disabled";
512 };
513
514 tcsr_mutex: hwlock@1f40000 {
515 compatible = "qcom,tcsr-mutex";
516 reg = <0x01f40000 0x40000>;
517 #hwlock-cells = <1>;
518 };
519
520 tcsr: syscon@1fc0000 {
521 compatible = "qcom,sdx55-tcsr", "syscon";
522 reg = <0x01fc0000 0x1000>;
523 };
524
525 sdhc_1: mmc@8804000 {
526 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
527 reg = <0x08804000 0x1000>;
528 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
530 interrupt-names = "hc_irq", "pwr_irq";
531 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
532 <&gcc GCC_SDCC1_APPS_CLK>;
533 clock-names = "iface", "core";
534 status = "disabled";
535 };
536
537 remoteproc_mpss: remoteproc@4080000 {
538 compatible = "qcom,sdx55-mpss-pas";
539 reg = <0x04080000 0x4040>;
540
541 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
542 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
543 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
544 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
545 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
546 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
547 interrupt-names = "wdog", "fatal", "ready", "handover",
548 "stop-ack", "shutdown-ack";
549
550 clocks = <&rpmhcc RPMH_CXO_CLK>;
551 clock-names = "xo";
552
553 power-domains = <&rpmhpd SDX55_CX>,
554 <&rpmhpd SDX55_MSS>;
555 power-domain-names = "cx", "mss";
556
557 qcom,smem-states = <&modem_smp2p_out 0>;
558 qcom,smem-state-names = "stop";
559
560 status = "disabled";
561
562 glink-edge {
563 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
564 label = "mpss";
565 qcom,remote-pid = <1>;
566 mboxes = <&apcs 15>;
567 };
568 };
569
570 usb: usb@a6f8800 {
571 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
572 reg = <0x0a6f8800 0x400>;
573 status = "disabled";
574 #address-cells = <1>;
575 #size-cells = <1>;
576 ranges;
577
578 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
579 <&gcc GCC_USB30_MASTER_CLK>,
580 <&gcc GCC_USB30_MSTR_AXI_CLK>,
581 <&gcc GCC_USB30_SLEEP_CLK>,
582 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
583 clock-names = "cfg_noc",
584 "core",
585 "iface",
586 "sleep",
587 "mock_utmi";
588
589 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
590 <&gcc GCC_USB30_MASTER_CLK>;
591 assigned-clock-rates = <19200000>, <200000000>;
592
593 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
594 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
595 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
596 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
597 <&pdc 51 IRQ_TYPE_LEVEL_HIGH>;
598 interrupt-names = "pwr_event",
599 "hs_phy_irq",
600 "dp_hs_phy_irq",
601 "dm_hs_phy_irq",
602 "ss_phy_irq";
603
604 power-domains = <&gcc USB30_GDSC>;
605
606 resets = <&gcc GCC_USB30_BCR>;
607
608 usb_dwc3: usb@a600000 {
609 compatible = "snps,dwc3";
610 reg = <0x0a600000 0xcd00>;
611 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
612 iommus = <&apps_smmu 0x1a0 0x0>;
613 snps,dis_u2_susphy_quirk;
614 snps,dis_enblslpm_quirk;
615 phys = <&usb_hsphy>, <&usb_qmpphy>;
616 phy-names = "usb2-phy", "usb3-phy";
617 };
618 };
619
620 pdc: interrupt-controller@b210000 {
621 compatible = "qcom,sdx55-pdc", "qcom,pdc";
622 reg = <0x0b210000 0x30000>;
623 qcom,pdc-ranges = <0 179 52>;
624 #interrupt-cells = <2>;
625 interrupt-parent = <&intc>;
626 interrupt-controller;
627 };
628
629 restart@c264000 {
630 compatible = "qcom,pshold";
631 reg = <0x0c264000 0x1000>;
632 };
633
634 spmi_bus: spmi@c440000 {
635 compatible = "qcom,spmi-pmic-arb";
636 reg = <0x0c440000 0x0000d00>,
637 <0x0c600000 0x2000000>,
638 <0x0e600000 0x0100000>,
639 <0x0e700000 0x00a0000>,
640 <0x0c40a000 0x0000700>;
641 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
642 interrupt-names = "periph_irq";
643 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
644 qcom,ee = <0>;
645 qcom,channel = <0>;
646 #address-cells = <2>;
647 #size-cells = <0>;
648 interrupt-controller;
649 #interrupt-cells = <4>;
650 };
651
652 tlmm: pinctrl@f100000 {
653 compatible = "qcom,sdx55-pinctrl";
654 reg = <0xf100000 0x300000>;
655 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
656 gpio-controller;
657 #gpio-cells = <2>;
658 interrupt-controller;
659 #interrupt-cells = <2>;
660 gpio-ranges = <&tlmm 0 0 108>;
661 };
662
663 sram@1468f000 {
664 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
665 reg = <0x1468f000 0x1000>;
666
667 #address-cells = <1>;
668 #size-cells = <1>;
669
670 ranges = <0x0 0x1468f000 0x1000>;
671
672 pil-reloc@94c {
673 compatible = "qcom,pil-reloc-info";
674 reg = <0x94c 0x200>;
675 };
676 };
677
678 apps_smmu: iommu@15000000 {
679 compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500";
680 reg = <0x15000000 0x20000>;
681 #iommu-cells = <2>;
682 #global-interrupts = <1>;
683 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
700 };
701
702 intc: interrupt-controller@17800000 {
703 compatible = "qcom,msm-qgic2";
704 interrupt-controller;
705 interrupt-parent = <&intc>;
706 #interrupt-cells = <3>;
707 reg = <0x17800000 0x1000>,
708 <0x17802000 0x1000>;
709 };
710
711 a7pll: clock@17808000 {
712 compatible = "qcom,sdx55-a7pll";
713 reg = <0x17808000 0x1000>;
714 clocks = <&rpmhcc RPMH_CXO_CLK>;
715 clock-names = "bi_tcxo";
716 #clock-cells = <0>;
717 };
718
719 apcs: mailbox@17810000 {
720 compatible = "qcom,sdx55-apcs-gcc", "syscon";
721 reg = <0x17810000 0x2000>;
722 #mbox-cells = <1>;
723 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
724 clock-names = "ref", "pll", "aux";
725 #clock-cells = <0>;
726 };
727
728 watchdog@17817000 {
729 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
730 reg = <0x17817000 0x1000>;
731 clocks = <&sleep_clk>;
732 };
733
734 timer@17820000 {
735 #address-cells = <1>;
736 #size-cells = <1>;
737 ranges;
738 compatible = "arm,armv7-timer-mem";
739 reg = <0x17820000 0x1000>;
740 clock-frequency = <19200000>;
741
742 frame@17821000 {
743 frame-number = <0>;
744 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
746 reg = <0x17821000 0x1000>,
747 <0x17822000 0x1000>;
748 };
749
750 frame@17823000 {
751 frame-number = <1>;
752 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
753 reg = <0x17823000 0x1000>;
754 status = "disabled";
755 };
756
757 frame@17824000 {
758 frame-number = <2>;
759 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
760 reg = <0x17824000 0x1000>;
761 status = "disabled";
762 };
763
764 frame@17825000 {
765 frame-number = <3>;
766 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
767 reg = <0x17825000 0x1000>;
768 status = "disabled";
769 };
770
771 frame@17826000 {
772 frame-number = <4>;
773 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
774 reg = <0x17826000 0x1000>;
775 status = "disabled";
776 };
777
778 frame@17827000 {
779 frame-number = <5>;
780 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
781 reg = <0x17827000 0x1000>;
782 status = "disabled";
783 };
784
785 frame@17828000 {
786 frame-number = <6>;
787 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
788 reg = <0x17828000 0x1000>;
789 status = "disabled";
790 };
791
792 frame@17829000 {
793 frame-number = <7>;
794 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
795 reg = <0x17829000 0x1000>;
796 status = "disabled";
797 };
798 };
799
800 apps_rsc: rsc@17830000 {
801 compatible = "qcom,rpmh-rsc";
802 reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
803 reg-names = "drv-0", "drv-1";
804 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
806 qcom,tcs-offset = <0xd00>;
807 qcom,drv-id = <1>;
808 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
809 <WAKE_TCS 2>, <CONTROL_TCS 1>;
810
811 rpmhcc: clock-controller {
812 compatible = "qcom,sdx55-rpmh-clk";
813 #clock-cells = <1>;
814 clock-names = "xo";
815 clocks = <&xo_board>;
816 };
817
818 rpmhpd: power-controller {
819 compatible = "qcom,sdx55-rpmhpd";
820 #power-domain-cells = <1>;
821 operating-points-v2 = <&rpmhpd_opp_table>;
822
823 rpmhpd_opp_table: opp-table {
824 compatible = "operating-points-v2";
825
826 rpmhpd_opp_ret: opp1 {
827 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
828 };
829
830 rpmhpd_opp_min_svs: opp2 {
831 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
832 };
833
834 rpmhpd_opp_low_svs: opp3 {
835 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
836 };
837
838 rpmhpd_opp_svs: opp4 {
839 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
840 };
841
842 rpmhpd_opp_svs_l1: opp5 {
843 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
844 };
845
846 rpmhpd_opp_nom: opp6 {
847 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
848 };
849
850 rpmhpd_opp_nom_l1: opp7 {
851 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
852 };
853
854 rpmhpd_opp_nom_l2: opp8 {
855 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
856 };
857
858 rpmhpd_opp_turbo: opp9 {
859 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
860 };
861
862 rpmhpd_opp_turbo_l1: opp10 {
863 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
864 };
865 };
866 };
867
868 apps_bcm_voter: bcm-voter {
869 compatible = "qcom,bcm-voter";
870 };
871 };
872 };
873
874 timer {
875 compatible = "arm,armv7-timer";
876 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
877 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
878 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
879 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
880 clock-frequency = <19200000>;
881 };
882 };
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