1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2 /*
3 * Copyright (c) 2017-2019 Andreas Färber
4 */
5
6 /memreserve/ 0x00000000 0x0000a800; /* boot code */
7 /memreserve/ 0x0000a800 0x000f5800;
8 /memreserve/ 0x17fff000 0x00001000;
9
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
12
13 / {
14 compatible = "realtek,rtd1195";
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu0: cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a7";
26 reg = <0x0>;
27 clock-frequency = <1000000000>;
28 };
29
30 cpu1: cpu@1 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a7";
33 reg = <0x1>;
34 clock-frequency = <1000000000>;
35 };
36 };
37
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges;
42
43 rpc_comm: rpc@b000 {
44 reg = <0x0000b000 0x1000>;
45 };
46
47 audio@1b00000 {
48 reg = <0x01b00000 0x400000>;
49 };
50
51 rpc_ringbuf: rpc@1ffe000 {
52 reg = <0x01ffe000 0x4000>;
53 };
54
55 secure@10000000 {
56 reg = <0x10000000 0x100000>;
57 no-map;
58 };
59 };
60
61 arm-pmu {
62 compatible = "arm,cortex-a7-pmu";
63 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
65 interrupt-affinity = <&cpu0>, <&cpu1>;
66 };
67
68 timer {
69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13
71 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 14
73 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 11
75 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 10
77 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <27000000>;
79 };
80
81 osc27M: osc {
82 compatible = "fixed-clock";
83 clock-frequency = <27000000>;
84 #clock-cells = <0>;
85 clock-output-names = "osc27M";
86 };
87
88 soc {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges = <0x00000000 0x00000000 0x0000a800>,
93 <0x18000000 0x18000000 0x00070000>,
94 <0x18100000 0x18100000 0x01000000>,
95 <0x80000000 0x80000000 0x80000000>;
96
97 rbus: bus@18000000 {
98 compatible = "simple-bus";
99 reg = <0x18000000 0x70000>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0x0 0x18000000 0x70000>;
103
104 crt: syscon@0 {
105 compatible = "syscon", "simple-mfd";
106 reg = <0x0 0x1000>;
107 reg-io-width = <4>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0x0 0x0 0x1000>;
111 };
112
113 iso: syscon@7000 {
114 compatible = "syscon", "simple-mfd";
115 reg = <0x7000 0x1000>;
116 reg-io-width = <4>;
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges = <0x0 0x7000 0x1000>;
120 };
121
122 sb2: syscon@1a000 {
123 compatible = "syscon", "simple-mfd";
124 reg = <0x1a000 0x1000>;
125 reg-io-width = <4>;
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges = <0x0 0x1a000 0x1000>;
129 };
130
131 misc: syscon@1b000 {
132 compatible = "syscon", "simple-mfd";
133 reg = <0x1b000 0x1000>;
134 reg-io-width = <4>;
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges = <0x0 0x1b000 0x1000>;
138 };
139
140 scpu_wrapper: syscon@1d000 {
141 compatible = "syscon", "simple-mfd";
142 reg = <0x1d000 0x1000>;
143 reg-io-width = <4>;
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0x0 0x1d000 0x1000>;
147 };
148 };
149
150 gic: interrupt-controller@ff011000 {
151 compatible = "arm,cortex-a7-gic";
152 reg = <0xff011000 0x1000>,
153 <0xff012000 0x2000>,
154 <0xff014000 0x2000>,
155 <0xff016000 0x2000>;
156 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
157 interrupt-controller;
158 #interrupt-cells = <3>;
159 };
160 };
161 };
162
163 &crt {
164 reset1: reset-controller@0 {
165 compatible = "snps,dw-low-reset";
166 reg = <0x0 0x4>;
167 #reset-cells = <1>;
168 };
169
170 reset2: reset-controller@4 {
171 compatible = "snps,dw-low-reset";
172 reg = <0x4 0x4>;
173 #reset-cells = <1>;
174 };
175
176 reset3: reset-controller@8 {
177 compatible = "snps,dw-low-reset";
178 reg = <0x8 0x4>;
179 #reset-cells = <1>;
180 };
181 };
182
183 &iso {
184 iso_reset: reset-controller@88 {
185 compatible = "snps,dw-low-reset";
186 reg = <0x88 0x4>;
187 #reset-cells = <1>;
188 };
189
190 wdt: watchdog@680 {
191 compatible = "realtek,rtd1295-watchdog";
192 reg = <0x680 0x100>;
193 clocks = <&osc27M>;
194 };
195
196 uart0: serial@800 {
197 compatible = "snps,dw-apb-uart";
198 reg = <0x800 0x400>;
199 reg-shift = <2>;
200 reg-io-width = <4>;
201 resets = <&iso_reset RTD1195_ISO_RSTN_UR0>;
202 clock-frequency = <27000000>;
203 status = "disabled";
204 };
205 };
206
207 &misc {
208 uart1: serial@200 {
209 compatible = "snps,dw-apb-uart";
210 reg = <0x200 0x100>;
211 reg-shift = <2>;
212 reg-io-width = <4>;
213 resets = <&reset2 RTD1195_RSTN_UR1>;
214 clock-frequency = <27000000>;
215 status = "disabled";
216 };
217 };
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