1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC
4 *
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
6 */
7
8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7793-sysc.h>
12
13 / {
14 compatible = "renesas,r8a7793";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 i2c4 = &i2c4;
24 i2c5 = &i2c5;
25 i2c6 = &i2c6;
26 i2c7 = &i2c7;
27 i2c8 = &i2c8;
28 spi0 = &qspi;
29 };
30
31 /*
32 * The external audio clocks are configured as 0 Hz fixed frequency
33 * clocks by default.
34 * Boards that provide audio clocks should override them.
35 */
36 audio_clk_a: audio_clk_a {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <0>;
40 };
41 audio_clk_b: audio_clk_b {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 };
46 audio_clk_c: audio_clk_c {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <0>;
50 };
51
52 /* External CAN clock */
53 can_clk: can {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 /* This value must be overridden by the board. */
57 clock-frequency = <0>;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 cpu0: cpu@0 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <0>;
68 clock-frequency = <1500000000>;
69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
70 power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
71 enable-method = "renesas,apmu";
72 voltage-tolerance = <1>; /* 1% */
73 clock-latency = <300000>; /* 300 us */
74
75 /* kHz - uV - OPPs unknown yet */
76 operating-points = <1500000 1000000>,
77 <1312500 1000000>,
78 <1125000 1000000>,
79 < 937500 1000000>,
80 < 750000 1000000>,
81 < 375000 1000000>;
82 next-level-cache = <&L2_CA15>;
83 };
84
85 cpu1: cpu@1 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a15";
88 reg = <1>;
89 clock-frequency = <1500000000>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
91 power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
92 enable-method = "renesas,apmu";
93 voltage-tolerance = <1>; /* 1% */
94 clock-latency = <300000>; /* 300 us */
95
96 /* kHz - uV - OPPs unknown yet */
97 operating-points = <1500000 1000000>,
98 <1312500 1000000>,
99 <1125000 1000000>,
100 < 937500 1000000>,
101 < 750000 1000000>,
102 < 375000 1000000>;
103 next-level-cache = <&L2_CA15>;
104 };
105
106 L2_CA15: cache-controller-0 {
107 compatible = "cache";
108 power-domains = <&sysc R8A7793_PD_CA15_SCU>;
109 cache-unified;
110 cache-level = <2>;
111 };
112 };
113
114 /* External root clock */
115 extal_clk: extal {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 /* This value must be overridden by the board. */
119 clock-frequency = <0>;
120 };
121
122 pmu {
123 compatible = "arm,cortex-a15-pmu";
124 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
125 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
126 interrupt-affinity = <&cpu0>, <&cpu1>;
127 };
128
129 /* External SCIF clock */
130 scif_clk: scif {
131 compatible = "fixed-clock";
132 #clock-cells = <0>;
133 /* This value must be overridden by the board. */
134 clock-frequency = <0>;
135 };
136
137 soc {
138 compatible = "simple-bus";
139 interrupt-parent = <&gic>;
140
141 #address-cells = <2>;
142 #size-cells = <2>;
143 ranges;
144
145 rwdt: watchdog@e6020000 {
146 compatible = "renesas,r8a7793-wdt",
147 "renesas,rcar-gen2-wdt";
148 reg = <0 0xe6020000 0 0x0c>;
149 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&cpg CPG_MOD 402>;
151 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
152 resets = <&cpg 402>;
153 status = "disabled";
154 };
155
156 gpio0: gpio@e6050000 {
157 compatible = "renesas,gpio-r8a7793",
158 "renesas,rcar-gen2-gpio";
159 reg = <0 0xe6050000 0 0x50>;
160 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
161 #gpio-cells = <2>;
162 gpio-controller;
163 gpio-ranges = <&pfc 0 0 32>;
164 #interrupt-cells = <2>;
165 interrupt-controller;
166 clocks = <&cpg CPG_MOD 912>;
167 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
168 resets = <&cpg 912>;
169 };
170
171 gpio1: gpio@e6051000 {
172 compatible = "renesas,gpio-r8a7793",
173 "renesas,rcar-gen2-gpio";
174 reg = <0 0xe6051000 0 0x50>;
175 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
176 #gpio-cells = <2>;
177 gpio-controller;
178 gpio-ranges = <&pfc 0 32 26>;
179 #interrupt-cells = <2>;
180 interrupt-controller;
181 clocks = <&cpg CPG_MOD 911>;
182 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
183 resets = <&cpg 911>;
184 };
185
186 gpio2: gpio@e6052000 {
187 compatible = "renesas,gpio-r8a7793",
188 "renesas,rcar-gen2-gpio";
189 reg = <0 0xe6052000 0 0x50>;
190 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
191 #gpio-cells = <2>;
192 gpio-controller;
193 gpio-ranges = <&pfc 0 64 32>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 clocks = <&cpg CPG_MOD 910>;
197 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
198 resets = <&cpg 910>;
199 };
200
201 gpio3: gpio@e6053000 {
202 compatible = "renesas,gpio-r8a7793",
203 "renesas,rcar-gen2-gpio";
204 reg = <0 0xe6053000 0 0x50>;
205 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
206 #gpio-cells = <2>;
207 gpio-controller;
208 gpio-ranges = <&pfc 0 96 32>;
209 #interrupt-cells = <2>;
210 interrupt-controller;
211 clocks = <&cpg CPG_MOD 909>;
212 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
213 resets = <&cpg 909>;
214 };
215
216 gpio4: gpio@e6054000 {
217 compatible = "renesas,gpio-r8a7793",
218 "renesas,rcar-gen2-gpio";
219 reg = <0 0xe6054000 0 0x50>;
220 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
221 #gpio-cells = <2>;
222 gpio-controller;
223 gpio-ranges = <&pfc 0 128 32>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
226 clocks = <&cpg CPG_MOD 908>;
227 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
228 resets = <&cpg 908>;
229 };
230
231 gpio5: gpio@e6055000 {
232 compatible = "renesas,gpio-r8a7793",
233 "renesas,rcar-gen2-gpio";
234 reg = <0 0xe6055000 0 0x50>;
235 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
236 #gpio-cells = <2>;
237 gpio-controller;
238 gpio-ranges = <&pfc 0 160 32>;
239 #interrupt-cells = <2>;
240 interrupt-controller;
241 clocks = <&cpg CPG_MOD 907>;
242 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
243 resets = <&cpg 907>;
244 };
245
246 gpio6: gpio@e6055400 {
247 compatible = "renesas,gpio-r8a7793",
248 "renesas,rcar-gen2-gpio";
249 reg = <0 0xe6055400 0 0x50>;
250 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
251 #gpio-cells = <2>;
252 gpio-controller;
253 gpio-ranges = <&pfc 0 192 32>;
254 #interrupt-cells = <2>;
255 interrupt-controller;
256 clocks = <&cpg CPG_MOD 905>;
257 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
258 resets = <&cpg 905>;
259 };
260
261 gpio7: gpio@e6055800 {
262 compatible = "renesas,gpio-r8a7793",
263 "renesas,rcar-gen2-gpio";
264 reg = <0 0xe6055800 0 0x50>;
265 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
266 #gpio-cells = <2>;
267 gpio-controller;
268 gpio-ranges = <&pfc 0 224 26>;
269 #interrupt-cells = <2>;
270 interrupt-controller;
271 clocks = <&cpg CPG_MOD 904>;
272 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
273 resets = <&cpg 904>;
274 };
275
276 pfc: pinctrl@e6060000 {
277 compatible = "renesas,pfc-r8a7793";
278 reg = <0 0xe6060000 0 0x250>;
279 };
280
281 /* Special CPG clocks */
282 cpg: clock-controller@e6150000 {
283 compatible = "renesas,r8a7793-cpg-mssr";
284 reg = <0 0xe6150000 0 0x1000>;
285 clocks = <&extal_clk>, <&usb_extal_clk>;
286 clock-names = "extal", "usb_extal";
287 #clock-cells = <2>;
288 #power-domain-cells = <0>;
289 #reset-cells = <1>;
290 };
291
292 apmu@e6152000 {
293 compatible = "renesas,r8a7793-apmu", "renesas,apmu";
294 reg = <0 0xe6152000 0 0x188>;
295 cpus = <&cpu0>, <&cpu1>;
296 };
297
298 rst: reset-controller@e6160000 {
299 compatible = "renesas,r8a7793-rst";
300 reg = <0 0xe6160000 0 0x0100>;
301 };
302
303 sysc: system-controller@e6180000 {
304 compatible = "renesas,r8a7793-sysc";
305 reg = <0 0xe6180000 0 0x0200>;
306 #power-domain-cells = <1>;
307 };
308
309 irqc0: interrupt-controller@e61c0000 {
310 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
311 #interrupt-cells = <2>;
312 interrupt-controller;
313 reg = <0 0xe61c0000 0 0x200>;
314 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&cpg CPG_MOD 407>;
325 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
326 resets = <&cpg 407>;
327 };
328
329 tmu0: timer@e61e0000 {
330 compatible = "renesas,tmu-r8a7793", "renesas,tmu";
331 reg = <0 0xe61e0000 0 0x30>;
332 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
335 interrupt-names = "tuni0", "tuni1", "tuni2";
336 clocks = <&cpg CPG_MOD 125>;
337 clock-names = "fck";
338 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
339 resets = <&cpg 125>;
340 status = "disabled";
341 };
342
343 tmu1: timer@fff60000 {
344 compatible = "renesas,tmu-r8a7793", "renesas,tmu";
345 reg = <0 0xfff60000 0 0x30>;
346 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
351 clocks = <&cpg CPG_MOD 111>;
352 clock-names = "fck";
353 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
354 resets = <&cpg 111>;
355 status = "disabled";
356 };
357
358 tmu2: timer@fff70000 {
359 compatible = "renesas,tmu-r8a7793", "renesas,tmu";
360 reg = <0 0xfff70000 0 0x30>;
361 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
366 clocks = <&cpg CPG_MOD 122>;
367 clock-names = "fck";
368 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
369 resets = <&cpg 122>;
370 status = "disabled";
371 };
372
373 tmu3: timer@fff80000 {
374 compatible = "renesas,tmu-r8a7793", "renesas,tmu";
375 reg = <0 0xfff80000 0 0x30>;
376 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-names = "tuni0", "tuni1", "tuni2";
380 clocks = <&cpg CPG_MOD 121>;
381 clock-names = "fck";
382 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
383 resets = <&cpg 121>;
384 status = "disabled";
385 };
386
387 thermal: thermal@e61f0000 {
388 compatible = "renesas,thermal-r8a7793",
389 "renesas,rcar-gen2-thermal",
390 "renesas,rcar-thermal";
391 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
392 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cpg CPG_MOD 522>;
394 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
395 resets = <&cpg 522>;
396 #thermal-sensor-cells = <0>;
397 };
398
399 ipmmu_sy0: iommu@e6280000 {
400 compatible = "renesas,ipmmu-r8a7793",
401 "renesas,ipmmu-vmsa";
402 reg = <0 0xe6280000 0 0x1000>;
403 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
405 #iommu-cells = <1>;
406 status = "disabled";
407 };
408
409 ipmmu_sy1: iommu@e6290000 {
410 compatible = "renesas,ipmmu-r8a7793",
411 "renesas,ipmmu-vmsa";
412 reg = <0 0xe6290000 0 0x1000>;
413 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
414 #iommu-cells = <1>;
415 status = "disabled";
416 };
417
418 ipmmu_ds: iommu@e6740000 {
419 compatible = "renesas,ipmmu-r8a7793",
420 "renesas,ipmmu-vmsa";
421 reg = <0 0xe6740000 0 0x1000>;
422 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
424 #iommu-cells = <1>;
425 status = "disabled";
426 };
427
428 ipmmu_mp: iommu@ec680000 {
429 compatible = "renesas,ipmmu-r8a7793",
430 "renesas,ipmmu-vmsa";
431 reg = <0 0xec680000 0 0x1000>;
432 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
433 #iommu-cells = <1>;
434 status = "disabled";
435 };
436
437 ipmmu_mx: iommu@fe951000 {
438 compatible = "renesas,ipmmu-r8a7793",
439 "renesas,ipmmu-vmsa";
440 reg = <0 0xfe951000 0 0x1000>;
441 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
443 #iommu-cells = <1>;
444 status = "disabled";
445 };
446
447 ipmmu_rt: iommu@ffc80000 {
448 compatible = "renesas,ipmmu-r8a7793",
449 "renesas,ipmmu-vmsa";
450 reg = <0 0xffc80000 0 0x1000>;
451 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
452 #iommu-cells = <1>;
453 status = "disabled";
454 };
455
456 ipmmu_gp: iommu@e62a0000 {
457 compatible = "renesas,ipmmu-r8a7793",
458 "renesas,ipmmu-vmsa";
459 reg = <0 0xe62a0000 0 0x1000>;
460 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
462 #iommu-cells = <1>;
463 status = "disabled";
464 };
465
466 icram0: sram@e63a0000 {
467 compatible = "mmio-sram";
468 reg = <0 0xe63a0000 0 0x12000>;
469 #address-cells = <1>;
470 #size-cells = <1>;
471 ranges = <0 0 0xe63a0000 0x12000>;
472 };
473
474 icram1: sram@e63c0000 {
475 compatible = "mmio-sram";
476 reg = <0 0xe63c0000 0 0x1000>;
477 #address-cells = <1>;
478 #size-cells = <1>;
479 ranges = <0 0 0xe63c0000 0x1000>;
480
481 smp-sram@0 {
482 compatible = "renesas,smp-sram";
483 reg = <0 0x100>;
484 };
485 };
486
487 /* The memory map in the User's Manual maps the cores to
488 * bus numbers
489 */
490 i2c0: i2c@e6508000 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 compatible = "renesas,i2c-r8a7793",
494 "renesas,rcar-gen2-i2c";
495 reg = <0 0xe6508000 0 0x40>;
496 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cpg CPG_MOD 931>;
498 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
499 resets = <&cpg 931>;
500 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled";
502 };
503
504 i2c1: i2c@e6518000 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a7793",
508 "renesas,rcar-gen2-i2c";
509 reg = <0 0xe6518000 0 0x40>;
510 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 930>;
512 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
513 resets = <&cpg 930>;
514 i2c-scl-internal-delay-ns = <6>;
515 status = "disabled";
516 };
517
518 i2c2: i2c@e6530000 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "renesas,i2c-r8a7793",
522 "renesas,rcar-gen2-i2c";
523 reg = <0 0xe6530000 0 0x40>;
524 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 929>;
526 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
527 resets = <&cpg 929>;
528 i2c-scl-internal-delay-ns = <6>;
529 status = "disabled";
530 };
531
532 i2c3: i2c@e6540000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,i2c-r8a7793",
536 "renesas,rcar-gen2-i2c";
537 reg = <0 0xe6540000 0 0x40>;
538 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&cpg CPG_MOD 928>;
540 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
541 resets = <&cpg 928>;
542 i2c-scl-internal-delay-ns = <6>;
543 status = "disabled";
544 };
545
546 i2c4: i2c@e6520000 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 compatible = "renesas,i2c-r8a7793",
550 "renesas,rcar-gen2-i2c";
551 reg = <0 0xe6520000 0 0x40>;
552 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 927>;
554 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
555 resets = <&cpg 927>;
556 i2c-scl-internal-delay-ns = <6>;
557 status = "disabled";
558 };
559
560 i2c5: i2c@e6528000 {
561 /* doesn't need pinmux */
562 #address-cells = <1>;
563 #size-cells = <0>;
564 compatible = "renesas,i2c-r8a7793",
565 "renesas,rcar-gen2-i2c";
566 reg = <0 0xe6528000 0 0x40>;
567 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cpg CPG_MOD 925>;
569 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
570 resets = <&cpg 925>;
571 i2c-scl-internal-delay-ns = <110>;
572 status = "disabled";
573 };
574
575 i2c6: i2c@e60b0000 {
576 /* doesn't need pinmux */
577 #address-cells = <1>;
578 #size-cells = <0>;
579 compatible = "renesas,iic-r8a7793",
580 "renesas,rcar-gen2-iic",
581 "renesas,rmobile-iic";
582 reg = <0 0xe60b0000 0 0x425>;
583 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cpg CPG_MOD 926>;
585 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
586 <&dmac1 0x77>, <&dmac1 0x78>;
587 dma-names = "tx", "rx", "tx", "rx";
588 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
589 resets = <&cpg 926>;
590 status = "disabled";
591 };
592
593 i2c7: i2c@e6500000 {
594 #address-cells = <1>;
595 #size-cells = <0>;
596 compatible = "renesas,iic-r8a7793",
597 "renesas,rcar-gen2-iic",
598 "renesas,rmobile-iic";
599 reg = <0 0xe6500000 0 0x425>;
600 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cpg CPG_MOD 318>;
602 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
603 <&dmac1 0x61>, <&dmac1 0x62>;
604 dma-names = "tx", "rx", "tx", "rx";
605 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
606 resets = <&cpg 318>;
607 status = "disabled";
608 };
609
610 i2c8: i2c@e6510000 {
611 #address-cells = <1>;
612 #size-cells = <0>;
613 compatible = "renesas,iic-r8a7793",
614 "renesas,rcar-gen2-iic",
615 "renesas,rmobile-iic";
616 reg = <0 0xe6510000 0 0x425>;
617 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&cpg CPG_MOD 323>;
619 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
620 <&dmac1 0x65>, <&dmac1 0x66>;
621 dma-names = "tx", "rx", "tx", "rx";
622 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
623 resets = <&cpg 323>;
624 status = "disabled";
625 };
626
627 dmac0: dma-controller@e6700000 {
628 compatible = "renesas,dmac-r8a7793",
629 "renesas,rcar-dmac";
630 reg = <0 0xe6700000 0 0x20000>;
631 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "error",
648 "ch0", "ch1", "ch2", "ch3",
649 "ch4", "ch5", "ch6", "ch7",
650 "ch8", "ch9", "ch10", "ch11",
651 "ch12", "ch13", "ch14";
652 clocks = <&cpg CPG_MOD 219>;
653 clock-names = "fck";
654 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
655 resets = <&cpg 219>;
656 #dma-cells = <1>;
657 dma-channels = <15>;
658 };
659
660 dmac1: dma-controller@e6720000 {
661 compatible = "renesas,dmac-r8a7793",
662 "renesas,rcar-dmac";
663 reg = <0 0xe6720000 0 0x20000>;
664 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
680 interrupt-names = "error",
681 "ch0", "ch1", "ch2", "ch3",
682 "ch4", "ch5", "ch6", "ch7",
683 "ch8", "ch9", "ch10", "ch11",
684 "ch12", "ch13", "ch14";
685 clocks = <&cpg CPG_MOD 218>;
686 clock-names = "fck";
687 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
688 resets = <&cpg 218>;
689 #dma-cells = <1>;
690 dma-channels = <15>;
691 };
692
693 qspi: spi@e6b10000 {
694 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
695 reg = <0 0xe6b10000 0 0x2c>;
696 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&cpg CPG_MOD 917>;
698 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
699 <&dmac1 0x17>, <&dmac1 0x18>;
700 dma-names = "tx", "rx", "tx", "rx";
701 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
702 resets = <&cpg 917>;
703 num-cs = <1>;
704 #address-cells = <1>;
705 #size-cells = <0>;
706 status = "disabled";
707 };
708
709 scifa0: serial@e6c40000 {
710 compatible = "renesas,scifa-r8a7793",
711 "renesas,rcar-gen2-scifa", "renesas,scifa";
712 reg = <0 0xe6c40000 0 64>;
713 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&cpg CPG_MOD 204>;
715 clock-names = "fck";
716 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
717 <&dmac1 0x21>, <&dmac1 0x22>;
718 dma-names = "tx", "rx", "tx", "rx";
719 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
720 resets = <&cpg 204>;
721 status = "disabled";
722 };
723
724 scifa1: serial@e6c50000 {
725 compatible = "renesas,scifa-r8a7793",
726 "renesas,rcar-gen2-scifa", "renesas,scifa";
727 reg = <0 0xe6c50000 0 64>;
728 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&cpg CPG_MOD 203>;
730 clock-names = "fck";
731 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
732 <&dmac1 0x25>, <&dmac1 0x26>;
733 dma-names = "tx", "rx", "tx", "rx";
734 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
735 resets = <&cpg 203>;
736 status = "disabled";
737 };
738
739 scifa2: serial@e6c60000 {
740 compatible = "renesas,scifa-r8a7793",
741 "renesas,rcar-gen2-scifa", "renesas,scifa";
742 reg = <0 0xe6c60000 0 64>;
743 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&cpg CPG_MOD 202>;
745 clock-names = "fck";
746 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
747 <&dmac1 0x27>, <&dmac1 0x28>;
748 dma-names = "tx", "rx", "tx", "rx";
749 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
750 resets = <&cpg 202>;
751 status = "disabled";
752 };
753
754 scifa3: serial@e6c70000 {
755 compatible = "renesas,scifa-r8a7793",
756 "renesas,rcar-gen2-scifa", "renesas,scifa";
757 reg = <0 0xe6c70000 0 64>;
758 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&cpg CPG_MOD 1106>;
760 clock-names = "fck";
761 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
762 <&dmac1 0x1b>, <&dmac1 0x1c>;
763 dma-names = "tx", "rx", "tx", "rx";
764 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
765 resets = <&cpg 1106>;
766 status = "disabled";
767 };
768
769 scifa4: serial@e6c78000 {
770 compatible = "renesas,scifa-r8a7793",
771 "renesas,rcar-gen2-scifa", "renesas,scifa";
772 reg = <0 0xe6c78000 0 64>;
773 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cpg CPG_MOD 1107>;
775 clock-names = "fck";
776 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
777 <&dmac1 0x1f>, <&dmac1 0x20>;
778 dma-names = "tx", "rx", "tx", "rx";
779 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
780 resets = <&cpg 1107>;
781 status = "disabled";
782 };
783
784 scifa5: serial@e6c80000 {
785 compatible = "renesas,scifa-r8a7793",
786 "renesas,rcar-gen2-scifa", "renesas,scifa";
787 reg = <0 0xe6c80000 0 64>;
788 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&cpg CPG_MOD 1108>;
790 clock-names = "fck";
791 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
792 <&dmac1 0x23>, <&dmac1 0x24>;
793 dma-names = "tx", "rx", "tx", "rx";
794 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
795 resets = <&cpg 1108>;
796 status = "disabled";
797 };
798
799 scifb0: serial@e6c20000 {
800 compatible = "renesas,scifb-r8a7793",
801 "renesas,rcar-gen2-scifb", "renesas,scifb";
802 reg = <0 0xe6c20000 0 0x100>;
803 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&cpg CPG_MOD 206>;
805 clock-names = "fck";
806 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
807 <&dmac1 0x3d>, <&dmac1 0x3e>;
808 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
810 resets = <&cpg 206>;
811 status = "disabled";
812 };
813
814 scifb1: serial@e6c30000 {
815 compatible = "renesas,scifb-r8a7793",
816 "renesas,rcar-gen2-scifb", "renesas,scifb";
817 reg = <0 0xe6c30000 0 0x100>;
818 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&cpg CPG_MOD 207>;
820 clock-names = "fck";
821 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
822 <&dmac1 0x19>, <&dmac1 0x1a>;
823 dma-names = "tx", "rx", "tx", "rx";
824 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
825 resets = <&cpg 207>;
826 status = "disabled";
827 };
828
829 scifb2: serial@e6ce0000 {
830 compatible = "renesas,scifb-r8a7793",
831 "renesas,rcar-gen2-scifb", "renesas,scifb";
832 reg = <0 0xe6ce0000 0 0x100>;
833 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&cpg CPG_MOD 216>;
835 clock-names = "fck";
836 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
837 <&dmac1 0x1d>, <&dmac1 0x1e>;
838 dma-names = "tx", "rx", "tx", "rx";
839 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
840 resets = <&cpg 216>;
841 status = "disabled";
842 };
843
844 scif0: serial@e6e60000 {
845 compatible = "renesas,scif-r8a7793",
846 "renesas,rcar-gen2-scif", "renesas,scif";
847 reg = <0 0xe6e60000 0 64>;
848 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
850 <&scif_clk>;
851 clock-names = "fck", "brg_int", "scif_clk";
852 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
853 <&dmac1 0x29>, <&dmac1 0x2a>;
854 dma-names = "tx", "rx", "tx", "rx";
855 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
856 resets = <&cpg 721>;
857 status = "disabled";
858 };
859
860 scif1: serial@e6e68000 {
861 compatible = "renesas,scif-r8a7793",
862 "renesas,rcar-gen2-scif", "renesas,scif";
863 reg = <0 0xe6e68000 0 64>;
864 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
866 <&scif_clk>;
867 clock-names = "fck", "brg_int", "scif_clk";
868 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
869 <&dmac1 0x2d>, <&dmac1 0x2e>;
870 dma-names = "tx", "rx", "tx", "rx";
871 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
872 resets = <&cpg 720>;
873 status = "disabled";
874 };
875
876 scif2: serial@e6e58000 {
877 compatible = "renesas,scif-r8a7793",
878 "renesas,rcar-gen2-scif", "renesas,scif";
879 reg = <0 0xe6e58000 0 64>;
880 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
882 <&scif_clk>;
883 clock-names = "fck", "brg_int", "scif_clk";
884 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
885 <&dmac1 0x2b>, <&dmac1 0x2c>;
886 dma-names = "tx", "rx", "tx", "rx";
887 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
888 resets = <&cpg 719>;
889 status = "disabled";
890 };
891
892 scif3: serial@e6ea8000 {
893 compatible = "renesas,scif-r8a7793",
894 "renesas,rcar-gen2-scif", "renesas,scif";
895 reg = <0 0xe6ea8000 0 64>;
896 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
898 <&scif_clk>;
899 clock-names = "fck", "brg_int", "scif_clk";
900 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
901 <&dmac1 0x2f>, <&dmac1 0x30>;
902 dma-names = "tx", "rx", "tx", "rx";
903 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
904 resets = <&cpg 718>;
905 status = "disabled";
906 };
907
908 scif4: serial@e6ee0000 {
909 compatible = "renesas,scif-r8a7793",
910 "renesas,rcar-gen2-scif", "renesas,scif";
911 reg = <0 0xe6ee0000 0 64>;
912 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
914 <&scif_clk>;
915 clock-names = "fck", "brg_int", "scif_clk";
916 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
917 <&dmac1 0xfb>, <&dmac1 0xfc>;
918 dma-names = "tx", "rx", "tx", "rx";
919 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
920 resets = <&cpg 715>;
921 status = "disabled";
922 };
923
924 scif5: serial@e6ee8000 {
925 compatible = "renesas,scif-r8a7793",
926 "renesas,rcar-gen2-scif", "renesas,scif";
927 reg = <0 0xe6ee8000 0 64>;
928 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
930 <&scif_clk>;
931 clock-names = "fck", "brg_int", "scif_clk";
932 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
933 <&dmac1 0xfd>, <&dmac1 0xfe>;
934 dma-names = "tx", "rx", "tx", "rx";
935 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
936 resets = <&cpg 714>;
937 status = "disabled";
938 };
939
940 hscif0: serial@e62c0000 {
941 compatible = "renesas,hscif-r8a7793",
942 "renesas,rcar-gen2-hscif", "renesas,hscif";
943 reg = <0 0xe62c0000 0 96>;
944 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
946 <&scif_clk>;
947 clock-names = "fck", "brg_int", "scif_clk";
948 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
949 <&dmac1 0x39>, <&dmac1 0x3a>;
950 dma-names = "tx", "rx", "tx", "rx";
951 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
952 resets = <&cpg 717>;
953 status = "disabled";
954 };
955
956 hscif1: serial@e62c8000 {
957 compatible = "renesas,hscif-r8a7793",
958 "renesas,rcar-gen2-hscif", "renesas,hscif";
959 reg = <0 0xe62c8000 0 96>;
960 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
962 <&scif_clk>;
963 clock-names = "fck", "brg_int", "scif_clk";
964 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
965 <&dmac1 0x4d>, <&dmac1 0x4e>;
966 dma-names = "tx", "rx", "tx", "rx";
967 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
968 resets = <&cpg 716>;
969 status = "disabled";
970 };
971
972 hscif2: serial@e62d0000 {
973 compatible = "renesas,hscif-r8a7793",
974 "renesas,rcar-gen2-hscif", "renesas,hscif";
975 reg = <0 0xe62d0000 0 96>;
976 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
977 clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
978 <&scif_clk>;
979 clock-names = "fck", "brg_int", "scif_clk";
980 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
981 <&dmac1 0x3b>, <&dmac1 0x3c>;
982 dma-names = "tx", "rx", "tx", "rx";
983 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
984 resets = <&cpg 713>;
985 status = "disabled";
986 };
987
988 can0: can@e6e80000 {
989 compatible = "renesas,can-r8a7793",
990 "renesas,rcar-gen2-can";
991 reg = <0 0xe6e80000 0 0x1000>;
992 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
994 <&can_clk>;
995 clock-names = "clkp1", "clkp2", "can_clk";
996 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
997 resets = <&cpg 916>;
998 status = "disabled";
999 };
1000
1001 can1: can@e6e88000 {
1002 compatible = "renesas,can-r8a7793",
1003 "renesas,rcar-gen2-can";
1004 reg = <0 0xe6e88000 0 0x1000>;
1005 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
1007 <&can_clk>;
1008 clock-names = "clkp1", "clkp2", "can_clk";
1009 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1010 resets = <&cpg 915>;
1011 status = "disabled";
1012 };
1013
1014 vin0: video@e6ef0000 {
1015 compatible = "renesas,vin-r8a7793",
1016 "renesas,rcar-gen2-vin";
1017 reg = <0 0xe6ef0000 0 0x1000>;
1018 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&cpg CPG_MOD 811>;
1020 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1021 resets = <&cpg 811>;
1022 status = "disabled";
1023 };
1024
1025 vin1: video@e6ef1000 {
1026 compatible = "renesas,vin-r8a7793",
1027 "renesas,rcar-gen2-vin";
1028 reg = <0 0xe6ef1000 0 0x1000>;
1029 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&cpg CPG_MOD 810>;
1031 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1032 resets = <&cpg 810>;
1033 status = "disabled";
1034 };
1035
1036 vin2: video@e6ef2000 {
1037 compatible = "renesas,vin-r8a7793",
1038 "renesas,rcar-gen2-vin";
1039 reg = <0 0xe6ef2000 0 0x1000>;
1040 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&cpg CPG_MOD 809>;
1042 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1043 resets = <&cpg 809>;
1044 status = "disabled";
1045 };
1046
1047 rcar_sound: sound@ec500000 {
1048 /*
1049 * #sound-dai-cells is required if simple-card
1050 *
1051 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1052 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1053 */
1054 compatible = "renesas,rcar_sound-r8a7793",
1055 "renesas,rcar_sound-gen2";
1056 reg = <0 0xec500000 0 0x1000>, /* SCU */
1057 <0 0xec5a0000 0 0x100>, /* ADG */
1058 <0 0xec540000 0 0x1000>, /* SSIU */
1059 <0 0xec541000 0 0x280>, /* SSI */
1060 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1061 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1062
1063 clocks = <&cpg CPG_MOD 1005>,
1064 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1065 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1066 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1067 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1068 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1069 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1070 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1071 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1072 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1073 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1074 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1075 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
1076 <&cpg CPG_CORE R8A7793_CLK_M2>;
1077 clock-names = "ssi-all",
1078 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1079 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1080 "ssi.1", "ssi.0",
1081 "src.9", "src.8", "src.7", "src.6",
1082 "src.5", "src.4", "src.3", "src.2",
1083 "src.1", "src.0",
1084 "dvc.0", "dvc.1",
1085 "clk_a", "clk_b", "clk_c", "clk_i";
1086 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1087 resets = <&cpg 1005>,
1088 <&cpg 1006>, <&cpg 1007>,
1089 <&cpg 1008>, <&cpg 1009>,
1090 <&cpg 1010>, <&cpg 1011>,
1091 <&cpg 1012>, <&cpg 1013>,
1092 <&cpg 1014>, <&cpg 1015>;
1093 reset-names = "ssi-all",
1094 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1095 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1096 "ssi.1", "ssi.0";
1097
1098 status = "disabled";
1099
1100 rcar_sound,dvc {
1101 dvc0: dvc-0 {
1102 dmas = <&audma1 0xbc>;
1103 dma-names = "tx";
1104 };
1105 dvc1: dvc-1 {
1106 dmas = <&audma1 0xbe>;
1107 dma-names = "tx";
1108 };
1109 };
1110
1111 rcar_sound,src {
1112 src0: src-0 {
1113 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1114 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1115 dma-names = "rx", "tx";
1116 };
1117 src1: src-1 {
1118 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1120 dma-names = "rx", "tx";
1121 };
1122 src2: src-2 {
1123 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1124 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1125 dma-names = "rx", "tx";
1126 };
1127 src3: src-3 {
1128 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1129 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1130 dma-names = "rx", "tx";
1131 };
1132 src4: src-4 {
1133 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1134 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1135 dma-names = "rx", "tx";
1136 };
1137 src5: src-5 {
1138 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1139 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1140 dma-names = "rx", "tx";
1141 };
1142 src6: src-6 {
1143 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1144 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1145 dma-names = "rx", "tx";
1146 };
1147 src7: src-7 {
1148 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1149 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1150 dma-names = "rx", "tx";
1151 };
1152 src8: src-8 {
1153 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1154 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1155 dma-names = "rx", "tx";
1156 };
1157 src9: src-9 {
1158 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1159 dmas = <&audma0 0x97>, <&audma1 0xba>;
1160 dma-names = "rx", "tx";
1161 };
1162 };
1163
1164 rcar_sound,ssi {
1165 ssi0: ssi-0 {
1166 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1167 dmas = <&audma0 0x01>, <&audma1 0x02>,
1168 <&audma0 0x15>, <&audma1 0x16>;
1169 dma-names = "rx", "tx", "rxu", "txu";
1170 };
1171 ssi1: ssi-1 {
1172 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1173 dmas = <&audma0 0x03>, <&audma1 0x04>,
1174 <&audma0 0x49>, <&audma1 0x4a>;
1175 dma-names = "rx", "tx", "rxu", "txu";
1176 };
1177 ssi2: ssi-2 {
1178 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1179 dmas = <&audma0 0x05>, <&audma1 0x06>,
1180 <&audma0 0x63>, <&audma1 0x64>;
1181 dma-names = "rx", "tx", "rxu", "txu";
1182 };
1183 ssi3: ssi-3 {
1184 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&audma0 0x07>, <&audma1 0x08>,
1186 <&audma0 0x6f>, <&audma1 0x70>;
1187 dma-names = "rx", "tx", "rxu", "txu";
1188 };
1189 ssi4: ssi-4 {
1190 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1191 dmas = <&audma0 0x09>, <&audma1 0x0a>,
1192 <&audma0 0x71>, <&audma1 0x72>;
1193 dma-names = "rx", "tx", "rxu", "txu";
1194 };
1195 ssi5: ssi-5 {
1196 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1197 dmas = <&audma0 0x0b>, <&audma1 0x0c>,
1198 <&audma0 0x73>, <&audma1 0x74>;
1199 dma-names = "rx", "tx", "rxu", "txu";
1200 };
1201 ssi6: ssi-6 {
1202 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1203 dmas = <&audma0 0x0d>, <&audma1 0x0e>,
1204 <&audma0 0x75>, <&audma1 0x76>;
1205 dma-names = "rx", "tx", "rxu", "txu";
1206 };
1207 ssi7: ssi-7 {
1208 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1209 dmas = <&audma0 0x0f>, <&audma1 0x10>,
1210 <&audma0 0x79>, <&audma1 0x7a>;
1211 dma-names = "rx", "tx", "rxu", "txu";
1212 };
1213 ssi8: ssi-8 {
1214 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1215 dmas = <&audma0 0x11>, <&audma1 0x12>,
1216 <&audma0 0x7b>, <&audma1 0x7c>;
1217 dma-names = "rx", "tx", "rxu", "txu";
1218 };
1219 ssi9: ssi-9 {
1220 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1221 dmas = <&audma0 0x13>, <&audma1 0x14>,
1222 <&audma0 0x7d>, <&audma1 0x7e>;
1223 dma-names = "rx", "tx", "rxu", "txu";
1224 };
1225 };
1226 };
1227
1228 audma0: dma-controller@ec700000 {
1229 compatible = "renesas,dmac-r8a7793",
1230 "renesas,rcar-dmac";
1231 reg = <0 0xec700000 0 0x10000>;
1232 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1246 interrupt-names = "error",
1247 "ch0", "ch1", "ch2", "ch3",
1248 "ch4", "ch5", "ch6", "ch7",
1249 "ch8", "ch9", "ch10", "ch11",
1250 "ch12";
1251 clocks = <&cpg CPG_MOD 502>;
1252 clock-names = "fck";
1253 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1254 resets = <&cpg 502>;
1255 #dma-cells = <1>;
1256 dma-channels = <13>;
1257 };
1258
1259 audma1: dma-controller@ec720000 {
1260 compatible = "renesas,dmac-r8a7793",
1261 "renesas,rcar-dmac";
1262 reg = <0 0xec720000 0 0x10000>;
1263 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1277 interrupt-names = "error",
1278 "ch0", "ch1", "ch2", "ch3",
1279 "ch4", "ch5", "ch6", "ch7",
1280 "ch8", "ch9", "ch10", "ch11",
1281 "ch12";
1282 clocks = <&cpg CPG_MOD 501>;
1283 clock-names = "fck";
1284 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1285 resets = <&cpg 501>;
1286 #dma-cells = <1>;
1287 dma-channels = <13>;
1288 };
1289
1290 sdhi0: mmc@ee100000 {
1291 compatible = "renesas,sdhi-r8a7793",
1292 "renesas,rcar-gen2-sdhi";
1293 reg = <0 0xee100000 0 0x328>;
1294 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1295 clocks = <&cpg CPG_MOD 314>;
1296 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1297 <&dmac1 0xcd>, <&dmac1 0xce>;
1298 dma-names = "tx", "rx", "tx", "rx";
1299 max-frequency = <195000000>;
1300 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1301 resets = <&cpg 314>;
1302 status = "disabled";
1303 };
1304
1305 sdhi1: mmc@ee140000 {
1306 compatible = "renesas,sdhi-r8a7793",
1307 "renesas,rcar-gen2-sdhi";
1308 reg = <0 0xee140000 0 0x100>;
1309 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&cpg CPG_MOD 312>;
1311 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1312 <&dmac1 0xc1>, <&dmac1 0xc2>;
1313 dma-names = "tx", "rx", "tx", "rx";
1314 max-frequency = <97500000>;
1315 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1316 resets = <&cpg 312>;
1317 status = "disabled";
1318 };
1319
1320 sdhi2: mmc@ee160000 {
1321 compatible = "renesas,sdhi-r8a7793",
1322 "renesas,rcar-gen2-sdhi";
1323 reg = <0 0xee160000 0 0x100>;
1324 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1325 clocks = <&cpg CPG_MOD 311>;
1326 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1327 <&dmac1 0xd3>, <&dmac1 0xd4>;
1328 dma-names = "tx", "rx", "tx", "rx";
1329 max-frequency = <97500000>;
1330 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1331 resets = <&cpg 311>;
1332 status = "disabled";
1333 };
1334
1335 mmcif0: mmc@ee200000 {
1336 compatible = "renesas,mmcif-r8a7793",
1337 "renesas,sh-mmcif";
1338 reg = <0 0xee200000 0 0x80>;
1339 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1340 clocks = <&cpg CPG_MOD 315>;
1341 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1342 <&dmac1 0xd1>, <&dmac1 0xd2>;
1343 dma-names = "tx", "rx", "tx", "rx";
1344 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1345 resets = <&cpg 315>;
1346 reg-io-width = <4>;
1347 status = "disabled";
1348 max-frequency = <97500000>;
1349 };
1350
1351 ether: ethernet@ee700000 {
1352 compatible = "renesas,ether-r8a7793",
1353 "renesas,rcar-gen2-ether";
1354 reg = <0 0xee700000 0 0x400>;
1355 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1356 clocks = <&cpg CPG_MOD 813>;
1357 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1358 resets = <&cpg 813>;
1359 phy-mode = "rmii";
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1362 status = "disabled";
1363 };
1364
1365 gic: interrupt-controller@f1001000 {
1366 compatible = "arm,gic-400";
1367 #interrupt-cells = <3>;
1368 #address-cells = <0>;
1369 interrupt-controller;
1370 reg = <0 0xf1001000 0 0x1000>,
1371 <0 0xf1002000 0 0x2000>,
1372 <0 0xf1004000 0 0x2000>,
1373 <0 0xf1006000 0 0x2000>;
1374 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1375 clocks = <&cpg CPG_MOD 408>;
1376 clock-names = "clk";
1377 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1378 resets = <&cpg 408>;
1379 };
1380
1381 fdp1@fe940000 {
1382 compatible = "renesas,fdp1";
1383 reg = <0 0xfe940000 0 0x2400>;
1384 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1385 clocks = <&cpg CPG_MOD 119>;
1386 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1387 resets = <&cpg 119>;
1388 };
1389
1390 fdp1@fe944000 {
1391 compatible = "renesas,fdp1";
1392 reg = <0 0xfe944000 0 0x2400>;
1393 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&cpg CPG_MOD 118>;
1395 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1396 resets = <&cpg 118>;
1397 };
1398
1399 du: display@feb00000 {
1400 compatible = "renesas,du-r8a7793";
1401 reg = <0 0xfeb00000 0 0x40000>;
1402 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1405 clock-names = "du.0", "du.1";
1406 resets = <&cpg 724>;
1407 reset-names = "du.0";
1408 status = "disabled";
1409
1410 ports {
1411 #address-cells = <1>;
1412 #size-cells = <0>;
1413
1414 port@0 {
1415 reg = <0>;
1416 du_out_rgb: endpoint {
1417 };
1418 };
1419 port@1 {
1420 reg = <1>;
1421 du_out_lvds0: endpoint {
1422 remote-endpoint = <&lvds0_in>;
1423 };
1424 };
1425 };
1426 };
1427
1428 lvds0: lvds@feb90000 {
1429 compatible = "renesas,r8a7793-lvds";
1430 reg = <0 0xfeb90000 0 0x1c>;
1431 clocks = <&cpg CPG_MOD 726>;
1432 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1433 resets = <&cpg 726>;
1434
1435 status = "disabled";
1436
1437 ports {
1438 #address-cells = <1>;
1439 #size-cells = <0>;
1440
1441 port@0 {
1442 reg = <0>;
1443 lvds0_in: endpoint {
1444 remote-endpoint = <&du_out_lvds0>;
1445 };
1446 };
1447 port@1 {
1448 reg = <1>;
1449 lvds0_out: endpoint {
1450 };
1451 };
1452 };
1453 };
1454
1455 prr: chipid@ff000044 {
1456 compatible = "renesas,prr";
1457 reg = <0 0xff000044 0 4>;
1458 };
1459
1460 cmt0: timer@ffca0000 {
1461 compatible = "renesas,r8a7793-cmt0",
1462 "renesas,rcar-gen2-cmt0";
1463 reg = <0 0xffca0000 0 0x1004>;
1464 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1466 clocks = <&cpg CPG_MOD 124>;
1467 clock-names = "fck";
1468 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1469 resets = <&cpg 124>;
1470
1471 status = "disabled";
1472 };
1473
1474 cmt1: timer@e6130000 {
1475 compatible = "renesas,r8a7793-cmt1",
1476 "renesas,rcar-gen2-cmt1";
1477 reg = <0 0xe6130000 0 0x1004>;
1478 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1486 clocks = <&cpg CPG_MOD 329>;
1487 clock-names = "fck";
1488 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1489 resets = <&cpg 329>;
1490
1491 status = "disabled";
1492 };
1493 };
1494
1495 thermal-zones {
1496 cpu_thermal: cpu-thermal {
1497 polling-delay-passive = <0>;
1498 polling-delay = <0>;
1499
1500 thermal-sensors = <&thermal>;
1501
1502 trips {
1503 cpu-crit {
1504 temperature = <95000>;
1505 hysteresis = <0>;
1506 type = "critical";
1507 };
1508 };
1509 cooling-maps {
1510 };
1511 };
1512 };
1513
1514 timer {
1515 compatible = "arm,armv7-timer";
1516 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1517 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1518 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1519 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1520 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
1521 };
1522
1523 /* External USB clock - can be overridden by the board */
1524 usb_extal_clk: usb_extal {
1525 compatible = "fixed-clock";
1526 #clock-cells = <0>;
1527 clock-frequency = <48000000>;
1528 };
1529 };
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