1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Google Veyron Fievel Rev 0+ board device tree source
4 *
5 * Copyright 2016 Google, Inc
6 */
7
8 /dts-v1/;
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-analog-audio.dtsi"
11
12 / {
13 model = "Google Fievel";
14 compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
15 "google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
16 "google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
17 "google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
18 "google,veyron-fievel-rev0", "google,veyron-fievel",
19 "google,veyron", "rockchip,rk3288";
20
21 vccsys: vccsys {
22 compatible = "regulator-fixed";
23 regulator-name = "vccsys";
24 regulator-boot-on;
25 regulator-always-on;
26 };
27
28 /*
29 * vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys,
30 * enabled by vcc_18
31 */
32 vcc33_io: vcc33-io {
33 compatible = "regulator-fixed";
34 regulator-always-on;
35 regulator-boot-on;
36 regulator-name = "vcc33_io";
37 };
38
39 vcc5_host1: vcc5-host1-regulator {
40 compatible = "regulator-fixed";
41 enable-active-high;
42 gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&hub_usb1_pwr_en>;
45 regulator-name = "vcc5_host1";
46 regulator-always-on;
47 regulator-boot-on;
48 };
49
50 vcc5_host2: vcc5-host2-regulator {
51 compatible = "regulator-fixed";
52 enable-active-high;
53 gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>;
54 pinctrl-names = "default";
55 pinctrl-0 = <&hub_usb2_pwr_en>;
56 regulator-name = "vcc5_host2";
57 regulator-always-on;
58 regulator-boot-on;
59 };
60
61 vcc5v_otg: vcc5v-otg-regulator {
62 compatible = "regulator-fixed";
63 enable-active-high;
64 gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&usb_otg_pwr_en>;
67 regulator-name = "vcc5_otg";
68 regulator-always-on;
69 regulator-boot-on;
70 };
71
72 ext_gmac: external-gmac-clock {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <125000000>;
76 clock-output-names = "ext_gmac";
77 };
78 };
79
80 &gmac {
81 status = "okay";
82
83 assigned-clocks = <&cru SCLK_MAC>;
84 assigned-clock-parents = <&ext_gmac>;
85 clock_in_out = "input";
86 phy-handle = <ðphy>;
87 phy-mode = "rgmii";
88 phy-supply = <&vcc33_lan>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
91 rx_delay = <0x10>;
92 tx_delay = <0x30>;
93
94 /*
95 * Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low)
96 * with a 30ms settling time.
97 */
98 snps,reset-gpio = <&gpio4 RK_PB0 0>;
99 snps,reset-active-low;
100 snps,reset-delays-us = <0 10000 30000>;
101 wakeup-source;
102
103 mdio0 {
104 compatible = "snps,dwmac-mdio";
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 ethphy: ethernet-phy@1 {
109 reg = <1>;
110 };
111 };
112 };
113
114 &rk808 {
115 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
116 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
119
120 vcc6-supply = <&vcc33_sys>;
121 vcc10-supply = <&vcc33_sys>;
122 vcc11-supply = <&vcc_5v>;
123 vcc12-supply = <&vcc33_sys>;
124
125 regulators {
126 /delete-node/ LDO_REG1;
127
128 /*
129 * According to the schematic, vcc18_lcdt is for
130 * HDMI_AVDD_1V8
131 */
132 vcc18_lcdt: LDO_REG2 {
133 regulator-always-on;
134 regulator-boot-on;
135 regulator-min-microvolt = <1800000>;
136 regulator-max-microvolt = <1800000>;
137 regulator-name = "vdd18_lcdt";
138 regulator-state-mem {
139 regulator-off-in-suspend;
140 };
141 };
142
143 /*
144 * This is not a pwren anymore, but the real power supply,
145 * vdd10_lcd for HDMI_AVDD_1V0
146 */
147 vdd10_lcd: LDO_REG7 {
148 regulator-always-on;
149 regulator-boot-on;
150 regulator-min-microvolt = <1000000>;
151 regulator-max-microvolt = <1000000>;
152 regulator-name = "vdd10_lcd";
153 regulator-state-mem {
154 regulator-off-in-suspend;
155 };
156 };
157
158 /* for usb camera */
159 vcc33_ccd: LDO_REG8 {
160 regulator-always-on;
161 regulator-boot-on;
162 regulator-min-microvolt = <3300000>;
163 regulator-max-microvolt = <3300000>;
164 regulator-name = "vcc33_ccd";
165 regulator-state-mem {
166 regulator-off-in-suspend;
167 };
168 };
169
170 vcc33_lan: SWITCH_REG2 {
171 regulator-name = "vcc33_lan";
172 };
173 };
174 };
175
176 &sdio0 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 btmrvl: btmrvl@2 {
181 compatible = "marvell,sd8897-bt";
182 reg = <2>;
183 interrupt-parent = <&gpio4>;
184 interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
185 marvell,wakeup-pin = /bits/ 16 <13>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&bt_host_wake_l>;
188 };
189 };
190
191 &vcc50_hdmi {
192 enable-active-high;
193 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&vcc50_hdmi_en>;
196 };
197
198 &vcc_5v {
199 enable-active-high;
200 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&drv_5v>;
203 };
204
205 &gpio0 {
206 gpio-line-names = "PMIC_SLEEP_AP",
207 "DDRIO_PWROFF",
208 "DDRIO_RETEN",
209 "TS3A227E_INT_L",
210 "PMIC_INT_L",
211 "PWR_KEY_L",
212 "HUB_USB1_nFALUT",
213 "PHY_PMEB",
214
215 "PHY_INT",
216 /*
217 * RECOVERY_SW_L is Chrome OS ABI. Schematics call
218 * it REC_MODE_L.
219 */
220 "RECOVERY_SW_L",
221 "OTP_OUT",
222 "",
223 "USB_OTG_POWER_EN",
224 "AP_WARM_RESET_H",
225 "USB_OTG_nFALUT",
226 "I2C0_SDA_PMIC",
227
228 "I2C0_SCL_PMIC",
229 "DEVMODE_L",
230 "USB_INT";
231 };
232
233 &gpio2 {
234 gpio-line-names = "CONFIG0",
235 "CONFIG1",
236 "CONFIG2",
237 "",
238 "",
239 "",
240 "",
241 "CONFIG3",
242
243 "",
244 "EMMC_RST_L",
245 "",
246 "",
247 "BL_PWR_EN",
248 "",
249 "TOUCH_INT",
250 "TOUCH_RST",
251
252 "I2C3_SCL_TP",
253 "I2C3_SDA_TP";
254 };
255
256 &gpio3 {
257 gpio-line-names = "FLASH0_D0",
258 "FLASH0_D1",
259 "FLASH0_D2",
260 "FLASH0_D3",
261 "FLASH0_D4",
262 "FLASH0_D5",
263 "FLASH0_D6",
264 "FLASH0_D7",
265
266 "VCC5V_GOOD_H",
267 "",
268 "",
269 "",
270 "",
271 "",
272 "",
273 "",
274
275 "FLASH0_CS2/EMMC_CMD",
276 "",
277 "FLASH0_DQS/EMMC_CLKO",
278 "",
279 "",
280 "",
281 "",
282 "",
283
284 "PHY_TXD2",
285 "PHY_TXD3",
286 "MAC_RXD2",
287 "MAC_RXD3",
288 "PHY_TXD0",
289 "PHY_TXD1",
290 "MAC_RXD0",
291 "MAC_RXD1";
292 };
293
294 &gpio4 {
295 gpio-line-names = "MAC_MDC",
296 "MAC_RXDV",
297 "MAC_RXER",
298 "MAC_CLK",
299 "PHY_TXEN",
300 "MAC_MDIO",
301 "MAC_RXCLK",
302 "",
303
304 "PHY_RST",
305 "PHY_TXCLK",
306 "",
307 "",
308 "",
309 "",
310 "",
311 "",
312
313 "UART0_RXD",
314 "UART0_TXD",
315 "UART0_CTS_L",
316 "UART0_RTS_L",
317 "SDIO0_D0",
318 "SDIO0_D1",
319 "SDIO0_D2",
320 "SDIO0_D3",
321
322 "SDIO0_CMD",
323 "SDIO0_CLK",
324 "BT_DEV_WAKE",
325 "",
326 "WIFI_ENABLE_H",
327 "BT_ENABLE_L",
328 "WIFI_HOST_WAKE",
329 "BT_HOST_WAKE";
330 };
331
332 &gpio5 {
333 gpio-line-names = "",
334 "",
335 "",
336 "",
337 "",
338 "",
339 "",
340 "",
341
342 "",
343 "",
344 "",
345 "",
346 "USB_OTG_CTL1",
347 "HUB_USB2_CTL1",
348 "HUB_USB2_PWR_EN",
349 "HUB_USB_ILIM_SEL",
350
351 "USB_OTG_STATUS_L",
352 "HUB_USB1_CTL1",
353 "HUB_USB1_PWR_EN",
354 "VCC50_HDMI_EN";
355 };
356
357 &gpio6 {
358 gpio-line-names = "I2S0_SCLK",
359 "I2S0_LRCK_RX",
360 "I2S0_LRCK_TX",
361 "I2S0_SDI",
362 "I2S0_SDO0",
363 "HP_DET_H",
364 "",
365 "INT_CODEC",
366
367 "I2S0_CLK",
368 "I2C2_SDA",
369 "I2C2_SCL",
370 "MICDET",
371 "",
372 "",
373 "",
374 "",
375
376 "HUB_USB2_nFALUT",
377 "USB_OTG_ILIM_SEL";
378 };
379
380 &gpio7 {
381 gpio-line-names = "LCD_BL_PWM",
382 "PWM_LOG",
383 "BL_EN",
384 "PWR_LED1",
385 "TPM_INT_H",
386 "SPK_ON",
387 /*
388 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
389 * it FW_WP_AP.
390 */
391 "AP_FLASH_WP_L",
392 "",
393
394 "CPU_NMI",
395 "DVSOK",
396 "",
397 "EDP_HPD",
398 "DVS1",
399 "",
400 "LCD_EN",
401 "DVS2",
402
403 "HDMI_CEC",
404 "I2C4_SDA",
405 "I2C4_SCL",
406 "I2C5_SDA_HDMI",
407 "I2C5_SCL_HDMI",
408 "5V_DRV",
409 "UART2_RXD",
410 "UART2_TXD";
411 };
412
413 &gpio8 {
414 gpio-line-names = "RAM_ID0",
415 "RAM_ID1",
416 "RAM_ID2",
417 "RAM_ID3",
418 "I2C1_SDA_TPM",
419 "I2C1_SCL_TPM",
420 "SPI2_CLK",
421 "SPI2_CS0",
422
423 "SPI2_RXD",
424 "SPI2_TXD";
425 };
426
427 &pinctrl {
428 pinctrl-names = "default", "sleep";
429 pinctrl-0 = <
430 /* Common for sleep and wake, but no owners */
431 &ddr0_retention
432 &ddrio_pwroff
433 &global_pwroff
434
435 /* For usb bc1.2 */
436 &usb_otg_ilim_sel
437 &usb_usb_ilim_sel
438
439 /* Wake only */
440 &bt_dev_wake_awake
441 &pwr_led1_on
442 >;
443
444 pinctrl-1 = <
445 /* Common for sleep and wake, but no owners */
446 &ddr0_retention
447 &ddrio_pwroff
448 &global_pwroff
449
450 /* For usb bc1.2 */
451 &usb_otg_ilim_sel
452 &usb_usb_ilim_sel
453
454 /* Sleep only */
455 &bt_dev_wake_sleep
456 &pwr_led1_blink
457 >;
458
459 buck-5v {
460 drv_5v: drv-5v {
461 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
462 };
463 };
464
465 gmac {
466 phy_rst: phy-rst {
467 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
468 };
469
470 phy_pmeb: phy-pmeb {
471 rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
472 };
473
474 phy_int: phy-int {
475 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
476 };
477 };
478
479 hdmi {
480 vcc50_hdmi_en: vcc50-hdmi-en {
481 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
482 };
483 };
484
485 leds {
486 pwr_led1_on: pwr-led1-on {
487 rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
488 };
489
490 pwr_led1_blink: pwr-led1-blink {
491 rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
492 };
493 };
494
495 pmic {
496 dvs_1: dvs-1 {
497 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
498 };
499
500 dvs_2: dvs-2 {
501 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
502 };
503 };
504
505 usb-bc12 {
506 usb_otg_ilim_sel: usb-otg-ilim-sel {
507 rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
508 };
509
510 usb_usb_ilim_sel: usb-usb-ilim-sel {
511 rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
512 };
513 };
514
515 usb-host {
516 hub_usb1_pwr_en: hub_usb1_pwr_en {
517 rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
518 };
519
520 hub_usb2_pwr_en: hub_usb2_pwr_en {
521 rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
522 };
523
524 usb_otg_pwr_en: usb_otg_pwr_en {
525 rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
526 };
527 };
528 };
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