1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 */
6
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 interrupt-parent = <&gic>;
16
17 aliases {
18 ethernet0 = &emac;
19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
22 gpio3 = &gpio3;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &uart2;
31 serial3 = &uart3;
32 spi0 = &spi0;
33 spi1 = &spi1;
34 };
35
36 xin24m: oscillator {
37 compatible = "fixed-clock";
38 clock-frequency = <24000000>;
39 #clock-cells = <0>;
40 clock-output-names = "xin24m";
41 };
42
43 gpu: gpu@10090000 {
44 compatible = "arm,mali-400";
45 reg = <0x10090000 0x10000>;
46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
47 clock-names = "bus", "core";
48 assigned-clocks = <&cru ACLK_GPU>;
49 assigned-clock-rates = <100000000>;
50 resets = <&cru SRST_GPU>;
51 status = "disabled";
52 };
53
54 vpu: video-codec@10104000 {
55 compatible = "rockchip,rk3066-vpu";
56 reg = <0x10104000 0x800>;
57 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-names = "vepu", "vdpu";
60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
62 clock-names = "aclk_vdpu", "hclk_vdpu",
63 "aclk_vepu", "hclk_vepu";
64 };
65
66 L2: cache-controller@10138000 {
67 compatible = "arm,pl310-cache";
68 reg = <0x10138000 0x1000>;
69 cache-unified;
70 cache-level = <2>;
71 };
72
73 scu@1013c000 {
74 compatible = "arm,cortex-a9-scu";
75 reg = <0x1013c000 0x100>;
76 };
77
78 global_timer: global-timer@1013c200 {
79 compatible = "arm,cortex-a9-global-timer";
80 reg = <0x1013c200 0x20>;
81 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
82 clocks = <&cru CORE_PERI>;
83 status = "disabled";
84 /* The clock source and the sched_clock provided by the arm_global_timer
85 * on Rockchip rk3066a/rk3188 are quite unstable because their rates
86 * depend on the CPU frequency.
87 * Keep the arm_global_timer disabled in order to have the
88 * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
89 */
90 };
91
92 local_timer: local-timer@1013c600 {
93 compatible = "arm,cortex-a9-twd-timer";
94 reg = <0x1013c600 0x20>;
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
96 clocks = <&cru CORE_PERI>;
97 };
98
99 gic: interrupt-controller@1013d000 {
100 compatible = "arm,cortex-a9-gic";
101 interrupt-controller;
102 #interrupt-cells = <3>;
103 reg = <0x1013d000 0x1000>,
104 <0x1013c100 0x0100>;
105 };
106
107 uart0: serial@10124000 {
108 compatible = "snps,dw-apb-uart";
109 reg = <0x10124000 0x400>;
110 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
111 reg-shift = <2>;
112 reg-io-width = <1>;
113 clock-names = "baudclk", "apb_pclk";
114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
115 status = "disabled";
116 };
117
118 uart1: serial@10126000 {
119 compatible = "snps,dw-apb-uart";
120 reg = <0x10126000 0x400>;
121 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
122 reg-shift = <2>;
123 reg-io-width = <1>;
124 clock-names = "baudclk", "apb_pclk";
125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
126 status = "disabled";
127 };
128
129 qos_gpu: qos@1012d000 {
130 compatible = "rockchip,rk3066-qos", "syscon";
131 reg = <0x1012d000 0x20>;
132 };
133
134 qos_vpu: qos@1012e000 {
135 compatible = "rockchip,rk3066-qos", "syscon";
136 reg = <0x1012e000 0x20>;
137 };
138
139 qos_lcdc0: qos@1012f000 {
140 compatible = "rockchip,rk3066-qos", "syscon";
141 reg = <0x1012f000 0x20>;
142 };
143
144 qos_cif0: qos@1012f080 {
145 compatible = "rockchip,rk3066-qos", "syscon";
146 reg = <0x1012f080 0x20>;
147 };
148
149 qos_ipp: qos@1012f100 {
150 compatible = "rockchip,rk3066-qos", "syscon";
151 reg = <0x1012f100 0x20>;
152 };
153
154 qos_lcdc1: qos@1012f180 {
155 compatible = "rockchip,rk3066-qos", "syscon";
156 reg = <0x1012f180 0x20>;
157 };
158
159 qos_cif1: qos@1012f200 {
160 compatible = "rockchip,rk3066-qos", "syscon";
161 reg = <0x1012f200 0x20>;
162 };
163
164 qos_rga: qos@1012f280 {
165 compatible = "rockchip,rk3066-qos", "syscon";
166 reg = <0x1012f280 0x20>;
167 };
168
169 usb_otg: usb@10180000 {
170 compatible = "rockchip,rk3066-usb", "snps,dwc2";
171 reg = <0x10180000 0x40000>;
172 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cru HCLK_OTG0>;
174 clock-names = "otg";
175 dr_mode = "otg";
176 g-np-tx-fifo-size = <16>;
177 g-rx-fifo-size = <275>;
178 g-tx-fifo-size = <256 128 128 64 64 32>;
179 phys = <&usbphy0>;
180 phy-names = "usb2-phy";
181 status = "disabled";
182 };
183
184 usb_host: usb@101c0000 {
185 compatible = "snps,dwc2";
186 reg = <0x101c0000 0x40000>;
187 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&cru HCLK_OTG1>;
189 clock-names = "otg";
190 dr_mode = "host";
191 phys = <&usbphy1>;
192 phy-names = "usb2-phy";
193 status = "disabled";
194 };
195
196 emac: ethernet@10204000 {
197 compatible = "rockchip,rk3066-emac";
198 reg = <0x10204000 0x3c>;
199 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
201 clock-names = "hclk", "macref";
202 max-speed = <100>;
203 phy-mode = "rmii";
204 rockchip,grf = <&grf>;
205 status = "disabled";
206 };
207
208 mmc0: mmc@10214000 {
209 compatible = "rockchip,rk2928-dw-mshc";
210 reg = <0x10214000 0x1000>;
211 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
213 clock-names = "biu", "ciu";
214 dmas = <&dmac2 1>;
215 dma-names = "rx-tx";
216 fifo-depth = <256>;
217 resets = <&cru SRST_SDMMC>;
218 reset-names = "reset";
219 status = "disabled";
220 };
221
222 mmc1: mmc@10218000 {
223 compatible = "rockchip,rk2928-dw-mshc";
224 reg = <0x10218000 0x1000>;
225 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
227 clock-names = "biu", "ciu";
228 dmas = <&dmac2 3>;
229 dma-names = "rx-tx";
230 fifo-depth = <256>;
231 resets = <&cru SRST_SDIO>;
232 reset-names = "reset";
233 status = "disabled";
234 };
235
236 emmc: mmc@1021c000 {
237 compatible = "rockchip,rk2928-dw-mshc";
238 reg = <0x1021c000 0x1000>;
239 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
241 clock-names = "biu", "ciu";
242 dmas = <&dmac2 4>;
243 dma-names = "rx-tx";
244 fifo-depth = <256>;
245 resets = <&cru SRST_EMMC>;
246 reset-names = "reset";
247 status = "disabled";
248 };
249
250 nfc: nand-controller@10500000 {
251 compatible = "rockchip,rk2928-nfc";
252 reg = <0x10500000 0x4000>;
253 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cru HCLK_NANDC0>;
255 clock-names = "ahb";
256 status = "disabled";
257 };
258
259 pmu: pmu@20004000 {
260 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
261 reg = <0x20004000 0x100>;
262
263 reboot-mode {
264 compatible = "syscon-reboot-mode";
265 offset = <0x40>;
266 mode-normal = <BOOT_NORMAL>;
267 mode-recovery = <BOOT_RECOVERY>;
268 mode-bootloader = <BOOT_FASTBOOT>;
269 mode-loader = <BOOT_BL_DOWNLOAD>;
270 };
271 };
272
273 grf: grf@20008000 {
274 compatible = "syscon", "simple-mfd";
275 reg = <0x20008000 0x200>;
276 };
277
278 dmac1_s: dma-controller@20018000 {
279 compatible = "arm,pl330", "arm,primecell";
280 reg = <0x20018000 0x4000>;
281 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
283 #dma-cells = <1>;
284 arm,pl330-broken-no-flushp;
285 arm,pl330-periph-burst;
286 clocks = <&cru ACLK_DMA1>;
287 clock-names = "apb_pclk";
288 };
289
290 dmac1_ns: dma-controller@2001c000 {
291 compatible = "arm,pl330", "arm,primecell";
292 reg = <0x2001c000 0x4000>;
293 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
295 #dma-cells = <1>;
296 arm,pl330-broken-no-flushp;
297 arm,pl330-periph-burst;
298 clocks = <&cru ACLK_DMA1>;
299 clock-names = "apb_pclk";
300 status = "disabled";
301 };
302
303 i2c0: i2c@2002d000 {
304 compatible = "rockchip,rk3066-i2c";
305 reg = <0x2002d000 0x1000>;
306 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309
310 rockchip,grf = <&grf>;
311
312 clock-names = "i2c";
313 clocks = <&cru PCLK_I2C0>;
314
315 status = "disabled";
316 };
317
318 i2c1: i2c@2002f000 {
319 compatible = "rockchip,rk3066-i2c";
320 reg = <0x2002f000 0x1000>;
321 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324
325 rockchip,grf = <&grf>;
326
327 clocks = <&cru PCLK_I2C1>;
328 clock-names = "i2c";
329
330 status = "disabled";
331 };
332
333 pwm0: pwm@20030000 {
334 compatible = "rockchip,rk2928-pwm";
335 reg = <0x20030000 0x10>;
336 #pwm-cells = <2>;
337 clocks = <&cru PCLK_PWM01>;
338 status = "disabled";
339 };
340
341 pwm1: pwm@20030010 {
342 compatible = "rockchip,rk2928-pwm";
343 reg = <0x20030010 0x10>;
344 #pwm-cells = <2>;
345 clocks = <&cru PCLK_PWM01>;
346 status = "disabled";
347 };
348
349 wdt: watchdog@2004c000 {
350 compatible = "snps,dw-wdt";
351 reg = <0x2004c000 0x100>;
352 clocks = <&cru PCLK_WDT>;
353 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
354 status = "disabled";
355 };
356
357 pwm2: pwm@20050020 {
358 compatible = "rockchip,rk2928-pwm";
359 reg = <0x20050020 0x10>;
360 #pwm-cells = <2>;
361 clocks = <&cru PCLK_PWM23>;
362 status = "disabled";
363 };
364
365 pwm3: pwm@20050030 {
366 compatible = "rockchip,rk2928-pwm";
367 reg = <0x20050030 0x10>;
368 #pwm-cells = <2>;
369 clocks = <&cru PCLK_PWM23>;
370 status = "disabled";
371 };
372
373 i2c2: i2c@20056000 {
374 compatible = "rockchip,rk3066-i2c";
375 reg = <0x20056000 0x1000>;
376 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379
380 rockchip,grf = <&grf>;
381
382 clocks = <&cru PCLK_I2C2>;
383 clock-names = "i2c";
384
385 status = "disabled";
386 };
387
388 i2c3: i2c@2005a000 {
389 compatible = "rockchip,rk3066-i2c";
390 reg = <0x2005a000 0x1000>;
391 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
392 #address-cells = <1>;
393 #size-cells = <0>;
394
395 rockchip,grf = <&grf>;
396
397 clocks = <&cru PCLK_I2C3>;
398 clock-names = "i2c";
399
400 status = "disabled";
401 };
402
403 i2c4: i2c@2005e000 {
404 compatible = "rockchip,rk3066-i2c";
405 reg = <0x2005e000 0x1000>;
406 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409
410 rockchip,grf = <&grf>;
411
412 clocks = <&cru PCLK_I2C4>;
413 clock-names = "i2c";
414
415 status = "disabled";
416 };
417
418 uart2: serial@20064000 {
419 compatible = "snps,dw-apb-uart";
420 reg = <0x20064000 0x400>;
421 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
422 reg-shift = <2>;
423 reg-io-width = <1>;
424 clock-names = "baudclk", "apb_pclk";
425 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
426 status = "disabled";
427 };
428
429 uart3: serial@20068000 {
430 compatible = "snps,dw-apb-uart";
431 reg = <0x20068000 0x400>;
432 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
433 reg-shift = <2>;
434 reg-io-width = <1>;
435 clock-names = "baudclk", "apb_pclk";
436 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
437 status = "disabled";
438 };
439
440 saradc: saradc@2006c000 {
441 compatible = "rockchip,saradc";
442 reg = <0x2006c000 0x100>;
443 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
444 #io-channel-cells = <1>;
445 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
446 clock-names = "saradc", "apb_pclk";
447 resets = <&cru SRST_SARADC>;
448 reset-names = "saradc-apb";
449 status = "disabled";
450 };
451
452 spi0: spi@20070000 {
453 compatible = "rockchip,rk3066-spi";
454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
455 clock-names = "spiclk", "apb_pclk";
456 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
457 reg = <0x20070000 0x1000>;
458 #address-cells = <1>;
459 #size-cells = <0>;
460 dmas = <&dmac2 10>, <&dmac2 11>;
461 dma-names = "tx", "rx";
462 status = "disabled";
463 };
464
465 spi1: spi@20074000 {
466 compatible = "rockchip,rk3066-spi";
467 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
468 clock-names = "spiclk", "apb_pclk";
469 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
470 reg = <0x20074000 0x1000>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 dmas = <&dmac2 12>, <&dmac2 13>;
474 dma-names = "tx", "rx";
475 status = "disabled";
476 };
477
478 dmac2: dma-controller@20078000 {
479 compatible = "arm,pl330", "arm,primecell";
480 reg = <0x20078000 0x4000>;
481 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
483 #dma-cells = <1>;
484 arm,pl330-broken-no-flushp;
485 arm,pl330-periph-burst;
486 clocks = <&cru ACLK_DMA2>;
487 clock-names = "apb_pclk";
488 };
489 };
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